1 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // InstrSchedModel annotations for out-of-order CPUs.
12 // Instructions with folded loads need to read the memory operand immediately,
13 // but other register operands don't have to be read until the load is ready.
14 // These operands are marked with ReadAfterLd.
15 def ReadAfterLd : SchedRead;
16 def ReadAfterVecLd : SchedRead;
17 def ReadAfterVecXLd : SchedRead;
18 def ReadAfterVecYLd : SchedRead;
20 // Instructions that move data between general purpose registers and vector
21 // registers may be subject to extra latency due to data bypass delays.
22 // This SchedRead describes a bypass delay caused by data being moved from the
23 // integer unit to the floating point unit.
24 def ReadInt2Fpu : SchedRead;
26 // Instructions with both a load and a store folded are modeled as a folded
28 def WriteRMW : SchedWrite;
30 // Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
31 multiclass X86WriteRes<SchedWrite SchedRW,
32 list<ProcResourceKind> ExePorts,
33 int Lat, list<int> Res, int UOps> {
34 def : WriteRes<SchedRW, ExePorts> {
36 let ResourceCycles = Res;
37 let NumMicroOps = UOps;
41 // Most instructions can fold loads, so almost every SchedWrite comes in two
42 // variants: With and without a folded load.
43 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
44 // with a folded load.
45 class X86FoldableSchedWrite : SchedWrite {
46 // The SchedWrite to use when a load is folded into the instruction.
48 // The SchedRead to tag register operands than don't need to be ready
49 // until the folded load has completed.
50 SchedRead ReadAfterFold;
53 // Multiclass that produces a linked pair of SchedWrites.
54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
55 // Register-Memory operation.
57 // Register-Register operation.
58 def NAME : X86FoldableSchedWrite {
59 let Folded = !cast<SchedWrite>(NAME#"Ld");
60 let ReadAfterFold = ReadAfter;
64 // Helpers to mark SchedWrites as unsupported.
65 multiclass X86WriteResUnsupported<SchedWrite SchedRW> {
66 let Unsupported = 1 in {
67 def : WriteRes<SchedRW, []>;
70 multiclass X86WriteResPairUnsupported<X86FoldableSchedWrite SchedRW> {
71 let Unsupported = 1 in {
72 def : WriteRes<SchedRW, []>;
73 def : WriteRes<SchedRW.Folded, []>;
77 // Multiclass that wraps X86FoldableSchedWrite for each vector width.
78 class X86SchedWriteWidths<X86FoldableSchedWrite sScl,
79 X86FoldableSchedWrite s128,
80 X86FoldableSchedWrite s256,
81 X86FoldableSchedWrite s512> {
82 X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.
83 X86FoldableSchedWrite MMX = sScl; // MMX operations.
84 X86FoldableSchedWrite XMM = s128; // XMM operations.
85 X86FoldableSchedWrite YMM = s256; // YMM operations.
86 X86FoldableSchedWrite ZMM = s512; // ZMM operations.
89 // Multiclass that wraps X86SchedWriteWidths for each fp vector type.
90 class X86SchedWriteSizes<X86SchedWriteWidths sPS,
91 X86SchedWriteWidths sPD> {
92 X86SchedWriteWidths PS = sPS;
93 X86SchedWriteWidths PD = sPD;
96 // Multiclass that wraps move/load/store triple for a vector width.
97 class X86SchedWriteMoveLS<SchedWrite MoveRR,
100 SchedWrite RR = MoveRR;
101 SchedWrite RM = LoadRM;
102 SchedWrite MR = StoreMR;
105 // Multiclass that wraps masked load/store writes for a vector width.
106 class X86SchedWriteMaskMove<SchedWrite LoadRM, SchedWrite StoreMR> {
107 SchedWrite RM = LoadRM;
108 SchedWrite MR = StoreMR;
111 // Multiclass that wraps X86SchedWriteMoveLS for each vector width.
112 class X86SchedWriteMoveLSWidths<X86SchedWriteMoveLS sScl,
113 X86SchedWriteMoveLS s128,
114 X86SchedWriteMoveLS s256,
115 X86SchedWriteMoveLS s512> {
116 X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.
117 X86SchedWriteMoveLS MMX = sScl; // MMX operations.
118 X86SchedWriteMoveLS XMM = s128; // XMM operations.
119 X86SchedWriteMoveLS YMM = s256; // YMM operations.
120 X86SchedWriteMoveLS ZMM = s512; // ZMM operations.
123 // Loads, stores, and moves, not folded with other operations.
124 def WriteLoad : SchedWrite;
125 def WriteStore : SchedWrite;
126 def WriteStoreNT : SchedWrite;
127 def WriteMove : SchedWrite;
128 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
131 defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
132 defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.
133 def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
134 def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>;
135 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
137 // Integer multiplication
138 defm WriteIMul8 : X86SchedWritePair; // Integer 8-bit multiplication.
139 defm WriteIMul16 : X86SchedWritePair; // Integer 16-bit multiplication.
140 defm WriteIMul16Imm : X86SchedWritePair; // Integer 16-bit multiplication by immediate.
141 defm WriteIMul16Reg : X86SchedWritePair; // Integer 16-bit multiplication by register.
142 defm WriteIMul32 : X86SchedWritePair; // Integer 32-bit multiplication.
143 defm WriteIMul32Imm : X86SchedWritePair; // Integer 32-bit multiplication by immediate.
144 defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by register.
145 defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.
146 defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.
147 defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.
148 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
150 def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
151 def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
152 defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.
153 def WriteCMPXCHGRMW : SchedWrite; // Compare and set, compare and swap.
154 def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
157 defm WriteDiv8 : X86SchedWritePair;
158 defm WriteDiv16 : X86SchedWritePair;
159 defm WriteDiv32 : X86SchedWritePair;
160 defm WriteDiv64 : X86SchedWritePair;
161 defm WriteIDiv8 : X86SchedWritePair;
162 defm WriteIDiv16 : X86SchedWritePair;
163 defm WriteIDiv32 : X86SchedWritePair;
164 defm WriteIDiv64 : X86SchedWritePair;
166 defm WriteBSF : X86SchedWritePair; // Bit scan forward.
167 defm WriteBSR : X86SchedWritePair; // Bit scan reverse.
168 defm WritePOPCNT : X86SchedWritePair; // Bit population count.
169 defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
170 defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
171 defm WriteCMOV : X86SchedWritePair; // Conditional move.
172 def WriteFCMOV : SchedWrite; // X87 conditional move.
173 def WriteSETCC : SchedWrite; // Set register based on condition code.
174 def WriteSETCCStore : SchedWrite;
175 def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.
177 def WriteBitTest : SchedWrite; // Bit Test
178 def WriteBitTestImmLd : SchedWrite;
179 def WriteBitTestRegLd : SchedWrite;
181 def WriteBitTestSet : SchedWrite; // Bit Test + Set
182 def WriteBitTestSetImmLd : SchedWrite;
183 def WriteBitTestSetRegLd : SchedWrite;
184 def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;
185 def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;
187 // Integer shifts and rotates.
188 defm WriteShift : X86SchedWritePair;
189 defm WriteShiftCL : X86SchedWritePair;
190 defm WriteRotate : X86SchedWritePair;
191 defm WriteRotateCL : X86SchedWritePair;
193 // Double shift instructions.
194 def WriteSHDrri : SchedWrite;
195 def WriteSHDrrcl : SchedWrite;
196 def WriteSHDmri : SchedWrite;
197 def WriteSHDmrcl : SchedWrite;
199 // BMI1 BEXTR/BLS, BMI2 BZHI
200 defm WriteBEXTR : X86SchedWritePair;
201 defm WriteBLS : X86SchedWritePair;
202 defm WriteBZHI : X86SchedWritePair;
204 // Idioms that clear a register, like xorps %xmm0, %xmm0.
205 // These can often bypass execution ports completely.
206 def WriteZero : SchedWrite;
208 // Branches don't produce values, so they have no latency, but they still
209 // consume resources. Indirect branches can fold loads.
210 defm WriteJump : X86SchedWritePair;
212 // Floating point. This covers both scalar and vector operations.
213 def WriteFLD0 : SchedWrite;
214 def WriteFLD1 : SchedWrite;
215 def WriteFLDC : SchedWrite;
216 def WriteFLoad : SchedWrite;
217 def WriteFLoadX : SchedWrite;
218 def WriteFLoadY : SchedWrite;
219 def WriteFMaskedLoad : SchedWrite;
220 def WriteFMaskedLoadY : SchedWrite;
221 def WriteFStore : SchedWrite;
222 def WriteFStoreX : SchedWrite;
223 def WriteFStoreY : SchedWrite;
224 def WriteFStoreNT : SchedWrite;
225 def WriteFStoreNTX : SchedWrite;
226 def WriteFStoreNTY : SchedWrite;
228 def WriteFMaskedStore32 : SchedWrite;
229 def WriteFMaskedStore64 : SchedWrite;
230 def WriteFMaskedStore32Y : SchedWrite;
231 def WriteFMaskedStore64Y : SchedWrite;
233 def WriteFMove : SchedWrite;
234 def WriteFMoveX : SchedWrite;
235 def WriteFMoveY : SchedWrite;
237 defm WriteFAdd : X86SchedWritePair<ReadAfterVecLd>; // Floating point add/sub.
238 defm WriteFAddX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point add/sub (XMM).
239 defm WriteFAddY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (YMM).
240 defm WriteFAddZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (ZMM).
241 defm WriteFAdd64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double add/sub.
242 defm WriteFAdd64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double add/sub (XMM).
243 defm WriteFAdd64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (YMM).
244 defm WriteFAdd64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (ZMM).
245 defm WriteFCmp : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare.
246 defm WriteFCmpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point compare (XMM).
247 defm WriteFCmpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (YMM).
248 defm WriteFCmpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (ZMM).
249 defm WriteFCmp64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double compare.
250 defm WriteFCmp64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double compare (XMM).
251 defm WriteFCmp64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (YMM).
252 defm WriteFCmp64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (ZMM).
253 defm WriteFCom : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare to flags (X87).
254 defm WriteFComX : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare to flags (SSE).
255 defm WriteFMul : X86SchedWritePair<ReadAfterVecLd>; // Floating point multiplication.
256 defm WriteFMulX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point multiplication (XMM).
257 defm WriteFMulY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
258 defm WriteFMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
259 defm WriteFMul64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double multiplication.
260 defm WriteFMul64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double multiplication (XMM).
261 defm WriteFMul64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (YMM).
262 defm WriteFMul64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (ZMM).
263 defm WriteFDiv : X86SchedWritePair<ReadAfterVecLd>; // Floating point division.
264 defm WriteFDivX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point division (XMM).
265 defm WriteFDivY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (YMM).
266 defm WriteFDivZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (ZMM).
267 defm WriteFDiv64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double division.
268 defm WriteFDiv64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double division (XMM).
269 defm WriteFDiv64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (YMM).
270 defm WriteFDiv64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (ZMM).
271 defm WriteFSqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point square root.
272 defm WriteFSqrtX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point square root (XMM).
273 defm WriteFSqrtY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (YMM).
274 defm WriteFSqrtZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (ZMM).
275 defm WriteFSqrt64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double square root.
276 defm WriteFSqrt64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double square root (XMM).
277 defm WriteFSqrt64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (YMM).
278 defm WriteFSqrt64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (ZMM).
279 defm WriteFSqrt80 : X86SchedWritePair<ReadAfterVecLd>; // Floating point long double square root.
280 defm WriteFRcp : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal estimate.
281 defm WriteFRcpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal estimate (XMM).
282 defm WriteFRcpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (YMM).
283 defm WriteFRcpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (ZMM).
284 defm WriteFRsqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal square root estimate.
285 defm WriteFRsqrtX: X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal square root estimate (XMM).
286 defm WriteFRsqrtY: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (YMM).
287 defm WriteFRsqrtZ: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (ZMM).
288 defm WriteFMA : X86SchedWritePair<ReadAfterVecLd>; // Fused Multiply Add.
289 defm WriteFMAX : X86SchedWritePair<ReadAfterVecXLd>; // Fused Multiply Add (XMM).
290 defm WriteFMAY : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (YMM).
291 defm WriteFMAZ : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (ZMM).
292 defm WriteDPPD : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double dot product.
293 defm WriteDPPS : X86SchedWritePair<ReadAfterVecXLd>; // Floating point single dot product.
294 defm WriteDPPSY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point single dot product (YMM).
295 defm WriteDPPSZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point single dot product (ZMM).
296 defm WriteFSign : X86SchedWritePair<ReadAfterVecLd>; // Floating point fabs/fchs.
297 defm WriteFRnd : X86SchedWritePair<ReadAfterVecXLd>; // Floating point rounding.
298 defm WriteFRndY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (YMM).
299 defm WriteFRndZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (ZMM).
300 defm WriteFLogic : X86SchedWritePair<ReadAfterVecXLd>; // Floating point and/or/xor logicals.
301 defm WriteFLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (YMM).
302 defm WriteFLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (ZMM).
303 defm WriteFTest : X86SchedWritePair<ReadAfterVecXLd>; // Floating point TEST instructions.
304 defm WriteFTestY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (YMM).
305 defm WriteFTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (ZMM).
306 defm WriteFShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector shuffles.
307 defm WriteFShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (YMM).
308 defm WriteFShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (ZMM).
309 defm WriteFVarShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector variable shuffles.
310 defm WriteFVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (YMM).
311 defm WriteFVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (ZMM).
312 defm WriteFBlend : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector blends.
313 defm WriteFBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (YMM).
314 defm WriteFBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (ZMM).
315 defm WriteFVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Fp vector variable blends.
316 defm WriteFVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMM).
317 defm WriteFVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMZMM).
319 // FMA Scheduling helper class.
320 class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
322 // Horizontal Add/Sub (float and integer)
323 defm WriteFHAdd : X86SchedWritePair<ReadAfterVecXLd>;
324 defm WriteFHAddY : X86SchedWritePair<ReadAfterVecYLd>;
325 defm WriteFHAddZ : X86SchedWritePair<ReadAfterVecYLd>;
326 defm WritePHAdd : X86SchedWritePair<ReadAfterVecLd>;
327 defm WritePHAddX : X86SchedWritePair<ReadAfterVecXLd>;
328 defm WritePHAddY : X86SchedWritePair<ReadAfterVecYLd>;
329 defm WritePHAddZ : X86SchedWritePair<ReadAfterVecYLd>;
331 // Vector integer operations.
332 def WriteVecLoad : SchedWrite;
333 def WriteVecLoadX : SchedWrite;
334 def WriteVecLoadY : SchedWrite;
335 def WriteVecLoadNT : SchedWrite;
336 def WriteVecLoadNTY : SchedWrite;
337 def WriteVecMaskedLoad : SchedWrite;
338 def WriteVecMaskedLoadY : SchedWrite;
339 def WriteVecStore : SchedWrite;
340 def WriteVecStoreX : SchedWrite;
341 def WriteVecStoreY : SchedWrite;
342 def WriteVecStoreNT : SchedWrite;
343 def WriteVecStoreNTY : SchedWrite;
344 def WriteVecMaskedStore32 : SchedWrite;
345 def WriteVecMaskedStore64 : SchedWrite;
346 def WriteVecMaskedStore32Y : SchedWrite;
347 def WriteVecMaskedStore64Y : SchedWrite;
348 def WriteVecMove : SchedWrite;
349 def WriteVecMoveX : SchedWrite;
350 def WriteVecMoveY : SchedWrite;
351 def WriteVecMoveToGpr : SchedWrite;
352 def WriteVecMoveFromGpr : SchedWrite;
354 defm WriteVecALU : X86SchedWritePair<ReadAfterVecLd>; // Vector integer ALU op, no logicals.
355 defm WriteVecALUX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer ALU op, no logicals (XMM).
356 defm WriteVecALUY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (YMM).
357 defm WriteVecALUZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (ZMM).
358 defm WriteVecLogic : X86SchedWritePair<ReadAfterVecLd>; // Vector integer and/or/xor logicals.
359 defm WriteVecLogicX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer and/or/xor logicals (XMM).
360 defm WriteVecLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (YMM).
361 defm WriteVecLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (ZMM).
362 defm WriteVecTest : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer TEST instructions.
363 defm WriteVecTestY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (YMM).
364 defm WriteVecTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (ZMM).
365 defm WriteVecShift : X86SchedWritePair<ReadAfterVecLd>; // Vector integer shifts (default).
366 defm WriteVecShiftX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer shifts (XMM).
367 defm WriteVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (YMM).
368 defm WriteVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (ZMM).
369 defm WriteVecShiftImm : X86SchedWritePair<ReadAfterVecLd>; // Vector integer immediate shifts (default).
370 defm WriteVecShiftImmX: X86SchedWritePair<ReadAfterVecXLd>; // Vector integer immediate shifts (XMM).
371 defm WriteVecShiftImmY: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (YMM).
372 defm WriteVecShiftImmZ: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (ZMM).
373 defm WriteVecIMul : X86SchedWritePair<ReadAfterVecLd>; // Vector integer multiply (default).
374 defm WriteVecIMulX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer multiply (XMM).
375 defm WriteVecIMulY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (YMM).
376 defm WriteVecIMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (ZMM).
377 defm WritePMULLD : X86SchedWritePair<ReadAfterVecXLd>; // Vector PMULLD.
378 defm WritePMULLDY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (YMM).
379 defm WritePMULLDZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (ZMM).
380 defm WriteShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector shuffles.
381 defm WriteShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector shuffles (XMM).
382 defm WriteShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (YMM).
383 defm WriteShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (ZMM).
384 defm WriteVarShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector variable shuffles.
385 defm WriteVarShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable shuffles (XMM).
386 defm WriteVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (YMM).
387 defm WriteVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (ZMM).
388 defm WriteBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector blends.
389 defm WriteBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (YMM).
390 defm WriteBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (ZMM).
391 defm WriteVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable blends.
392 defm WriteVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (YMM).
393 defm WriteVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (ZMM).
394 defm WritePSADBW : X86SchedWritePair<ReadAfterVecLd>; // Vector PSADBW.
395 defm WritePSADBWX : X86SchedWritePair<ReadAfterVecXLd>; // Vector PSADBW (XMM).
396 defm WritePSADBWY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (YMM).
397 defm WritePSADBWZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (ZMM).
398 defm WriteMPSAD : X86SchedWritePair<ReadAfterVecXLd>; // Vector MPSAD.
399 defm WriteMPSADY : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (YMM).
400 defm WriteMPSADZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (ZMM).
401 defm WritePHMINPOS : X86SchedWritePair<ReadAfterVecXLd>; // Vector PHMINPOS.
403 // Vector insert/extract operations.
404 defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element.
405 def WriteVecExtract : SchedWrite; // Extract vector element to gpr.
406 def WriteVecExtractSt : SchedWrite; // Extract vector element and store.
408 // MOVMSK operations.
409 def WriteFMOVMSK : SchedWrite;
410 def WriteVecMOVMSK : SchedWrite;
411 def WriteVecMOVMSKY : SchedWrite;
412 def WriteMMXMOVMSK : SchedWrite;
414 // Conversion between integer and float.
415 defm WriteCvtSD2I : X86SchedWritePair<ReadAfterVecLd>; // Double -> Integer.
416 defm WriteCvtPD2I : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Integer (XMM).
417 defm WriteCvtPD2IY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (YMM).
418 defm WriteCvtPD2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (ZMM).
420 defm WriteCvtSS2I : X86SchedWritePair<ReadAfterVecLd>; // Float -> Integer.
421 defm WriteCvtPS2I : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Integer (XMM).
422 defm WriteCvtPS2IY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (YMM).
423 defm WriteCvtPS2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (ZMM).
425 defm WriteCvtI2SD : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Double.
426 defm WriteCvtI2PD : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Double (XMM).
427 defm WriteCvtI2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (YMM).
428 defm WriteCvtI2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (ZMM).
430 defm WriteCvtI2SS : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Float.
431 defm WriteCvtI2PS : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Float (XMM).
432 defm WriteCvtI2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (YMM).
433 defm WriteCvtI2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (ZMM).
435 defm WriteCvtSS2SD : X86SchedWritePair<ReadAfterVecLd>; // Float -> Double size conversion.
436 defm WriteCvtPS2PD : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Double size conversion (XMM).
437 defm WriteCvtPS2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (YMM).
438 defm WriteCvtPS2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (ZMM).
440 defm WriteCvtSD2SS : X86SchedWritePair<ReadAfterVecLd>; // Double -> Float size conversion.
441 defm WriteCvtPD2PS : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Float size conversion (XMM).
442 defm WriteCvtPD2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (YMM).
443 defm WriteCvtPD2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (ZMM).
445 defm WriteCvtPH2PS : X86SchedWritePair<ReadAfterVecXLd>; // Half -> Float size conversion.
446 defm WriteCvtPH2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (YMM).
447 defm WriteCvtPH2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (ZMM).
449 def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion.
450 def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM).
451 def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM).
452 def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion.
453 def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM).
454 def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM).
456 // CRC32 instruction.
457 defm WriteCRC32 : X86SchedWritePair<ReadAfterLd>;
459 // Strings instructions.
460 // Packed Compare Implicit Length Strings, Return Mask
461 defm WritePCmpIStrM : X86SchedWritePair<ReadAfterVecXLd>;
462 // Packed Compare Explicit Length Strings, Return Mask
463 defm WritePCmpEStrM : X86SchedWritePair<ReadAfterVecXLd>;
464 // Packed Compare Implicit Length Strings, Return Index
465 defm WritePCmpIStrI : X86SchedWritePair<ReadAfterVecXLd>;
466 // Packed Compare Explicit Length Strings, Return Index
467 defm WritePCmpEStrI : X86SchedWritePair<ReadAfterVecXLd>;
470 defm WriteAESDecEnc : X86SchedWritePair<ReadAfterVecXLd>; // Decryption, encryption.
471 defm WriteAESIMC : X86SchedWritePair<ReadAfterVecXLd>; // InvMixColumn.
472 defm WriteAESKeyGen : X86SchedWritePair<ReadAfterVecXLd>; // Key Generation.
474 // Carry-less multiplication instructions.
475 defm WriteCLMul : X86SchedWritePair<ReadAfterVecXLd>;
478 def WriteEMMS : SchedWrite;
481 def WriteLDMXCSR : SchedWrite;
482 def WriteSTMXCSR : SchedWrite;
484 // Catch-all for expensive system instructions.
485 def WriteSystem : SchedWrite;
488 defm WriteFShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width vector shuffles.
489 defm WriteFVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width variable shuffles.
490 defm WriteShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector shuffles.
491 defm WriteVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector variable shuffles.
492 defm WriteVarVecShift : X86SchedWritePair<ReadAfterVecXLd>; // Variable vector shifts.
493 defm WriteVarVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (YMM).
494 defm WriteVarVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (ZMM).
496 // Old microcoded instructions that nobody use.
497 def WriteMicrocoded : SchedWrite;
499 // Fence instructions.
500 def WriteFence : SchedWrite;
502 // Nop, not very useful expect it provides a model for nops!
503 def WriteNop : SchedWrite;
505 // Move/Load/Store wrappers.
507 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStore>;
509 : X86SchedWriteMoveLS<WriteFMoveX, WriteFLoadX, WriteFStoreX>;
511 : X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreY>;
512 def SchedWriteFMoveLS
513 : X86SchedWriteMoveLSWidths<WriteFMoveLS, WriteFMoveLSX,
514 WriteFMoveLSY, WriteFMoveLSY>;
517 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNT>;
519 : X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNTX>;
521 : X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreNTY>;
522 def SchedWriteFMoveLSNT
523 : X86SchedWriteMoveLSWidths<WriteFMoveLSNT, WriteFMoveLSNTX,
524 WriteFMoveLSNTY, WriteFMoveLSNTY>;
527 : X86SchedWriteMoveLS<WriteVecMove, WriteVecLoad, WriteVecStore>;
529 : X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadX, WriteVecStoreX>;
531 : X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadY, WriteVecStoreY>;
532 def SchedWriteVecMoveLS
533 : X86SchedWriteMoveLSWidths<WriteVecMoveLS, WriteVecMoveLSX,
534 WriteVecMoveLSY, WriteVecMoveLSY>;
537 : X86SchedWriteMoveLS<WriteVecMove, WriteVecLoadNT, WriteVecStoreNT>;
538 def WriteVecMoveLSNTX
539 : X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadNT, WriteVecStoreNT>;
540 def WriteVecMoveLSNTY
541 : X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadNTY, WriteVecStoreNTY>;
542 def SchedWriteVecMoveLSNT
543 : X86SchedWriteMoveLSWidths<WriteVecMoveLSNT, WriteVecMoveLSNTX,
544 WriteVecMoveLSNTY, WriteVecMoveLSNTY>;
546 // Conditional SIMD Packed Loads and Stores wrappers.
548 : X86SchedWriteMaskMove<WriteFMaskedLoad, WriteFMaskedStore32>;
550 : X86SchedWriteMaskMove<WriteFMaskedLoad, WriteFMaskedStore64>;
551 def WriteFMaskMove32Y
552 : X86SchedWriteMaskMove<WriteFMaskedLoadY, WriteFMaskedStore32Y>;
553 def WriteFMaskMove64Y
554 : X86SchedWriteMaskMove<WriteFMaskedLoadY, WriteFMaskedStore64Y>;
555 def WriteVecMaskMove32
556 : X86SchedWriteMaskMove<WriteVecMaskedLoad, WriteVecMaskedStore32>;
557 def WriteVecMaskMove64
558 : X86SchedWriteMaskMove<WriteVecMaskedLoad, WriteVecMaskedStore64>;
559 def WriteVecMaskMove32Y
560 : X86SchedWriteMaskMove<WriteVecMaskedLoadY, WriteVecMaskedStore32Y>;
561 def WriteVecMaskMove64Y
562 : X86SchedWriteMaskMove<WriteVecMaskedLoadY, WriteVecMaskedStore64Y>;
564 // Vector width wrappers.
566 : X86SchedWriteWidths<WriteFAdd, WriteFAddX, WriteFAddY, WriteFAddZ>;
568 : X86SchedWriteWidths<WriteFAdd64, WriteFAdd64X, WriteFAdd64Y, WriteFAdd64Z>;
570 : X86SchedWriteWidths<WriteFHAdd, WriteFHAdd, WriteFHAddY, WriteFHAddZ>;
572 : X86SchedWriteWidths<WriteFCmp, WriteFCmpX, WriteFCmpY, WriteFCmpZ>;
574 : X86SchedWriteWidths<WriteFCmp64, WriteFCmp64X, WriteFCmp64Y, WriteFCmp64Z>;
576 : X86SchedWriteWidths<WriteFMul, WriteFMulX, WriteFMulY, WriteFMulZ>;
578 : X86SchedWriteWidths<WriteFMul64, WriteFMul64X, WriteFMul64Y, WriteFMul64Z>;
580 : X86SchedWriteWidths<WriteFMA, WriteFMAX, WriteFMAY, WriteFMAZ>;
582 : X86SchedWriteWidths<WriteDPPD, WriteDPPD, WriteDPPD, WriteDPPD>;
584 : X86SchedWriteWidths<WriteDPPS, WriteDPPS, WriteDPPSY, WriteDPPSZ>;
586 : X86SchedWriteWidths<WriteFDiv, WriteFDivX, WriteFDivY, WriteFDivZ>;
588 : X86SchedWriteWidths<WriteFDiv64, WriteFDiv64X, WriteFDiv64Y, WriteFDiv64Z>;
590 : X86SchedWriteWidths<WriteFSqrt, WriteFSqrtX,
591 WriteFSqrtY, WriteFSqrtZ>;
592 def SchedWriteFSqrt64
593 : X86SchedWriteWidths<WriteFSqrt64, WriteFSqrt64X,
594 WriteFSqrt64Y, WriteFSqrt64Z>;
596 : X86SchedWriteWidths<WriteFRcp, WriteFRcpX, WriteFRcpY, WriteFRcpZ>;
598 : X86SchedWriteWidths<WriteFRsqrt, WriteFRsqrtX, WriteFRsqrtY, WriteFRsqrtZ>;
600 : X86SchedWriteWidths<WriteFRnd, WriteFRnd, WriteFRndY, WriteFRndZ>;
602 : X86SchedWriteWidths<WriteFLogic, WriteFLogic, WriteFLogicY, WriteFLogicZ>;
604 : X86SchedWriteWidths<WriteFTest, WriteFTest, WriteFTestY, WriteFTestZ>;
606 def SchedWriteFShuffle
607 : X86SchedWriteWidths<WriteFShuffle, WriteFShuffle,
608 WriteFShuffleY, WriteFShuffleZ>;
609 def SchedWriteFVarShuffle
610 : X86SchedWriteWidths<WriteFVarShuffle, WriteFVarShuffle,
611 WriteFVarShuffleY, WriteFVarShuffleZ>;
613 : X86SchedWriteWidths<WriteFBlend, WriteFBlend, WriteFBlendY, WriteFBlendZ>;
614 def SchedWriteFVarBlend
615 : X86SchedWriteWidths<WriteFVarBlend, WriteFVarBlend,
616 WriteFVarBlendY, WriteFVarBlendZ>;
618 def SchedWriteCvtDQ2PD
619 : X86SchedWriteWidths<WriteCvtI2SD, WriteCvtI2PD,
620 WriteCvtI2PDY, WriteCvtI2PDZ>;
621 def SchedWriteCvtDQ2PS
622 : X86SchedWriteWidths<WriteCvtI2SS, WriteCvtI2PS,
623 WriteCvtI2PSY, WriteCvtI2PSZ>;
624 def SchedWriteCvtPD2DQ
625 : X86SchedWriteWidths<WriteCvtSD2I, WriteCvtPD2I,
626 WriteCvtPD2IY, WriteCvtPD2IZ>;
627 def SchedWriteCvtPS2DQ
628 : X86SchedWriteWidths<WriteCvtSS2I, WriteCvtPS2I,
629 WriteCvtPS2IY, WriteCvtPS2IZ>;
630 def SchedWriteCvtPS2PD
631 : X86SchedWriteWidths<WriteCvtSS2SD, WriteCvtPS2PD,
632 WriteCvtPS2PDY, WriteCvtPS2PDZ>;
633 def SchedWriteCvtPD2PS
634 : X86SchedWriteWidths<WriteCvtSD2SS, WriteCvtPD2PS,
635 WriteCvtPD2PSY, WriteCvtPD2PSZ>;
638 : X86SchedWriteWidths<WriteVecALU, WriteVecALUX, WriteVecALUY, WriteVecALUZ>;
640 : X86SchedWriteWidths<WritePHAdd, WritePHAddX, WritePHAddY, WritePHAddZ>;
641 def SchedWriteVecLogic
642 : X86SchedWriteWidths<WriteVecLogic, WriteVecLogicX,
643 WriteVecLogicY, WriteVecLogicZ>;
644 def SchedWriteVecTest
645 : X86SchedWriteWidths<WriteVecTest, WriteVecTest,
646 WriteVecTestY, WriteVecTestZ>;
647 def SchedWriteVecShift
648 : X86SchedWriteWidths<WriteVecShift, WriteVecShiftX,
649 WriteVecShiftY, WriteVecShiftZ>;
650 def SchedWriteVecShiftImm
651 : X86SchedWriteWidths<WriteVecShiftImm, WriteVecShiftImmX,
652 WriteVecShiftImmY, WriteVecShiftImmZ>;
653 def SchedWriteVarVecShift
654 : X86SchedWriteWidths<WriteVarVecShift, WriteVarVecShift,
655 WriteVarVecShiftY, WriteVarVecShiftZ>;
656 def SchedWriteVecIMul
657 : X86SchedWriteWidths<WriteVecIMul, WriteVecIMulX,
658 WriteVecIMulY, WriteVecIMulZ>;
660 : X86SchedWriteWidths<WritePMULLD, WritePMULLD,
661 WritePMULLDY, WritePMULLDZ>;
663 : X86SchedWriteWidths<WriteMPSAD, WriteMPSAD,
664 WriteMPSADY, WriteMPSADZ>;
666 : X86SchedWriteWidths<WritePSADBW, WritePSADBWX,
667 WritePSADBWY, WritePSADBWZ>;
669 def SchedWriteShuffle
670 : X86SchedWriteWidths<WriteShuffle, WriteShuffleX,
671 WriteShuffleY, WriteShuffleZ>;
672 def SchedWriteVarShuffle
673 : X86SchedWriteWidths<WriteVarShuffle, WriteVarShuffleX,
674 WriteVarShuffleY, WriteVarShuffleZ>;
676 : X86SchedWriteWidths<WriteBlend, WriteBlend, WriteBlendY, WriteBlendZ>;
677 def SchedWriteVarBlend
678 : X86SchedWriteWidths<WriteVarBlend, WriteVarBlend,
679 WriteVarBlendY, WriteVarBlendZ>;
681 // Vector size wrappers.
682 def SchedWriteFAddSizes
683 : X86SchedWriteSizes<SchedWriteFAdd, SchedWriteFAdd64>;
684 def SchedWriteFCmpSizes
685 : X86SchedWriteSizes<SchedWriteFCmp, SchedWriteFCmp64>;
686 def SchedWriteFMulSizes
687 : X86SchedWriteSizes<SchedWriteFMul, SchedWriteFMul64>;
688 def SchedWriteFDivSizes
689 : X86SchedWriteSizes<SchedWriteFDiv, SchedWriteFDiv64>;
690 def SchedWriteFSqrtSizes
691 : X86SchedWriteSizes<SchedWriteFSqrt, SchedWriteFSqrt64>;
692 def SchedWriteFLogicSizes
693 : X86SchedWriteSizes<SchedWriteFLogic, SchedWriteFLogic>;
694 def SchedWriteFShuffleSizes
695 : X86SchedWriteSizes<SchedWriteFShuffle, SchedWriteFShuffle>;
697 //===----------------------------------------------------------------------===//
698 // Generic Processor Scheduler Models.
700 // IssueWidth is analogous to the number of decode units. Core and its
701 // descendents, including Nehalem and SandyBridge have 4 decoders.
702 // Resources beyond the decoder operate on micro-ops and are bufferred
703 // so adjacent micro-ops don't directly compete.
705 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
706 // decoded in the same cycle. The value 32 is a reasonably arbitrary
707 // number of in-flight instructions.
709 // HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
710 // indicates high latency opcodes. Alternatively, InstrItinData
711 // entries may be included here to define specific operand
712 // latencies. Since these latencies are not used for pipeline hazards,
713 // they do not need to be exact.
715 // The GenericX86Model contains no instruction schedules
716 // and disables PostRAScheduler.
717 class GenericX86Model : SchedMachineModel {
719 let MicroOpBufferSize = 32;
721 let HighLatency = 10;
722 let PostRAScheduler = 0;
723 let CompleteModel = 0;
726 def GenericModel : GenericX86Model;
728 // Define a model with the PostRAScheduler enabled.
729 def GenericPostRAModel : GenericX86Model {
730 let PostRAScheduler = 1;