1 //=- X86ScheduleZnver2.td - X86 Znver2 Scheduling -------------*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for Znver2 to support instruction
10 // scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 def Znver2Model : SchedMachineModel {
15 // Zen can decode 4 instructions per cycle.
17 // Based on the reorder buffer we define MicroOpBufferSize
18 let MicroOpBufferSize = 224;
20 let MispredictPenalty = 17;
22 let PostRAScheduler = 1;
24 // FIXME: This variable is required for incomplete model.
25 // We haven't catered all instructions.
26 // So, we reset the value of this variable so as to
27 // say that the model is incomplete.
28 let CompleteModel = 0;
31 let SchedModel = Znver2Model in {
33 // Zen can issue micro-ops to 10 different units in one cycle.
35 // * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3)
36 // * Three AGU units (ZAGU0, ZAGU1, ZAGU2)
37 // * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3)
38 // AGUs feed load store queues @two loads and 1 store per cycle.
40 // Four ALU units are defined below
41 def Zn2ALU0 : ProcResource<1>;
42 def Zn2ALU1 : ProcResource<1>;
43 def Zn2ALU2 : ProcResource<1>;
44 def Zn2ALU3 : ProcResource<1>;
46 // Three AGU units are defined below
47 def Zn2AGU0 : ProcResource<1>;
48 def Zn2AGU1 : ProcResource<1>;
49 def Zn2AGU2 : ProcResource<1>;
51 // Four FPU units are defined below
52 def Zn2FPU0 : ProcResource<1>;
53 def Zn2FPU1 : ProcResource<1>;
54 def Zn2FPU2 : ProcResource<1>;
55 def Zn2FPU3 : ProcResource<1>;
58 def Zn2FPU013 : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU3]>;
59 def Zn2FPU01 : ProcResGroup<[Zn2FPU0, Zn2FPU1]>;
60 def Zn2FPU12 : ProcResGroup<[Zn2FPU1, Zn2FPU2]>;
61 def Zn2FPU13 : ProcResGroup<[Zn2FPU1, Zn2FPU3]>;
62 def Zn2FPU23 : ProcResGroup<[Zn2FPU2, Zn2FPU3]>;
63 def Zn2FPU02 : ProcResGroup<[Zn2FPU0, Zn2FPU2]>;
64 def Zn2FPU03 : ProcResGroup<[Zn2FPU0, Zn2FPU3]>;
66 // Below are the grouping of the units.
67 // Micro-ops to be issued to multiple units are tackled this way.
70 // Zn2ALU03 - 0,3 grouping
71 def Zn2ALU03: ProcResGroup<[Zn2ALU0, Zn2ALU3]>;
73 // 64 Entry (16x4 entries) Int Scheduler
74 def Zn2ALU : ProcResGroup<[Zn2ALU0, Zn2ALU1, Zn2ALU2, Zn2ALU3]> {
78 // 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations
79 // but are relevant for some instructions
80 def Zn2AGU : ProcResGroup<[Zn2AGU0, Zn2AGU1, Zn2AGU2]> {
84 // Integer Multiplication issued on ALU1.
85 def Zn2Multiplier : ProcResource<1>;
87 // Integer division issued on ALU2.
88 def Zn2Divider : ProcResource<1>;
90 // 4 Cycles load-to use Latency is captured
91 def : ReadAdvance<ReadAfterLd, 4>;
93 // 7 Cycles vector load-to use Latency is captured
94 def : ReadAdvance<ReadAfterVecLd, 7>;
95 def : ReadAdvance<ReadAfterVecXLd, 7>;
96 def : ReadAdvance<ReadAfterVecYLd, 7>;
98 def : ReadAdvance<ReadInt2Fpu, 0>;
100 // The Integer PRF for Zen is 168 entries, and it holds the architectural and
101 // speculative version of the 64-bit integer registers.
102 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
103 def Zn2IntegerPRF : RegisterFile<168, [GR64, CCR]>;
105 // 36 Entry (9x4 entries) floating-point Scheduler
106 def Zn2FPU : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU2, Zn2FPU3]> {
110 // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
111 // registers. Operations on 256-bit data types are cracked into two COPs.
112 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
115 // The unit can track up to 192 macro ops in-flight.
116 // The retire unit handles in-order commit of up to 8 macro ops per cycle.
117 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
118 // To be noted, the retire unit is shared between integer and FP ops.
119 // In SMT mode it is 96 entry per thread. But, we do not use the conservative
120 // value here because there is currently no way to fully mode the SMT mode,
121 // so there is no point in trying.
122 def Zn2RCU : RetireControlUnit<192, 8>;
124 // (a folded load is an instruction that loads and does some operation)
125 // Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops
126 // Instructions with folded loads are usually micro-fused, so they only appear
130 // This multiclass is for folded loads for integer units.
131 multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
132 list<ProcResourceKind> ExePorts,
133 int Lat, list<int> Res = [], int UOps = 1,
134 int LoadLat = 4, int LoadUOps = 1> {
135 // Register variant takes 1-cycle on Execution Port.
136 def : WriteRes<SchedRW, ExePorts> {
138 let ResourceCycles = Res;
139 let NumMicroOps = UOps;
142 // Memory variant also uses a cycle on Zn2AGU
143 // adds LoadLat cycles to the latency (default = 4).
144 def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
145 let Latency = !add(Lat, LoadLat);
146 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
147 let NumMicroOps = !add(UOps, LoadUOps);
151 // This multiclass is for folded loads for floating point units.
152 multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
153 list<ProcResourceKind> ExePorts,
154 int Lat, list<int> Res = [], int UOps = 1,
155 int LoadLat = 7, int LoadUOps = 0> {
156 // Register variant takes 1-cycle on Execution Port.
157 def : WriteRes<SchedRW, ExePorts> {
159 let ResourceCycles = Res;
160 let NumMicroOps = UOps;
163 // Memory variant also uses a cycle on Zn2AGU
164 // adds LoadLat cycles to the latency (default = 7).
165 def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
166 let Latency = !add(Lat, LoadLat);
167 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
168 let NumMicroOps = !add(UOps, LoadUOps);
172 // WriteRMW is set for instructions with Memory write
173 // operation in codegen
174 def : WriteRes<WriteRMW, [Zn2AGU]>;
176 def : WriteRes<WriteStore, [Zn2AGU]>;
177 def : WriteRes<WriteStoreNT, [Zn2AGU]>;
178 def : WriteRes<WriteMove, [Zn2ALU]>;
179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 8; }
181 def : WriteRes<WriteZero, []>;
182 def : WriteRes<WriteLEA, [Zn2ALU]>;
183 defm : Zn2WriteResPair<WriteALU, [Zn2ALU], 1>;
184 defm : Zn2WriteResPair<WriteADC, [Zn2ALU], 1>;
186 defm : Zn2WriteResPair<WriteIMul8, [Zn2ALU1, Zn2Multiplier], 4>;
188 defm : X86WriteRes<WriteBSWAP32, [Zn2ALU], 1, [4], 1>;
189 defm : X86WriteRes<WriteBSWAP64, [Zn2ALU], 1, [4], 1>;
190 defm : X86WriteRes<WriteCMPXCHG, [Zn2ALU], 3, [1], 1>;
191 defm : X86WriteRes<WriteCMPXCHGRMW,[Zn2ALU,Zn2AGU], 8, [1,1], 5>;
192 defm : X86WriteRes<WriteXCHG, [Zn2ALU], 1, [2], 2>;
194 defm : Zn2WriteResPair<WriteShift, [Zn2ALU], 1>;
195 defm : Zn2WriteResPair<WriteShiftCL, [Zn2ALU], 1>;
196 defm : Zn2WriteResPair<WriteRotate, [Zn2ALU], 1>;
197 defm : Zn2WriteResPair<WriteRotateCL, [Zn2ALU], 1>;
199 defm : X86WriteRes<WriteSHDrri, [Zn2ALU], 1, [1], 1>;
200 defm : X86WriteResUnsupported<WriteSHDrrcl>;
201 defm : X86WriteResUnsupported<WriteSHDmri>;
202 defm : X86WriteResUnsupported<WriteSHDmrcl>;
204 defm : Zn2WriteResPair<WriteJump, [Zn2ALU], 1>;
205 defm : Zn2WriteResFpuPair<WriteCRC32, [Zn2FPU0], 3>;
207 defm : Zn2WriteResPair<WriteCMOV, [Zn2ALU], 1>;
208 def : WriteRes<WriteSETCC, [Zn2ALU]>;
209 def : WriteRes<WriteSETCCStore, [Zn2ALU, Zn2AGU]>;
210 defm : X86WriteRes<WriteLAHFSAHF, [Zn2ALU], 2, [1], 2>;
212 defm : X86WriteRes<WriteBitTest, [Zn2ALU], 1, [1], 1>;
213 defm : X86WriteRes<WriteBitTestImmLd, [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
214 defm : X86WriteRes<WriteBitTestRegLd, [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
215 defm : X86WriteRes<WriteBitTestSet, [Zn2ALU], 2, [1], 2>;
218 defm : Zn2WriteResPair<WriteBSF, [Zn2ALU], 3>;
219 defm : Zn2WriteResPair<WriteBSR, [Zn2ALU], 4>;
220 defm : Zn2WriteResPair<WriteLZCNT, [Zn2ALU], 1>;
221 defm : Zn2WriteResPair<WriteTZCNT, [Zn2ALU], 2>;
222 defm : Zn2WriteResPair<WritePOPCNT, [Zn2ALU], 1>;
224 // Treat misc copies as a move.
225 def : InstRW<[WriteMove], (instrs COPY)>;
227 // BMI1 BEXTR, BMI2 BZHI
228 defm : Zn2WriteResPair<WriteBEXTR, [Zn2ALU], 1>;
229 defm : Zn2WriteResPair<WriteBZHI, [Zn2ALU], 1>;
232 defm : Zn2WriteResPair<WriteDiv8, [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
233 defm : Zn2WriteResPair<WriteDiv16, [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
234 defm : Zn2WriteResPair<WriteDiv32, [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
235 defm : Zn2WriteResPair<WriteDiv64, [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
236 defm : Zn2WriteResPair<WriteIDiv8, [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
237 defm : Zn2WriteResPair<WriteIDiv16, [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
238 defm : Zn2WriteResPair<WriteIDiv32, [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
239 defm : Zn2WriteResPair<WriteIDiv64, [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
242 def : WriteRes<WriteIMulH, [Zn2ALU1, Zn2Multiplier]>{
246 // Floating point operations
247 defm : X86WriteRes<WriteFLoad, [Zn2AGU], 8, [1], 1>;
248 defm : X86WriteRes<WriteFLoadX, [Zn2AGU], 8, [1], 1>;
249 defm : X86WriteRes<WriteFLoadY, [Zn2AGU], 8, [1], 1>;
250 defm : X86WriteRes<WriteFMaskedLoad, [Zn2AGU,Zn2FPU01], 8, [1,1], 1>;
251 defm : X86WriteRes<WriteFMaskedLoadY, [Zn2AGU,Zn2FPU01], 8, [1,1], 2>;
252 defm : X86WriteRes<WriteFMaskedStore32, [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
253 defm : X86WriteRes<WriteFMaskedStore32Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
254 defm : X86WriteRes<WriteFMaskedStore64, [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
255 defm : X86WriteRes<WriteFMaskedStore64Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
257 defm : X86WriteRes<WriteFStore, [Zn2AGU], 1, [1], 1>;
258 defm : X86WriteRes<WriteFStoreX, [Zn2AGU], 1, [1], 1>;
259 defm : X86WriteRes<WriteFStoreY, [Zn2AGU], 1, [1], 1>;
260 defm : X86WriteRes<WriteFStoreNT, [Zn2AGU,Zn2FPU2], 8, [1,1], 1>;
261 defm : X86WriteRes<WriteFStoreNTX, [Zn2AGU], 1, [1], 1>;
262 defm : X86WriteRes<WriteFStoreNTY, [Zn2AGU], 1, [1], 1>;
263 defm : X86WriteRes<WriteFMove, [Zn2FPU], 1, [1], 1>;
264 defm : X86WriteRes<WriteFMoveX, [Zn2FPU], 1, [1], 1>;
265 defm : X86WriteRes<WriteFMoveY, [Zn2FPU], 1, [1], 1>;
267 defm : Zn2WriteResFpuPair<WriteFAdd, [Zn2FPU0], 3>;
268 defm : Zn2WriteResFpuPair<WriteFAddX, [Zn2FPU0], 3>;
269 defm : Zn2WriteResFpuPair<WriteFAddY, [Zn2FPU0], 3>;
270 defm : X86WriteResPairUnsupported<WriteFAddZ>;
271 defm : Zn2WriteResFpuPair<WriteFAdd64, [Zn2FPU0], 3>;
272 defm : Zn2WriteResFpuPair<WriteFAdd64X, [Zn2FPU0], 3>;
273 defm : Zn2WriteResFpuPair<WriteFAdd64Y, [Zn2FPU0], 3>;
274 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
275 defm : Zn2WriteResFpuPair<WriteFCmp, [Zn2FPU0], 1>;
276 defm : Zn2WriteResFpuPair<WriteFCmpX, [Zn2FPU0], 1>;
277 defm : Zn2WriteResFpuPair<WriteFCmpY, [Zn2FPU0], 1>;
278 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
279 defm : Zn2WriteResFpuPair<WriteFCmp64, [Zn2FPU0], 1>;
280 defm : Zn2WriteResFpuPair<WriteFCmp64X, [Zn2FPU0], 1>;
281 defm : Zn2WriteResFpuPair<WriteFCmp64Y, [Zn2FPU0], 1>;
282 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
283 defm : Zn2WriteResFpuPair<WriteFCom, [Zn2FPU0], 3>;
284 defm : Zn2WriteResFpuPair<WriteFComX, [Zn2FPU0], 3>;
285 defm : Zn2WriteResFpuPair<WriteFBlend, [Zn2FPU01], 1>;
286 defm : Zn2WriteResFpuPair<WriteFBlendY, [Zn2FPU01], 1>;
287 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
288 defm : Zn2WriteResFpuPair<WriteFVarBlend, [Zn2FPU01], 1>;
289 defm : Zn2WriteResFpuPair<WriteFVarBlendY,[Zn2FPU01], 1>;
290 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
291 defm : Zn2WriteResFpuPair<WriteVarBlend, [Zn2FPU0], 1>;
292 defm : Zn2WriteResFpuPair<WriteVarBlendY, [Zn2FPU0], 1>;
293 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
294 defm : Zn2WriteResFpuPair<WriteCvtSS2I, [Zn2FPU3], 5>;
295 defm : Zn2WriteResFpuPair<WriteCvtPS2I, [Zn2FPU3], 5>;
296 defm : Zn2WriteResFpuPair<WriteCvtPS2IY, [Zn2FPU3], 5>;
297 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
298 defm : Zn2WriteResFpuPair<WriteCvtSD2I, [Zn2FPU3], 5>;
299 defm : Zn2WriteResFpuPair<WriteCvtPD2I, [Zn2FPU3], 5>;
300 defm : Zn2WriteResFpuPair<WriteCvtPD2IY, [Zn2FPU3], 5>;
301 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
302 defm : Zn2WriteResFpuPair<WriteCvtI2SS, [Zn2FPU3], 5>;
303 defm : Zn2WriteResFpuPair<WriteCvtI2PS, [Zn2FPU3], 5>;
304 defm : Zn2WriteResFpuPair<WriteCvtI2PSY, [Zn2FPU3], 5>;
305 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
306 defm : Zn2WriteResFpuPair<WriteCvtI2SD, [Zn2FPU3], 5>;
307 defm : Zn2WriteResFpuPair<WriteCvtI2PD, [Zn2FPU3], 5>;
308 defm : Zn2WriteResFpuPair<WriteCvtI2PDY, [Zn2FPU3], 5>;
309 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
310 defm : Zn2WriteResFpuPair<WriteFDiv, [Zn2FPU3], 15>;
311 defm : Zn2WriteResFpuPair<WriteFDivX, [Zn2FPU3], 15>;
312 defm : X86WriteResPairUnsupported<WriteFDivZ>;
313 defm : Zn2WriteResFpuPair<WriteFDiv64, [Zn2FPU3], 15>;
314 defm : Zn2WriteResFpuPair<WriteFDiv64X, [Zn2FPU3], 15>;
315 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
316 defm : Zn2WriteResFpuPair<WriteFSign, [Zn2FPU3], 2>;
317 defm : Zn2WriteResFpuPair<WriteFRnd, [Zn2FPU3], 3, [1], 1, 7, 0>;
318 defm : Zn2WriteResFpuPair<WriteFRndY, [Zn2FPU3], 3, [1], 1, 7, 0>;
319 defm : X86WriteResPairUnsupported<WriteFRndZ>;
320 defm : Zn2WriteResFpuPair<WriteFLogic, [Zn2FPU], 1>;
321 defm : Zn2WriteResFpuPair<WriteFLogicY, [Zn2FPU], 1>;
322 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
323 defm : Zn2WriteResFpuPair<WriteFTest, [Zn2FPU], 1>;
324 defm : Zn2WriteResFpuPair<WriteFTestY, [Zn2FPU], 1>;
325 defm : X86WriteResPairUnsupported<WriteFTestZ>;
326 defm : Zn2WriteResFpuPair<WriteFShuffle, [Zn2FPU12], 1>;
327 defm : Zn2WriteResFpuPair<WriteFShuffleY, [Zn2FPU12], 1>;
328 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
329 defm : Zn2WriteResFpuPair<WriteFVarShuffle, [Zn2FPU12], 3>;
330 defm : Zn2WriteResFpuPair<WriteFVarShuffleY,[Zn2FPU12], 3>;
331 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
332 defm : Zn2WriteResFpuPair<WriteFMul, [Zn2FPU01], 3, [1], 1, 7, 1>;
333 defm : Zn2WriteResFpuPair<WriteFMulX, [Zn2FPU01], 3, [1], 1, 7, 1>;
334 defm : Zn2WriteResFpuPair<WriteFMulY, [Zn2FPU01], 3, [1], 1, 7, 1>;
335 defm : X86WriteResPairUnsupported<WriteFMulZ>;
336 defm : Zn2WriteResFpuPair<WriteFMul64, [Zn2FPU01], 3, [1], 1, 7, 1>;
337 defm : Zn2WriteResFpuPair<WriteFMul64X, [Zn2FPU01], 3, [1], 1, 7, 1>;
338 defm : Zn2WriteResFpuPair<WriteFMul64Y, [Zn2FPU01], 3, [1], 1, 7, 1>;
339 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
340 defm : Zn2WriteResFpuPair<WriteFMA, [Zn2FPU03], 5>;
341 defm : Zn2WriteResFpuPair<WriteFMAX, [Zn2FPU03], 5>;
342 defm : Zn2WriteResFpuPair<WriteFMAY, [Zn2FPU03], 5>;
343 defm : X86WriteResPairUnsupported<WriteFMAZ>;
344 defm : Zn2WriteResFpuPair<WriteFRcp, [Zn2FPU01], 5>;
345 defm : Zn2WriteResFpuPair<WriteFRcpX, [Zn2FPU01], 5>;
346 defm : Zn2WriteResFpuPair<WriteFRcpY, [Zn2FPU01], 5, [1], 1, 7, 2>;
347 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
348 defm : Zn2WriteResFpuPair<WriteFRsqrtX, [Zn2FPU01], 5, [1], 1, 7, 1>;
349 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
350 defm : Zn2WriteResFpuPair<WriteFSqrt, [Zn2FPU3], 20, [20]>;
351 defm : Zn2WriteResFpuPair<WriteFSqrtX, [Zn2FPU3], 20, [20]>;
352 defm : Zn2WriteResFpuPair<WriteFSqrtY, [Zn2FPU3], 28, [28], 1, 7, 1>;
353 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
354 defm : Zn2WriteResFpuPair<WriteFSqrt64, [Zn2FPU3], 20, [20]>;
355 defm : Zn2WriteResFpuPair<WriteFSqrt64X, [Zn2FPU3], 20, [20]>;
356 defm : Zn2WriteResFpuPair<WriteFSqrt64Y, [Zn2FPU3], 20, [20], 1, 7, 1>;
357 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
358 defm : Zn2WriteResFpuPair<WriteFSqrt80, [Zn2FPU3], 20, [20]>;
360 // Vector integer operations which uses FPU units
361 defm : X86WriteRes<WriteVecLoad, [Zn2AGU], 8, [1], 1>;
362 defm : X86WriteRes<WriteVecLoadX, [Zn2AGU], 8, [1], 1>;
363 defm : X86WriteRes<WriteVecLoadY, [Zn2AGU], 8, [1], 1>;
364 defm : X86WriteRes<WriteVecLoadNT, [Zn2AGU], 8, [1], 1>;
365 defm : X86WriteRes<WriteVecLoadNTY, [Zn2AGU], 8, [1], 1>;
366 defm : X86WriteRes<WriteVecMaskedLoad, [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
367 defm : X86WriteRes<WriteVecMaskedLoadY, [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
368 defm : X86WriteRes<WriteVecStore, [Zn2AGU], 1, [1], 1>;
369 defm : X86WriteRes<WriteVecStoreX, [Zn2AGU], 1, [1], 1>;
370 defm : X86WriteRes<WriteVecStoreY, [Zn2AGU], 1, [1], 1>;
371 defm : X86WriteRes<WriteVecStoreNT, [Zn2AGU], 1, [1], 1>;
372 defm : X86WriteRes<WriteVecStoreNTY, [Zn2AGU], 1, [1], 1>;
373 defm : X86WriteRes<WriteVecMaskedStore32, [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
374 defm : X86WriteRes<WriteVecMaskedStore32Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
375 defm : X86WriteRes<WriteVecMaskedStore64, [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
376 defm : X86WriteRes<WriteVecMaskedStore64Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
377 defm : X86WriteRes<WriteVecMove, [Zn2FPU], 1, [1], 1>;
378 defm : X86WriteRes<WriteVecMoveX, [Zn2FPU], 1, [1], 1>;
379 defm : X86WriteRes<WriteVecMoveY, [Zn2FPU], 2, [1], 2>;
380 defm : X86WriteRes<WriteVecMoveToGpr, [Zn2FPU2], 2, [1], 1>;
381 defm : X86WriteRes<WriteVecMoveFromGpr, [Zn2FPU2], 3, [1], 1>;
382 defm : X86WriteRes<WriteEMMS, [Zn2FPU], 2, [1], 1>;
384 defm : Zn2WriteResFpuPair<WriteVecShift, [Zn2FPU], 1>;
385 defm : Zn2WriteResFpuPair<WriteVecShiftX, [Zn2FPU2], 1>;
386 defm : Zn2WriteResFpuPair<WriteVecShiftY, [Zn2FPU2], 1>;
387 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
388 defm : Zn2WriteResFpuPair<WriteVecShiftImm, [Zn2FPU], 1>;
389 defm : Zn2WriteResFpuPair<WriteVecShiftImmX, [Zn2FPU], 1>;
390 defm : Zn2WriteResFpuPair<WriteVecShiftImmY, [Zn2FPU], 1>;
391 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
392 defm : Zn2WriteResFpuPair<WriteVecLogic, [Zn2FPU], 1>;
393 defm : Zn2WriteResFpuPair<WriteVecLogicX, [Zn2FPU], 1>;
394 defm : Zn2WriteResFpuPair<WriteVecLogicY, [Zn2FPU], 1>;
395 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
396 defm : Zn2WriteResFpuPair<WriteVecTest, [Zn2FPU12], 1, [2], 1, 7, 1>;
397 defm : Zn2WriteResFpuPair<WriteVecTestY, [Zn2FPU12], 1, [2], 1, 7, 1>;
398 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
399 defm : Zn2WriteResFpuPair<WriteVecALU, [Zn2FPU], 1>;
400 defm : Zn2WriteResFpuPair<WriteVecALUX, [Zn2FPU], 1>;
401 defm : Zn2WriteResFpuPair<WriteVecALUY, [Zn2FPU], 1>;
402 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
403 defm : Zn2WriteResFpuPair<WriteVecIMul, [Zn2FPU0], 4>;
404 defm : Zn2WriteResFpuPair<WriteVecIMulX, [Zn2FPU0], 4>;
405 defm : Zn2WriteResFpuPair<WriteVecIMulY, [Zn2FPU0], 4>;
406 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
407 defm : Zn2WriteResFpuPair<WritePMULLD, [Zn2FPU0], 4, [1], 1, 7, 1>;
408 defm : Zn2WriteResFpuPair<WritePMULLDY, [Zn2FPU0], 4, [1], 1, 7, 1>;
409 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
410 defm : Zn2WriteResFpuPair<WriteShuffle, [Zn2FPU], 1>;
411 defm : Zn2WriteResFpuPair<WriteShuffleX, [Zn2FPU], 1>;
412 defm : Zn2WriteResFpuPair<WriteShuffleY, [Zn2FPU], 1>;
413 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
414 defm : Zn2WriteResFpuPair<WriteVarShuffle, [Zn2FPU], 1>;
415 defm : Zn2WriteResFpuPair<WriteVarShuffleX,[Zn2FPU], 1>;
416 defm : Zn2WriteResFpuPair<WriteVarShuffleY,[Zn2FPU], 1>;
417 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
418 defm : Zn2WriteResFpuPair<WriteBlend, [Zn2FPU01], 1>;
419 defm : Zn2WriteResFpuPair<WriteBlendY, [Zn2FPU01], 1>;
420 defm : X86WriteResPairUnsupported<WriteBlendZ>;
421 defm : Zn2WriteResFpuPair<WriteShuffle256, [Zn2FPU], 2>;
422 defm : Zn2WriteResFpuPair<WriteVarShuffle256, [Zn2FPU], 2>;
423 defm : Zn2WriteResFpuPair<WritePSADBW, [Zn2FPU0], 3>;
424 defm : Zn2WriteResFpuPair<WritePSADBWX, [Zn2FPU0], 3>;
425 defm : Zn2WriteResFpuPair<WritePSADBWY, [Zn2FPU0], 3>;
426 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
427 defm : Zn2WriteResFpuPair<WritePHMINPOS, [Zn2FPU0], 4>;
429 // Vector Shift Operations
430 defm : Zn2WriteResFpuPair<WriteVarVecShift, [Zn2FPU12], 3>;
431 defm : Zn2WriteResFpuPair<WriteVarVecShiftY, [Zn2FPU12], 3>;
432 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
434 // Vector insert/extract operations.
435 defm : Zn2WriteResFpuPair<WriteVecInsert, [Zn2FPU], 1>;
437 def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
439 let ResourceCycles = [1, 2];
441 def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
444 let ResourceCycles = [1, 2, 3];
447 // MOVMSK Instructions.
448 def : WriteRes<WriteFMOVMSK, [Zn2FPU2]>;
449 def : WriteRes<WriteMMXMOVMSK, [Zn2FPU2]>;
450 def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
452 def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
455 let ResourceCycles = [2];
459 defm : Zn2WriteResFpuPair<WriteAESDecEnc, [Zn2FPU01], 4>;
460 defm : Zn2WriteResFpuPair<WriteAESIMC, [Zn2FPU01], 4>;
461 defm : Zn2WriteResFpuPair<WriteAESKeyGen, [Zn2FPU01], 4>;
463 def : WriteRes<WriteFence, [Zn2AGU]>;
464 def : WriteRes<WriteNop, []>;
466 // Following instructions with latency=100 are microcoded.
467 // We set long latency so as to block the entire pipeline.
468 defm : Zn2WriteResFpuPair<WriteFShuffle256, [Zn2FPU], 100>;
469 defm : Zn2WriteResFpuPair<WriteFVarShuffle256, [Zn2FPU], 100>;
471 // Microcoded Instructions
472 def Zn2WriteMicrocoded : SchedWriteRes<[]> {
475 defm : Zn2WriteResPair<WriteDPPS, [], 15>;
476 defm : Zn2WriteResPair<WriteFHAdd, [], 7>;
477 defm : Zn2WriteResPair<WriteFHAddY, [], 7>;
478 defm : Zn2WriteResPair<WritePHAdd, [], 3>;
479 defm : Zn2WriteResPair<WritePHAddX, [], 3>;
480 defm : Zn2WriteResPair<WritePHAddY, [], 3>;
482 def : SchedAlias<WriteMicrocoded, Zn2WriteMicrocoded>;
483 def : SchedAlias<WriteFCMOV, Zn2WriteMicrocoded>;
484 def : SchedAlias<WriteSystem, Zn2WriteMicrocoded>;
485 def : SchedAlias<WriteMPSAD, Zn2WriteMicrocoded>;
486 def : SchedAlias<WriteMPSADY, Zn2WriteMicrocoded>;
487 def : SchedAlias<WriteMPSADLd, Zn2WriteMicrocoded>;
488 def : SchedAlias<WriteMPSADYLd, Zn2WriteMicrocoded>;
489 def : SchedAlias<WriteCLMul, Zn2WriteMicrocoded>;
490 def : SchedAlias<WriteCLMulLd, Zn2WriteMicrocoded>;
491 def : SchedAlias<WritePCmpIStrM, Zn2WriteMicrocoded>;
492 def : SchedAlias<WritePCmpIStrMLd, Zn2WriteMicrocoded>;
493 def : SchedAlias<WritePCmpEStrI, Zn2WriteMicrocoded>;
494 def : SchedAlias<WritePCmpEStrILd, Zn2WriteMicrocoded>;
495 def : SchedAlias<WritePCmpEStrM, Zn2WriteMicrocoded>;
496 def : SchedAlias<WritePCmpEStrMLd, Zn2WriteMicrocoded>;
497 def : SchedAlias<WritePCmpIStrI, Zn2WriteMicrocoded>;
498 def : SchedAlias<WritePCmpIStrILd, Zn2WriteMicrocoded>;
499 def : SchedAlias<WriteLDMXCSR, Zn2WriteMicrocoded>;
500 def : SchedAlias<WriteSTMXCSR, Zn2WriteMicrocoded>;
502 //=== Regex based InstRW ===//
507 // - mm: 64 bit mmx register.
508 // - x = 128 bit xmm register.
509 // - (x)mm = mmx or xmm register.
510 // - y = 256 bit ymm register.
511 // - v = any vector register.
513 //=== Integer Instructions ===//
514 //-- Move instructions --//
517 def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>;
521 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
525 def Zn2WriteXCHG : SchedWriteRes<[Zn2ALU]> {
529 def : InstRW<[Zn2WriteXCHG], (instregex "^XCHG(8|16|32|64)rr", "^XCHG(16|32|64)ar")>;
532 def Zn2WriteXCHGrm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
536 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "^XCHG(8|16|32|64)rm")>;
538 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
542 def Zn2WritePop16r : SchedWriteRes<[Zn2AGU]>{
546 def : InstRW<[Zn2WritePop16r], (instregex "POP16rmm")>;
547 def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>;
548 def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>;
552 // r. Has default values.
554 def Zn2WritePUSH : SchedWriteRes<[Zn2AGU]>{
557 def : InstRW<[Zn2WritePUSH], (instregex "PUSH(16|32)rmm")>;
560 def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>;
563 def Zn2WritePushA : SchedWriteRes<[Zn2AGU]> {
566 def : InstRW<[Zn2WritePushA], (instregex "PUSHA(16|32)")>;
569 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
573 def Zn2WriteMOVBE : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
576 def : InstRW<[Zn2WriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>;
579 def : InstRW<[Zn2WriteMOVBE], (instregex "MOVBE(16|32|64)mr")>;
581 //-- Arithmetic instructions --//
585 def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
586 "(ADD|SUB)(8|16|32|64)mi8",
591 def : InstRW<[WriteALULd],
592 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
593 "(ADC|SBB)(16|32|64)mi8",
598 def : InstRW<[WriteALULd],
599 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>;
603 def Zn2WriteMul16 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
606 def Zn2WriteMul16Imm : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
609 def : SchedAlias<WriteIMul16, Zn2WriteMul16>;
610 def : SchedAlias<WriteIMul16Imm, Zn2WriteMul16Imm>;
611 def : SchedAlias<WriteIMul16Reg, Zn2WriteMul16>;
614 def Zn2WriteMul16Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
617 def : SchedAlias<WriteIMul16Ld, Zn2WriteMul16Ld>;
618 def : SchedAlias<WriteIMul16ImmLd, Zn2WriteMul16Ld>;
619 def : SchedAlias<WriteIMul16RegLd, Zn2WriteMul16Ld>;
622 def Zn2WriteMul32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
625 def : SchedAlias<WriteIMul32, Zn2WriteMul32>;
626 def : SchedAlias<WriteIMul32Imm, Zn2WriteMul32>;
627 def : SchedAlias<WriteIMul32Reg, Zn2WriteMul32>;
630 def Zn2WriteMul32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
633 def : SchedAlias<WriteIMul32Ld, Zn2WriteMul32Ld>;
634 def : SchedAlias<WriteIMul32ImmLd, Zn2WriteMul32Ld>;
635 def : SchedAlias<WriteIMul32RegLd, Zn2WriteMul32Ld>;
638 def Zn2WriteMul64 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
642 def : SchedAlias<WriteIMul64, Zn2WriteMul64>;
643 def : SchedAlias<WriteIMul64Imm, Zn2WriteMul64>;
644 def : SchedAlias<WriteIMul64Reg, Zn2WriteMul64>;
647 def Zn2WriteMul64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
651 def : SchedAlias<WriteIMul64Ld, Zn2WriteMul64Ld>;
652 def : SchedAlias<WriteIMul64ImmLd, Zn2WriteMul64Ld>;
653 def : SchedAlias<WriteIMul64RegLd, Zn2WriteMul64Ld>;
657 def Zn2WriteMulX32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
659 let ResourceCycles = [1, 2];
661 def : InstRW<[Zn2WriteMulX32], (instrs MULX32rr)>;
664 def Zn2WriteMulX32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
666 let ResourceCycles = [1, 2, 2];
668 def : InstRW<[Zn2WriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
671 def Zn2WriteMulX64 : SchedWriteRes<[Zn2ALU1]> {
674 def : InstRW<[Zn2WriteMulX64], (instrs MULX64rr)>;
677 def Zn2WriteMulX64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
680 def : InstRW<[Zn2WriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
682 //-- Control transfer instructions --//
685 def Zn2WriteJCXZ : SchedWriteRes<[Zn2ALU03]>;
686 def : InstRW<[Zn2WriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
689 def : InstRW<[WriteMicrocoded], (instrs INTO)>;
692 def Zn2WriteLOOP : SchedWriteRes<[Zn2ALU03]>;
693 def : InstRW<[Zn2WriteLOOP], (instrs LOOP)>;
695 // LOOP(N)E, LOOP(N)Z
696 def Zn2WriteLOOPE : SchedWriteRes<[Zn2ALU03]>;
697 def : InstRW<[Zn2WriteLOOPE], (instrs LOOPE, LOOPNE)>;
701 def Zn2WriteCALLr : SchedWriteRes<[Zn2AGU, Zn2ALU03]>;
702 def : InstRW<[Zn2WriteCALLr], (instregex "CALL(16|32)r")>;
704 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
707 def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
710 def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
713 //-- Logic instructions --//
717 def : InstRW<[WriteALULd],
718 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
719 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
721 // Define ALU latency variants
722 def Zn2WriteALULat2 : SchedWriteRes<[Zn2ALU]> {
725 def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
731 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
735 def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> {
739 def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
742 def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
747 def : SchedAlias<WriteBitTestSetImmRMW, Zn2WriteBTRSCm>;
748 def : SchedAlias<WriteBitTestSetRegRMW, Zn2WriteBTRSCm>;
752 def : SchedAlias<WriteBLS, Zn2WriteALULat2>;
754 def : SchedAlias<WriteBLSLd, Zn2WriteALULat2Ld>;
757 def : InstRW<[WriteALU], (instrs STD, CLD)>;
761 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
763 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
767 def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>;
771 def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
775 def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>;
778 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>;
781 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
783 //-- Misc instructions --//
785 def Zn2WriteCMPXCHG8B : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
786 let NumMicroOps = 18;
788 def : InstRW<[Zn2WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
790 def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>;
793 def Zn2WriteLEAVE : SchedWriteRes<[Zn2ALU, Zn2AGU]> {
797 def : InstRW<[Zn2WriteLEAVE], (instregex "LEAVE")>;
800 def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
803 def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
806 def : InstRW<[WriteMicrocoded], (instrs RDPMC)>;
809 def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>;
812 def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>;
814 //-- String instructions --//
816 def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>;
819 def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>;
822 def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>;
825 def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>;
828 def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>;
831 def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>;
834 def Zn2XADD : SchedWriteRes<[Zn2ALU]>;
835 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;
836 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
838 //=== Floating Point x87 Instructions ===//
839 //-- Move instructions --//
841 def Zn2WriteFLDr : SchedWriteRes<[Zn2FPU13]> ;
843 def Zn2WriteSTr: SchedWriteRes<[Zn2FPU23]> {
850 def : InstRW<[Zn2WriteFLDr], (instregex "LD_Frr")>;
853 def Zn2WriteLD_F80m : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
856 def : InstRW<[Zn2WriteLD_F80m], (instregex "LD_F80m")>;
859 def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>;
863 def : InstRW<[Zn2WriteSTr], (instregex "ST_(F|FP)rr")>;
866 def Zn2WriteST_FP80m : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
869 def : InstRW<[Zn2WriteST_FP80m], (instregex "ST_FP80m")>;
873 def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>;
875 def Zn2WriteFXCH : SchedWriteRes<[Zn2FPU]>;
878 def : InstRW<[Zn2WriteFXCH], (instrs XCH_F)>;
881 def Zn2WriteFILD : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
885 def : InstRW<[Zn2WriteFILD], (instregex "ILD_F(16|32|64)m")>;
888 def Zn2WriteFIST : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
891 def : InstRW<[Zn2WriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>;
893 def Zn2WriteFPU13 : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
897 def Zn2WriteFPU3 : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
902 def : SchedAlias<WriteFLD0, Zn2WriteFPU13>;
905 def : SchedAlias<WriteFLD1, Zn2WriteFPU3>;
908 def : SchedAlias<WriteFLDC, Zn2WriteFPU3>;
912 def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>;
915 def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>;
918 def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>;
921 def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>;
924 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
927 def : InstRW<[Zn2WriteFPU3], (instregex "FFREE")>;
930 def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>;
933 def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>;
935 //-- Arithmetic instructions --//
937 def Zn2WriteFPU3Lat1 : SchedWriteRes<[Zn2FPU3]> ;
939 def Zn2WriteFPU0Lat1 : SchedWriteRes<[Zn2FPU0]> ;
941 def Zn2WriteFPU0Lat1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU0]> {
946 def : InstRW<[Zn2WriteFPU3Lat1], (instregex "CHS_F")>;
950 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>;
952 def : InstRW<[Zn2WriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>;
956 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>;
958 def Zn2WriteFPU02 : SchedWriteRes<[Zn2AGU, Zn2FPU02]>
963 // FCOMI(P) FUCOMI(P).
965 def : InstRW<[Zn2WriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
967 def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
971 let ResourceCycles = [1,3];
975 def : InstRW<[Zn2WriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
978 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "TST_F")>;
981 def : InstRW<[Zn2WriteFPU3Lat1], (instrs FXAM)>;
984 def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
987 def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
990 def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
993 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
996 def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
999 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FNOP)>;
1002 def : InstRW<[Zn2WriteFPU0Lat1], (instrs WAIT)>;
1005 def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
1008 def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
1010 //=== Integer MMX and XMM Instructions ===//
1014 def Zn2WriteFPU12 : SchedWriteRes<[Zn2FPU12]> ;
1015 def Zn2WriteFPU12Y : SchedWriteRes<[Zn2FPU12]> {
1017 let NumMicroOps = 2;
1019 def Zn2WriteFPU12m : SchedWriteRes<[Zn2AGU, Zn2FPU12]> ;
1020 def Zn2WriteFPU12Ym : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1022 let NumMicroOps = 2;
1025 def : InstRW<[Zn2WriteFPU12], (instrs MMX_PACKSSDWirr,
1028 def : InstRW<[Zn2WriteFPU12m], (instrs MMX_PACKSSDWirm,
1032 // VPMOVSX/ZX BW BD BQ WD WQ DQ.
1034 def : InstRW<[Zn2WriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>;
1035 def : InstRW<[Zn2WriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>;
1037 def Zn2WriteFPU013 : SchedWriteRes<[Zn2FPU013]> ;
1038 def Zn2WriteFPU013Y : SchedWriteRes<[Zn2FPU013]> ;
1039 def Zn2WriteFPU013m : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1041 let NumMicroOps = 2;
1043 def Zn2WriteFPU013Ld : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1045 let NumMicroOps = 2;
1047 def Zn2WriteFPU013LdY : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1049 let NumMicroOps = 2;
1054 def : InstRW<[Zn2WriteFPU013], (instregex "(V?)PBLENDWrri")>;
1056 def : InstRW<[Zn2WriteFPU013Y], (instrs VPBLENDWYrri)>;
1059 def : InstRW<[Zn2WriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>;
1061 def : InstRW<[Zn2WriteFPU013LdY], (instrs VPBLENDWYrmi)>;
1063 def Zn2WriteFPU01 : SchedWriteRes<[Zn2FPU01]> ;
1064 def Zn2WriteFPU01Y : SchedWriteRes<[Zn2FPU01]> {
1065 let NumMicroOps = 2;
1070 def : InstRW<[Zn2WriteFPU01], (instrs VPBLENDDrri)>;
1072 def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
1075 def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1076 let NumMicroOps = 2;
1078 let ResourceCycles = [1, 2];
1080 def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1081 let NumMicroOps = 2;
1083 let ResourceCycles = [1, 3];
1085 def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
1086 def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
1089 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
1092 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
1096 def : InstRW<[WriteMicrocoded],
1097 (instregex "VPMASKMOVD(Y?)rm")>;
1099 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1103 def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1105 let NumMicroOps = 2;
1106 let ResourceCycles = [1, 2];
1108 def : InstRW<[Zn2WriteVPBROADCAST128Ld],
1109 (instregex "VPBROADCAST(B|W)rm")>;
1112 def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1114 let NumMicroOps = 2;
1115 let ResourceCycles = [1, 2];
1117 def : InstRW<[Zn2WriteVPBROADCAST256Ld],
1118 (instregex "VPBROADCAST(B|W)Yrm")>;
1121 def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
1123 //-- Arithmetic instructions --//
1126 def Zn2WritePCMPGTQr : SchedWriteRes<[Zn2FPU03]>;
1127 def : InstRW<[Zn2WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1130 def Zn2WritePCMPGTQm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1134 def Zn2WritePCMPGTQYm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1137 def : InstRW<[Zn2WritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
1138 def : InstRW<[Zn2WritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
1140 //-- Logic instructions --//
1142 // PSLL,PSRL,PSRA W/D/Q.
1144 def Zn2WritePShift : SchedWriteRes<[Zn2FPU2]> {
1147 def Zn2WritePShiftY : SchedWriteRes<[Zn2FPU2]> {
1152 def : InstRW<[Zn2WritePShift], (instregex "(V?)PS(R|L)LDQri")>;
1153 def : InstRW<[Zn2WritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>;
1155 //=== Floating Point XMM and YMM Instructions ===//
1156 //-- Move instructions --//
1159 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
1160 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>;
1162 def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
1163 let NumMicroOps = 2;
1167 def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128)>;
1171 def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1173 let ResourceCycles = [1, 2];
1175 def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1177 def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
1179 let NumMicroOps = 2;
1180 let ResourceCycles = [5, 1, 2];
1183 def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1187 def : InstRW<[Zn2WriteFPU013], (instrs VEXTRACTF128rr)>;
1190 def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr)>;
1192 def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
1194 // let ResourceCycles = [2];
1196 def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
1198 let NumMicroOps = 2;
1202 def : InstRW<[Zn2WriteVINSERT128r], (instrs VINSERTF128rr)>;
1203 def : InstRW<[Zn2WriteVINSERT128Ld], (instrs VINSERTF128rm)>;
1206 def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>;
1208 //-- Conversion instructions --//
1209 def Zn2WriteCVTPD2PSr: SchedWriteRes<[Zn2FPU3]> {
1212 def Zn2WriteCVTPD2PSYr: SchedWriteRes<[Zn2FPU3]> {
1218 def : SchedAlias<WriteCvtPD2PS, Zn2WriteCVTPD2PSr>;
1220 def : SchedAlias<WriteCvtPD2PSY, Zn2WriteCVTPD2PSYr>;
1222 defm : X86WriteResUnsupported<WriteCvtPD2PSZ>;
1224 def Zn2WriteCVTPD2PSLd: SchedWriteRes<[Zn2AGU,Zn2FPU03]> {
1226 let NumMicroOps = 2;
1229 def : SchedAlias<WriteCvtPD2PSLd, Zn2WriteCVTPD2PSLd>;
1232 def Zn2WriteCVTPD2PSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1235 def : SchedAlias<WriteCvtPD2PSYLd, Zn2WriteCVTPD2PSYLd>;
1237 defm : X86WriteResUnsupported<WriteCvtPD2PSZLd>;
1241 // Same as WriteCVTPD2PSr
1242 def : SchedAlias<WriteCvtSD2SS, Zn2WriteCVTPD2PSr>;
1245 def : SchedAlias<WriteCvtSD2SSLd, Zn2WriteCVTPD2PSLd>;
1249 def Zn2WriteCVTPS2PDr : SchedWriteRes<[Zn2FPU3]> {
1252 def : SchedAlias<WriteCvtPS2PD, Zn2WriteCVTPS2PDr>;
1256 def Zn2WriteCVTPS2PDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1258 let NumMicroOps = 2;
1260 def : SchedAlias<WriteCvtPS2PDLd, Zn2WriteCVTPS2PDLd>;
1261 def : SchedAlias<WriteCvtPS2PDYLd, Zn2WriteCVTPS2PDLd>;
1262 defm : X86WriteResUnsupported<WriteCvtPS2PDZLd>;
1265 def Zn2WriteVCVTPS2PDY : SchedWriteRes<[Zn2FPU3]> {
1268 def : SchedAlias<WriteCvtPS2PDY, Zn2WriteVCVTPS2PDY>;
1269 defm : X86WriteResUnsupported<WriteCvtPS2PDZ>;
1273 def Zn2WriteCVTSS2SDr : SchedWriteRes<[Zn2FPU3]> {
1276 def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
1279 def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1281 let NumMicroOps = 2;
1282 let ResourceCycles = [1, 2];
1284 def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;
1286 def Zn2WriteCVTDQ2PDr: SchedWriteRes<[Zn2FPU12,Zn2FPU3]> {
1291 def : InstRW<[Zn2WriteCVTDQ2PDr], (instregex "(V)?CVTDQ2P(D|S)rr")>;
1295 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>;
1296 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PSYrr)>;
1298 def Zn2WriteCVTPD2DQr: SchedWriteRes<[Zn2FPU12, Zn2FPU3]> {
1303 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)P(D|S)2DQrr")>;
1305 def Zn2WriteCVTPD2DQLd: SchedWriteRes<[Zn2AGU,Zn2FPU12,Zn2FPU3]> {
1307 let NumMicroOps = 2;
1310 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>;
1311 // same as xmm handling
1313 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
1315 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
1317 def Zn2WriteCVTPS2PIr: SchedWriteRes<[Zn2FPU3]> {
1322 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>;
1326 def : InstRW<[Zn2WriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>;
1330 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>;
1332 def Zn2WriteCVSTSI2SSr: SchedWriteRes<[Zn2FPU3]> {
1336 // same as CVTPD2DQr
1339 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>;
1340 // same as CVTPD2DQm
1342 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>;
1344 def Zn2WriteCVSTSI2SDr: SchedWriteRes<[Zn2FPU013, Zn2FPU3]> {
1349 def : InstRW<[Zn2WriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>;
1352 def Zn2WriteCVSTSI2SIr: SchedWriteRes<[Zn2FPU3, Zn2FPU2]> {
1355 def Zn2WriteCVSTSI2SILd: SchedWriteRes<[Zn2AGU, Zn2FPU3, Zn2FPU2]> {
1360 def : InstRW<[Zn2WriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>;
1362 def : InstRW<[Zn2WriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>;
1366 def : SchedAlias<WriteCvtPS2PH, Zn2WriteMicrocoded>;
1367 def : SchedAlias<WriteCvtPS2PHY, Zn2WriteMicrocoded>;
1368 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
1370 def : SchedAlias<WriteCvtPS2PHSt, Zn2WriteMicrocoded>;
1371 def : SchedAlias<WriteCvtPS2PHYSt, Zn2WriteMicrocoded>;
1372 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
1376 def : SchedAlias<WriteCvtPH2PS, Zn2WriteMicrocoded>;
1377 def : SchedAlias<WriteCvtPH2PSY, Zn2WriteMicrocoded>;
1378 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
1380 def : SchedAlias<WriteCvtPH2PSLd, Zn2WriteMicrocoded>;
1381 def : SchedAlias<WriteCvtPH2PSYLd, Zn2WriteMicrocoded>;
1382 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
1384 //-- SSE4A instructions --//
1386 def Zn2WriteEXTRQ: SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1389 def : InstRW<[Zn2WriteEXTRQ], (instregex "EXTRQ")>;
1392 def Zn2WriteINSERTQ: SchedWriteRes<[Zn2FPU03,Zn2FPU1]> {
1395 def : InstRW<[Zn2WriteINSERTQ], (instregex "INSERTQ")>;
1397 //-- SHA instructions --//
1399 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
1401 // SHA1MSG1, SHA256MSG1
1403 def Zn2WriteSHA1MSG1r : SchedWriteRes<[Zn2FPU12]> {
1406 def : InstRW<[Zn2WriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
1408 def Zn2WriteSHA1MSG1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1411 def : InstRW<[Zn2WriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;
1415 def Zn2WriteSHA1MSG2r : SchedWriteRes<[Zn2FPU12]> ;
1416 def : InstRW<[Zn2WriteSHA1MSG2r], (instregex "SHA1MSG2rr")>;
1418 def Zn2WriteSHA1MSG2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1421 def : InstRW<[Zn2WriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>;
1425 def Zn2WriteSHA1NEXTEr : SchedWriteRes<[Zn2FPU1]> ;
1426 def : InstRW<[Zn2WriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>;
1428 def Zn2WriteSHA1NEXTELd : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1431 def : InstRW<[Zn2WriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>;
1435 def Zn2WriteSHA1RNDS4r : SchedWriteRes<[Zn2FPU1]> {
1438 def : InstRW<[Zn2WriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>;
1440 def Zn2WriteSHA1RNDS4Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1443 def : InstRW<[Zn2WriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>;
1447 def Zn2WriteSHA256RNDS2r : SchedWriteRes<[Zn2FPU1]> {
1450 def : InstRW<[Zn2WriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>;
1452 def Zn2WriteSHA256RNDS2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1455 def : InstRW<[Zn2WriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>;
1457 //-- Arithmetic instructions --//
1460 // TODO - convert to Zn2WriteResFpuPair
1462 def Zn2WriteVDIVPSYr : SchedWriteRes<[Zn2FPU3]> {
1464 let ResourceCycles = [10];
1466 def : SchedAlias<WriteFDivY, Zn2WriteVDIVPSYr>;
1469 def Zn2WriteVDIVPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1471 let NumMicroOps = 2;
1472 let ResourceCycles = [1, 17];
1474 def : SchedAlias<WriteFDivYLd, Zn2WriteVDIVPSYLd>;
1477 // TODO - convert to Zn2WriteResFpuPair
1479 def Zn2WriteVDIVPDY : SchedWriteRes<[Zn2FPU3]> {
1481 let ResourceCycles = [13];
1483 def : SchedAlias<WriteFDiv64Y, Zn2WriteVDIVPDY>;
1486 def Zn2WriteVDIVPDYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1488 let NumMicroOps = 2;
1489 let ResourceCycles = [1,20];
1491 def : SchedAlias<WriteFDiv64YLd, Zn2WriteVDIVPDYLd>;
1495 def : SchedAlias<WriteDPPSY, Zn2WriteMicrocoded>;
1498 def : SchedAlias<WriteDPPSYLd,Zn2WriteMicrocoded>;
1502 def : SchedAlias<WriteDPPD, Zn2WriteMicrocoded>;
1505 def : SchedAlias<WriteDPPDLd, Zn2WriteMicrocoded>;
1508 // TODO - convert to Zn2WriteResFpuPair
1510 def Zn2WriteRSQRTSSr : SchedWriteRes<[Zn2FPU02]> {
1513 def : SchedAlias<WriteFRsqrt, Zn2WriteRSQRTSSr>;
1516 def Zn2WriteRSQRTSSLd: SchedWriteRes<[Zn2AGU, Zn2FPU02]> {
1518 let NumMicroOps = 2;
1519 let ResourceCycles = [1,2];
1521 def : SchedAlias<WriteFRsqrtLd, Zn2WriteRSQRTSSLd>;
1524 // TODO - convert to Zn2WriteResFpuPair
1526 def Zn2WriteRSQRTPSYr : SchedWriteRes<[Zn2FPU01]> {
1528 let NumMicroOps = 2;
1529 let ResourceCycles = [2];
1531 def : SchedAlias<WriteFRsqrtY, Zn2WriteRSQRTPSYr>;
1534 def Zn2WriteRSQRTPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1536 let NumMicroOps = 2;
1538 def : SchedAlias<WriteFRsqrtYLd, Zn2WriteRSQRTPSYLd>;
1540 //-- Other instructions --//
1543 def : InstRW<[WriteALU], (instrs VZEROUPPER)>;
1546 def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>;