contrib/llvm-project/llvm/lib/Target/X86/X86ScheduleZnver2.td

   1 //=- X86ScheduleZnver2.td - X86 Znver2 Scheduling -------------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Znver2 to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def Znver2Model : SchedMachineModel {
  15   // Zen can decode 4 instructions per cycle.
  16   let IssueWidth = 4;
  17   // Based on the reorder buffer we define MicroOpBufferSize
  18   let MicroOpBufferSize = 224;
  19   let LoadLatency = 4;
  20   let MispredictPenalty = 17;
  21   let HighLatency = 25;
  22   let PostRAScheduler = 1;
  23
  24   // FIXME: This variable is required for incomplete model.
  25   // We haven't catered all instructions.
  26   // So, we reset the value of this variable so as to
  27   // say that the model is incomplete.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = Znver2Model in {
  32
  33 // Zen can issue micro-ops to 10 different units in one cycle.
  34 // These are
  35 //  * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3)
  36 //  * Three AGU units (ZAGU0, ZAGU1, ZAGU2)
  37 //  * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3)
  38 // AGUs feed load store queues @two loads and 1 store per cycle.
  39
  40 // Four ALU units are defined below
  41 def Zn2ALU0 : ProcResource<1>;
  42 def Zn2ALU1 : ProcResource<1>;
  43 def Zn2ALU2 : ProcResource<1>;
  44 def Zn2ALU3 : ProcResource<1>;
  45
  46 // Three AGU units are defined below
  47 def Zn2AGU0 : ProcResource<1>;
  48 def Zn2AGU1 : ProcResource<1>;
  49 def Zn2AGU2 : ProcResource<1>;
  50
  51 // Four FPU units are defined below
  52 def Zn2FPU0 : ProcResource<1>;
  53 def Zn2FPU1 : ProcResource<1>;
  54 def Zn2FPU2 : ProcResource<1>;
  55 def Zn2FPU3 : ProcResource<1>;
  56
  57 // FPU grouping
  58 def Zn2FPU013  : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU3]>;
  59 def Zn2FPU01   : ProcResGroup<[Zn2FPU0, Zn2FPU1]>;
  60 def Zn2FPU12   : ProcResGroup<[Zn2FPU1, Zn2FPU2]>;
  61 def Zn2FPU13   : ProcResGroup<[Zn2FPU1, Zn2FPU3]>;
  62 def Zn2FPU23   : ProcResGroup<[Zn2FPU2, Zn2FPU3]>;
  63 def Zn2FPU02   : ProcResGroup<[Zn2FPU0, Zn2FPU2]>;
  64 def Zn2FPU03   : ProcResGroup<[Zn2FPU0, Zn2FPU3]>;
  65
  66 // Below are the grouping of the units.
  67 // Micro-ops to be issued to multiple units are tackled this way.
  68
  69 // ALU grouping
  70 // Zn2ALU03 - 0,3 grouping
  71 def Zn2ALU03: ProcResGroup<[Zn2ALU0, Zn2ALU3]>;
  72
  73 // 64 Entry (16x4 entries) Int Scheduler
  74 def Zn2ALU : ProcResGroup<[Zn2ALU0, Zn2ALU1, Zn2ALU2, Zn2ALU3]> {
  75   let BufferSize=64;
  76 }
  77
  78 // 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations
  79 // but are relevant for some instructions
  80 def Zn2AGU : ProcResGroup<[Zn2AGU0, Zn2AGU1, Zn2AGU2]> {
  81   let BufferSize=28;
  82 }
  83
  84 // Integer Multiplication issued on ALU1.
  85 def Zn2Multiplier : ProcResource<1>;
  86
  87 // Integer division issued on ALU2.
  88 def Zn2Divider : ProcResource<1>;
  89
  90 // 4 Cycles load-to use Latency is captured
  91 def : ReadAdvance<ReadAfterLd, 4>;
  92
  93 // 7 Cycles vector load-to use Latency is captured
  94 def : ReadAdvance<ReadAfterVecLd, 7>;
  95 def : ReadAdvance<ReadAfterVecXLd, 7>;
  96 def : ReadAdvance<ReadAfterVecYLd, 7>;
  97
  98 def : ReadAdvance<ReadInt2Fpu, 0>;
  99
 100 // The Integer PRF for Zen is 168 entries, and it holds the architectural and
 101 // speculative version of the 64-bit integer registers.
 102 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 103 def Zn2IntegerPRF : RegisterFile<168, [GR64, CCR]>;
 104
 105 // 36 Entry (9x4 entries) floating-point Scheduler
 106 def Zn2FPU     : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU2, Zn2FPU3]> {
 107   let BufferSize=36;
 108 }
 109
 110 // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
 111 // registers. Operations on 256-bit data types are cracked into two COPs.
 112 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
 114
 115 // The unit can track up to 192 macro ops in-flight.
 116 // The retire unit handles in-order commit of up to 8 macro ops per cycle.
 117 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 118 // To be noted, the retire unit is shared between integer and FP ops.
 119 // In SMT mode it is 96 entry per thread. But, we do not use the conservative
 120 // value here because there is currently no way to fully mode the SMT mode,
 121 // so there is no point in trying.
 122 def Zn2RCU : RetireControlUnit<192, 8>;
 123
 124 // (a folded load is an instruction that loads and does some operation)
 125 // Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops
 126 // Instructions with folded loads are usually micro-fused, so they only appear
 127 // as two micro-ops.
 128 //      a. load and
 129 //      b. addpd
 130 // This multiclass is for folded loads for integer units.
 131 multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
 132                           list<ProcResourceKind> ExePorts,
 133                           int Lat, list<int> Res = [], int UOps = 1,
 134                           int LoadLat = 4, int LoadUOps = 1> {
 135   // Register variant takes 1-cycle on Execution Port.
 136   def : WriteRes<SchedRW, ExePorts> {
 137     let Latency = Lat;
 138     let ResourceCycles = Res;
 139     let NumMicroOps = UOps;
 140   }
 141
 142   // Memory variant also uses a cycle on Zn2AGU
 143   // adds LoadLat cycles to the latency (default = 4).
 144   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
 145     let Latency = !add(Lat, LoadLat);
 146     let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
 147     let NumMicroOps = !add(UOps, LoadUOps);
 148   }
 149 }
 150
 151 // This multiclass is for folded loads for floating point units.
 152 multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
 153                           list<ProcResourceKind> ExePorts,
 154                           int Lat, list<int> Res = [], int UOps = 1,
 155                           int LoadLat = 7, int LoadUOps = 0> {
 156   // Register variant takes 1-cycle on Execution Port.
 157   def : WriteRes<SchedRW, ExePorts> {
 158     let Latency = Lat;
 159     let ResourceCycles = Res;
 160     let NumMicroOps = UOps;
 161   }
 162
 163   // Memory variant also uses a cycle on Zn2AGU
 164   // adds LoadLat cycles to the latency (default = 7).
 165   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
 166     let Latency = !add(Lat, LoadLat);
 167     let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
 168     let NumMicroOps = !add(UOps, LoadUOps);
 169   }
 170 }
 171
 172 // WriteRMW is set for instructions with Memory write
 173 // operation in codegen
 174 def : WriteRes<WriteRMW, [Zn2AGU]>;
 175
 176 def : WriteRes<WriteStore,   [Zn2AGU]>;
 177 def : WriteRes<WriteStoreNT, [Zn2AGU]>;
 178 def : WriteRes<WriteMove,    [Zn2ALU]>;
 179 def : WriteRes<WriteLoad,    [Zn2AGU]> { let Latency = 8; }
 180
 181 def : WriteRes<WriteZero,  []>;
 182 def : WriteRes<WriteLEA, [Zn2ALU]>;
 183 defm : Zn2WriteResPair<WriteALU,   [Zn2ALU], 1>;
 184 defm : Zn2WriteResPair<WriteADC,   [Zn2ALU], 1>;
 185
 186 defm : Zn2WriteResPair<WriteIMul8,     [Zn2ALU1, Zn2Multiplier], 4>;
 187
 188 defm : X86WriteRes<WriteBSWAP32, [Zn2ALU], 1, [4], 1>;
 189 defm : X86WriteRes<WriteBSWAP64, [Zn2ALU], 1, [4], 1>;
 190 defm : X86WriteRes<WriteCMPXCHG, [Zn2ALU], 1, [1], 1>;
 191 defm : X86WriteRes<WriteCMPXCHGRMW,[Zn2ALU,Zn2AGU], 8, [1,1], 5>;
 192 defm : X86WriteRes<WriteXCHG, [Zn2ALU], 1, [2], 2>;
 193
 194 defm : Zn2WriteResPair<WriteShift, [Zn2ALU], 1>;
 195 defm : Zn2WriteResPair<WriteShiftCL,  [Zn2ALU], 1>;
 196 defm : Zn2WriteResPair<WriteRotate,   [Zn2ALU], 1>;
 197 defm : Zn2WriteResPair<WriteRotateCL, [Zn2ALU], 1>;
 198
 199 defm : X86WriteRes<WriteSHDrri, [Zn2ALU], 1, [1], 1>;
 200 defm : X86WriteResUnsupported<WriteSHDrrcl>;
 201 defm : X86WriteResUnsupported<WriteSHDmri>;
 202 defm : X86WriteResUnsupported<WriteSHDmrcl>;
 203
 204 defm : Zn2WriteResPair<WriteJump,  [Zn2ALU], 1>;
 205 defm : Zn2WriteResFpuPair<WriteCRC32, [Zn2FPU0], 3>;
 206
 207 defm : Zn2WriteResPair<WriteCMOV,   [Zn2ALU], 1>;
 208 def  : WriteRes<WriteSETCC,  [Zn2ALU]>;
 209 def  : WriteRes<WriteSETCCStore,  [Zn2ALU, Zn2AGU]>;
 210 defm : X86WriteRes<WriteLAHFSAHF, [Zn2ALU], 2, [1], 2>;
 211
 212 defm : X86WriteRes<WriteBitTest,         [Zn2ALU], 1, [1], 1>;
 213 defm : X86WriteRes<WriteBitTestImmLd,    [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
 214 defm : X86WriteRes<WriteBitTestRegLd,    [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
 215 defm : X86WriteRes<WriteBitTestSet,      [Zn2ALU], 2, [1], 2>;
 216
 217 // Bit counts.
 218 defm : Zn2WriteResPair<WriteBSF, [Zn2ALU], 3>;
 219 defm : Zn2WriteResPair<WriteBSR, [Zn2ALU], 3>;
 220 defm : Zn2WriteResPair<WriteLZCNT,          [Zn2ALU], 1>;
 221 defm : Zn2WriteResPair<WriteTZCNT,          [Zn2ALU], 2>;
 222 defm : Zn2WriteResPair<WritePOPCNT,         [Zn2ALU], 1>;
 223
 224 // Treat misc copies as a move.
 225 def : InstRW<[WriteMove], (instrs COPY)>;
 226
 227 // BMI1 BEXTR, BMI2 BZHI
 228 defm : Zn2WriteResPair<WriteBEXTR, [Zn2ALU], 1>;
 229 defm : Zn2WriteResPair<WriteBZHI, [Zn2ALU], 1>;
 230
 231 // IDIV
 232 defm : Zn2WriteResPair<WriteDiv8,   [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
 233 defm : Zn2WriteResPair<WriteDiv16,  [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
 234 defm : Zn2WriteResPair<WriteDiv32,  [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 235 defm : Zn2WriteResPair<WriteDiv64,  [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 236 defm : Zn2WriteResPair<WriteIDiv8,  [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
 237 defm : Zn2WriteResPair<WriteIDiv16, [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
 238 defm : Zn2WriteResPair<WriteIDiv32, [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 239 defm : Zn2WriteResPair<WriteIDiv64, [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 240
 241 // IMULH
 242 def  : WriteRes<WriteIMulH, [Zn2ALU1, Zn2Multiplier]>{
 243   let Latency = 4;
 244 }
 245
 246 // Floating point operations
 247 defm : X86WriteRes<WriteFLoad,         [Zn2AGU], 8, [1], 1>;
 248 defm : X86WriteRes<WriteFLoadX,        [Zn2AGU], 8, [1], 1>;
 249 defm : X86WriteRes<WriteFLoadY,        [Zn2AGU], 8, [1], 1>;
 250 defm : X86WriteRes<WriteFMaskedLoad,   [Zn2AGU,Zn2FPU01], 8, [1,1], 1>;
 251 defm : X86WriteRes<WriteFMaskedLoadY,  [Zn2AGU,Zn2FPU01], 8, [1,1], 2>;
 252 defm : X86WriteRes<WriteFMaskedStore32,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 253 defm : X86WriteRes<WriteFMaskedStore32Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 254 defm : X86WriteRes<WriteFMaskedStore64,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 255 defm : X86WriteRes<WriteFMaskedStore64Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 256
 257 defm : X86WriteRes<WriteFStore,        [Zn2AGU], 1, [1], 1>;
 258 defm : X86WriteRes<WriteFStoreX,       [Zn2AGU], 1, [1], 1>;
 259 defm : X86WriteRes<WriteFStoreY,       [Zn2AGU], 1, [1], 1>;
 260 defm : X86WriteRes<WriteFStoreNT,      [Zn2AGU,Zn2FPU2], 8, [1,1], 1>;
 261 defm : X86WriteRes<WriteFStoreNTX,     [Zn2AGU], 1, [1], 1>;
 262 defm : X86WriteRes<WriteFStoreNTY,     [Zn2AGU], 1, [1], 1>;
 263 defm : X86WriteRes<WriteFMove,         [Zn2FPU], 1, [1], 1>;
 264 defm : X86WriteRes<WriteFMoveX,        [Zn2FPU], 1, [1], 1>;
 265 defm : X86WriteRes<WriteFMoveY,        [Zn2FPU], 1, [1], 1>;
 266
 267 defm : Zn2WriteResFpuPair<WriteFAdd,      [Zn2FPU0],  3>;
 268 defm : Zn2WriteResFpuPair<WriteFAddX,     [Zn2FPU0],  3>;
 269 defm : Zn2WriteResFpuPair<WriteFAddY,     [Zn2FPU0],  3>;
 270 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 271 defm : Zn2WriteResFpuPair<WriteFAdd64,    [Zn2FPU0],  3>;
 272 defm : Zn2WriteResFpuPair<WriteFAdd64X,   [Zn2FPU0],  3>;
 273 defm : Zn2WriteResFpuPair<WriteFAdd64Y,   [Zn2FPU0],  3>;
 274 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 275 defm : Zn2WriteResFpuPair<WriteFCmp,      [Zn2FPU0],  3>;
 276 defm : Zn2WriteResFpuPair<WriteFCmpX,     [Zn2FPU0],  3>;
 277 defm : Zn2WriteResFpuPair<WriteFCmpY,     [Zn2FPU0],  3>;
 278 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 279 defm : Zn2WriteResFpuPair<WriteFCmp64,    [Zn2FPU0],  3>;
 280 defm : Zn2WriteResFpuPair<WriteFCmp64X,   [Zn2FPU0],  3>;
 281 defm : Zn2WriteResFpuPair<WriteFCmp64Y,   [Zn2FPU0],  3>;
 282 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 283 defm : Zn2WriteResFpuPair<WriteFCom,      [Zn2FPU0],  3>;
 284 defm : Zn2WriteResFpuPair<WriteFBlend,    [Zn2FPU01], 1>;
 285 defm : Zn2WriteResFpuPair<WriteFBlendY,   [Zn2FPU01], 1>;
 286 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 287 defm : Zn2WriteResFpuPair<WriteFVarBlend, [Zn2FPU01], 1>;
 288 defm : Zn2WriteResFpuPair<WriteFVarBlendY,[Zn2FPU01], 1>;
 289 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 290 defm : Zn2WriteResFpuPair<WriteVarBlend,  [Zn2FPU0],  1>;
 291 defm : Zn2WriteResFpuPair<WriteVarBlendY, [Zn2FPU0],  1>;
 292 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 293 defm : Zn2WriteResFpuPair<WriteCvtSS2I,   [Zn2FPU3],  5>;
 294 defm : Zn2WriteResFpuPair<WriteCvtPS2I,   [Zn2FPU3],  5>;
 295 defm : Zn2WriteResFpuPair<WriteCvtPS2IY,  [Zn2FPU3],  5>;
 296 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 297 defm : Zn2WriteResFpuPair<WriteCvtSD2I,   [Zn2FPU3],  5>;
 298 defm : Zn2WriteResFpuPair<WriteCvtPD2I,   [Zn2FPU3],  5>;
 299 defm : Zn2WriteResFpuPair<WriteCvtPD2IY,  [Zn2FPU3],  5>;
 300 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 301 defm : Zn2WriteResFpuPair<WriteCvtI2SS,   [Zn2FPU3],  5>;
 302 defm : Zn2WriteResFpuPair<WriteCvtI2PS,   [Zn2FPU3],  5>;
 303 defm : Zn2WriteResFpuPair<WriteCvtI2PSY,  [Zn2FPU3],  5>;
 304 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 305 defm : Zn2WriteResFpuPair<WriteCvtI2SD,   [Zn2FPU3],  5>;
 306 defm : Zn2WriteResFpuPair<WriteCvtI2PD,   [Zn2FPU3],  5>;
 307 defm : Zn2WriteResFpuPair<WriteCvtI2PDY,  [Zn2FPU3],  5>;
 308 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 309 defm : Zn2WriteResFpuPair<WriteFDiv,      [Zn2FPU3], 15>;
 310 defm : Zn2WriteResFpuPair<WriteFDivX,     [Zn2FPU3], 15>;
 311 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 312 defm : Zn2WriteResFpuPair<WriteFDiv64,    [Zn2FPU3], 15>;
 313 defm : Zn2WriteResFpuPair<WriteFDiv64X,   [Zn2FPU3], 15>;
 314 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 315 defm : Zn2WriteResFpuPair<WriteFSign,     [Zn2FPU3],  2>;
 316 defm : Zn2WriteResFpuPair<WriteFRnd,      [Zn2FPU3],  4, [1], 1, 7, 0>;
 317 defm : Zn2WriteResFpuPair<WriteFRndY,     [Zn2FPU3],  4, [1], 1, 7, 0>;
 318 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 319 defm : Zn2WriteResFpuPair<WriteFLogic,    [Zn2FPU],   1>;
 320 defm : Zn2WriteResFpuPair<WriteFLogicY,   [Zn2FPU],   1>;
 321 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 322 defm : Zn2WriteResFpuPair<WriteFTest,     [Zn2FPU],   1>;
 323 defm : Zn2WriteResFpuPair<WriteFTestY,    [Zn2FPU],   1>;
 324 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 325 defm : Zn2WriteResFpuPair<WriteFShuffle,  [Zn2FPU12], 1>;
 326 defm : Zn2WriteResFpuPair<WriteFShuffleY, [Zn2FPU12], 1>;
 327 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 328 defm : Zn2WriteResFpuPair<WriteFVarShuffle, [Zn2FPU12], 1>;
 329 defm : Zn2WriteResFpuPair<WriteFVarShuffleY,[Zn2FPU12], 1>;
 330 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 331 defm : Zn2WriteResFpuPair<WriteFMul,      [Zn2FPU01], 3, [1], 1, 7, 1>;
 332 defm : Zn2WriteResFpuPair<WriteFMulX,     [Zn2FPU01], 3, [1], 1, 7, 1>;
 333 defm : Zn2WriteResFpuPair<WriteFMulY,     [Zn2FPU01], 4, [1], 1, 7, 1>;
 334 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 335 defm : Zn2WriteResFpuPair<WriteFMul64,    [Zn2FPU01], 3, [1], 1, 7, 1>;
 336 defm : Zn2WriteResFpuPair<WriteFMul64X,   [Zn2FPU01], 3, [1], 1, 7, 1>;
 337 defm : Zn2WriteResFpuPair<WriteFMul64Y,   [Zn2FPU01], 4, [1], 1, 7, 1>;
 338 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 339 defm : Zn2WriteResFpuPair<WriteFMA,       [Zn2FPU03], 5>;
 340 defm : Zn2WriteResFpuPair<WriteFMAX,      [Zn2FPU03], 5>;
 341 defm : Zn2WriteResFpuPair<WriteFMAY,      [Zn2FPU03], 5>;
 342 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 343 defm : Zn2WriteResFpuPair<WriteFRcp,      [Zn2FPU01], 5>;
 344 defm : Zn2WriteResFpuPair<WriteFRcpX,     [Zn2FPU01], 5>;
 345 defm : Zn2WriteResFpuPair<WriteFRcpY,     [Zn2FPU01], 5, [1], 1, 7, 2>;
 346 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 347 defm : Zn2WriteResFpuPair<WriteFRsqrtX,   [Zn2FPU01], 5, [1], 1, 7, 1>;
 348 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 349 defm : Zn2WriteResFpuPair<WriteFSqrt,     [Zn2FPU3], 20, [20]>;
 350 defm : Zn2WriteResFpuPair<WriteFSqrtX,    [Zn2FPU3], 20, [20]>;
 351 defm : Zn2WriteResFpuPair<WriteFSqrtY,    [Zn2FPU3], 28, [28], 1, 7, 1>;
 352 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 353 defm : Zn2WriteResFpuPair<WriteFSqrt64,   [Zn2FPU3], 20, [20]>;
 354 defm : Zn2WriteResFpuPair<WriteFSqrt64X,  [Zn2FPU3], 20, [20]>;
 355 defm : Zn2WriteResFpuPair<WriteFSqrt64Y,  [Zn2FPU3], 20, [20], 1, 7, 1>;
 356 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 357 defm : Zn2WriteResFpuPair<WriteFSqrt80,   [Zn2FPU3], 20, [20]>;
 358
 359 // Vector integer operations which uses FPU units
 360 defm : X86WriteRes<WriteVecLoad,         [Zn2AGU], 8, [1], 1>;
 361 defm : X86WriteRes<WriteVecLoadX,        [Zn2AGU], 8, [1], 1>;
 362 defm : X86WriteRes<WriteVecLoadY,        [Zn2AGU], 8, [1], 1>;
 363 defm : X86WriteRes<WriteVecLoadNT,       [Zn2AGU], 8, [1], 1>;
 364 defm : X86WriteRes<WriteVecLoadNTY,      [Zn2AGU], 8, [1], 1>;
 365 defm : X86WriteRes<WriteVecMaskedLoad,   [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
 366 defm : X86WriteRes<WriteVecMaskedLoadY,  [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
 367 defm : X86WriteRes<WriteVecStore,        [Zn2AGU], 1, [1], 1>;
 368 defm : X86WriteRes<WriteVecStoreX,       [Zn2AGU], 1, [1], 1>;
 369 defm : X86WriteRes<WriteVecStoreY,       [Zn2AGU], 1, [1], 1>;
 370 defm : X86WriteRes<WriteVecStoreNT,      [Zn2AGU], 1, [1], 1>;
 371 defm : X86WriteRes<WriteVecStoreNTY,     [Zn2AGU], 1, [1], 1>;
 372 defm : X86WriteRes<WriteVecMaskedStore,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 373 defm : X86WriteRes<WriteVecMaskedStoreY, [Zn2AGU,Zn2FPU01], 5, [1,1], 2>;
 374 defm : X86WriteRes<WriteVecMove,         [Zn2FPU], 1, [1], 1>;
 375 defm : X86WriteRes<WriteVecMoveX,        [Zn2FPU], 1, [1], 1>;
 376 defm : X86WriteRes<WriteVecMoveY,        [Zn2FPU], 2, [1], 2>;
 377 defm : X86WriteRes<WriteVecMoveToGpr,    [Zn2FPU2], 2, [1], 1>;
 378 defm : X86WriteRes<WriteVecMoveFromGpr,  [Zn2FPU2], 3, [1], 1>;
 379 defm : X86WriteRes<WriteEMMS,            [Zn2FPU], 2, [1], 1>;
 380
 381 defm : Zn2WriteResFpuPair<WriteVecShift,   [Zn2FPU],   1>;
 382 defm : Zn2WriteResFpuPair<WriteVecShiftX,  [Zn2FPU2],  1>;
 383 defm : Zn2WriteResFpuPair<WriteVecShiftY,  [Zn2FPU2],  2>;
 384 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 385 defm : Zn2WriteResFpuPair<WriteVecShiftImm,  [Zn2FPU], 1>;
 386 defm : Zn2WriteResFpuPair<WriteVecShiftImmX, [Zn2FPU], 1>;
 387 defm : Zn2WriteResFpuPair<WriteVecShiftImmY, [Zn2FPU], 1>;
 388 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 389 defm : Zn2WriteResFpuPair<WriteVecLogic,   [Zn2FPU],   1>;
 390 defm : Zn2WriteResFpuPair<WriteVecLogicX,  [Zn2FPU],   1>;
 391 defm : Zn2WriteResFpuPair<WriteVecLogicY,  [Zn2FPU],   1>;
 392 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 393 defm : Zn2WriteResFpuPair<WriteVecTest,    [Zn2FPU12], 1, [2], 1, 7, 1>;
 394 defm : Zn2WriteResFpuPair<WriteVecTestY,   [Zn2FPU12], 1, [2], 1, 7, 1>;
 395 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 396 defm : Zn2WriteResFpuPair<WriteVecALU,     [Zn2FPU],   1>;
 397 defm : Zn2WriteResFpuPair<WriteVecALUX,    [Zn2FPU],   1>;
 398 defm : Zn2WriteResFpuPair<WriteVecALUY,    [Zn2FPU],   1>;
 399 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 400 defm : Zn2WriteResFpuPair<WriteVecIMul,    [Zn2FPU0],  4>;
 401 defm : Zn2WriteResFpuPair<WriteVecIMulX,   [Zn2FPU0],  4>;
 402 defm : Zn2WriteResFpuPair<WriteVecIMulY,   [Zn2FPU0],  4>;
 403 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 404 defm : Zn2WriteResFpuPair<WritePMULLD,     [Zn2FPU0],  4, [1], 1, 7, 1>;
 405 defm : Zn2WriteResFpuPair<WritePMULLDY,    [Zn2FPU0],  3, [1], 1, 7, 1>;
 406 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 407 defm : Zn2WriteResFpuPair<WriteShuffle,    [Zn2FPU],   1>;
 408 defm : Zn2WriteResFpuPair<WriteShuffleX,   [Zn2FPU],   1>;
 409 defm : Zn2WriteResFpuPair<WriteShuffleY,   [Zn2FPU],   1>;
 410 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 411 defm : Zn2WriteResFpuPair<WriteVarShuffle, [Zn2FPU],   1>;
 412 defm : Zn2WriteResFpuPair<WriteVarShuffleX,[Zn2FPU],   1>;
 413 defm : Zn2WriteResFpuPair<WriteVarShuffleY,[Zn2FPU],   1>;
 414 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 415 defm : Zn2WriteResFpuPair<WriteBlend,      [Zn2FPU01], 1>;
 416 defm : Zn2WriteResFpuPair<WriteBlendY,     [Zn2FPU01], 1>;
 417 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 418 defm : Zn2WriteResFpuPair<WriteShuffle256, [Zn2FPU],   2>;
 419 defm : Zn2WriteResFpuPair<WriteVarShuffle256, [Zn2FPU],   2>;
 420 defm : Zn2WriteResFpuPair<WritePSADBW,     [Zn2FPU0],  3>;
 421 defm : Zn2WriteResFpuPair<WritePSADBWX,    [Zn2FPU0],  3>;
 422 defm : Zn2WriteResFpuPair<WritePSADBWY,    [Zn2FPU0],  3>;
 423 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 424 defm : Zn2WriteResFpuPair<WritePHMINPOS,   [Zn2FPU0],  4>;
 425
 426 // Vector Shift Operations
 427 defm : Zn2WriteResFpuPair<WriteVarVecShift,  [Zn2FPU12], 1>;
 428 defm : Zn2WriteResFpuPair<WriteVarVecShiftY, [Zn2FPU12], 1>;
 429 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 430
 431 // Vector insert/extract operations.
 432 defm : Zn2WriteResFpuPair<WriteVecInsert,   [Zn2FPU],   1>;
 433
 434 def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
 435   let Latency = 2;
 436   let ResourceCycles = [1, 2];
 437 }
 438 def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
 439   let Latency = 5;
 440   let NumMicroOps = 2;
 441   let ResourceCycles = [1, 2, 3];
 442 }
 443
 444 // MOVMSK Instructions.
 445 def : WriteRes<WriteFMOVMSK, [Zn2FPU2]>;
 446 def : WriteRes<WriteMMXMOVMSK, [Zn2FPU2]>;
 447 def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
 448
 449 def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
 450   let NumMicroOps = 2;
 451   let Latency = 2;
 452   let ResourceCycles = [2];
 453 }
 454
 455 // AES Instructions.
 456 defm : Zn2WriteResFpuPair<WriteAESDecEnc, [Zn2FPU01], 4>;
 457 defm : Zn2WriteResFpuPair<WriteAESIMC,    [Zn2FPU01], 4>;
 458 defm : Zn2WriteResFpuPair<WriteAESKeyGen, [Zn2FPU01], 4>;
 459
 460 def : WriteRes<WriteFence,  [Zn2AGU]>;
 461 def : WriteRes<WriteNop, []>;
 462
 463 // Following instructions with latency=100 are microcoded.
 464 // We set long latency so as to block the entire pipeline.
 465 defm : Zn2WriteResFpuPair<WriteFShuffle256, [Zn2FPU], 100>;
 466 defm : Zn2WriteResFpuPair<WriteFVarShuffle256, [Zn2FPU], 100>;
 467
 468 // Microcoded Instructions
 469 def Zn2WriteMicrocoded : SchedWriteRes<[]> {
 470   let Latency = 100;
 471 }
 472
 473 def : SchedAlias<WriteMicrocoded, Zn2WriteMicrocoded>;
 474 def : SchedAlias<WriteFCMOV, Zn2WriteMicrocoded>;
 475 def : SchedAlias<WriteSystem, Zn2WriteMicrocoded>;
 476 def : SchedAlias<WriteMPSAD, Zn2WriteMicrocoded>;
 477 def : SchedAlias<WriteMPSADY, Zn2WriteMicrocoded>;
 478 def : SchedAlias<WriteMPSADLd, Zn2WriteMicrocoded>;
 479 def : SchedAlias<WriteMPSADYLd, Zn2WriteMicrocoded>;
 480 def : SchedAlias<WriteCLMul, Zn2WriteMicrocoded>;
 481 def : SchedAlias<WriteCLMulLd, Zn2WriteMicrocoded>;
 482 def : SchedAlias<WritePCmpIStrM, Zn2WriteMicrocoded>;
 483 def : SchedAlias<WritePCmpIStrMLd, Zn2WriteMicrocoded>;
 484 def : SchedAlias<WritePCmpEStrI, Zn2WriteMicrocoded>;
 485 def : SchedAlias<WritePCmpEStrILd, Zn2WriteMicrocoded>;
 486 def : SchedAlias<WritePCmpEStrM, Zn2WriteMicrocoded>;
 487 def : SchedAlias<WritePCmpEStrMLd, Zn2WriteMicrocoded>;
 488 def : SchedAlias<WritePCmpIStrI, Zn2WriteMicrocoded>;
 489 def : SchedAlias<WritePCmpIStrILd, Zn2WriteMicrocoded>;
 490 def : SchedAlias<WriteLDMXCSR, Zn2WriteMicrocoded>;
 491 def : SchedAlias<WriteSTMXCSR, Zn2WriteMicrocoded>;
 492
 493 //=== Regex based InstRW ===//
 494 // Notation:
 495 // - r: register.
 496 // - m = memory.
 497 // - i = immediate
 498 // - mm: 64 bit mmx register.
 499 // - x = 128 bit xmm register.
 500 // - (x)mm = mmx or xmm register.
 501 // - y = 256 bit ymm register.
 502 // - v = any vector register.
 503
 504 //=== Integer Instructions ===//
 505 //-- Move instructions --//
 506 // MOV.
 507 // r16,m.
 508 def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>;
 509
 510 // MOVSX, MOVZX.
 511 // r,m.
 512 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
 513
 514 // XCHG.
 515 // r,r.
 516 def Zn2WriteXCHG : SchedWriteRes<[Zn2ALU]> {
 517   let NumMicroOps = 2;
 518 }
 519
 520 def : InstRW<[Zn2WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
 521
 522 // r,m.
 523 def Zn2WriteXCHGrm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 524   let Latency = 5;
 525   let NumMicroOps = 2;
 526 }
 527 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
 528
 529 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
 530
 531 // POP16.
 532 // r.
 533 def Zn2WritePop16r : SchedWriteRes<[Zn2AGU]>{
 534   let Latency = 5;
 535   let NumMicroOps = 2;
 536 }
 537 def : InstRW<[Zn2WritePop16r], (instregex "POP16rmm")>;
 538 def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>;
 539 def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>;
 540
 541
 542 // PUSH.
 543 // r. Has default values.
 544 // m.
 545 def Zn2WritePUSH : SchedWriteRes<[Zn2AGU]>{
 546   let Latency = 4;
 547 }
 548 def : InstRW<[Zn2WritePUSH], (instregex "PUSH(16|32)rmm")>;
 549
 550 //PUSHF
 551 def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>;
 552
 553 // PUSHA.
 554 def Zn2WritePushA : SchedWriteRes<[Zn2AGU]> {
 555   let Latency = 8;
 556 }
 557 def : InstRW<[Zn2WritePushA], (instregex "PUSHA(16|32)")>;
 558
 559 //LAHF
 560 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
 561
 562 // MOVBE.
 563 // r,m.
 564 def Zn2WriteMOVBE : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 565   let Latency = 5;
 566 }
 567 def : InstRW<[Zn2WriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>;
 568
 569 // m16,r16.
 570 def : InstRW<[Zn2WriteMOVBE], (instregex "MOVBE(16|32|64)mr")>;
 571
 572 //-- Arithmetic instructions --//
 573
 574 // ADD SUB.
 575 // m,r/i.
 576 def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
 577                           "(ADD|SUB)(8|16|32|64)mi8",
 578                           "(ADD|SUB)64mi32")>;
 579
 580 // ADC SBB.
 581 // m,r/i.
 582 def : InstRW<[WriteALULd],
 583              (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
 584               "(ADC|SBB)(16|32|64)mi8",
 585               "(ADC|SBB)64mi32")>;
 586
 587 // INC DEC NOT NEG.
 588 // m.
 589 def : InstRW<[WriteALULd],
 590              (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>;
 591
 592 // MUL IMUL.
 593 // r16.
 594 def Zn2WriteMul16 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 595   let Latency = 3;
 596 }
 597 def : SchedAlias<WriteIMul16, Zn2WriteMul16>;
 598 def : SchedAlias<WriteIMul16Imm, Zn2WriteMul16>;
 599 def : SchedAlias<WriteIMul16Reg, Zn2WriteMul16>;
 600
 601 // m16.
 602 def Zn2WriteMul16Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 603   let Latency = 7;
 604 }
 605 def : SchedAlias<WriteIMul16Ld, Zn2WriteMul16Ld>;
 606 def : SchedAlias<WriteIMul16ImmLd, Zn2WriteMul16Ld>;
 607 def : SchedAlias<WriteIMul16RegLd, Zn2WriteMul16Ld>;
 608
 609 // r32.
 610 def Zn2WriteMul32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 611   let Latency = 3;
 612 }
 613 def : SchedAlias<WriteIMul32, Zn2WriteMul32>;
 614 def : SchedAlias<WriteIMul32Imm, Zn2WriteMul32>;
 615 def : SchedAlias<WriteIMul32Reg, Zn2WriteMul32>;
 616
 617 // m32.
 618 def Zn2WriteMul32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 619   let Latency = 7;
 620 }
 621 def : SchedAlias<WriteIMul32Ld, Zn2WriteMul32Ld>;
 622 def : SchedAlias<WriteIMul32ImmLd, Zn2WriteMul32Ld>;
 623 def : SchedAlias<WriteIMul32RegLd, Zn2WriteMul32Ld>;
 624
 625 // r64.
 626 def Zn2WriteMul64 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 627   let Latency = 4;
 628   let NumMicroOps = 2;
 629 }
 630 def : SchedAlias<WriteIMul64, Zn2WriteMul64>;
 631 def : SchedAlias<WriteIMul64Imm, Zn2WriteMul64>;
 632 def : SchedAlias<WriteIMul64Reg, Zn2WriteMul64>;
 633
 634 // m64.
 635 def Zn2WriteMul64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 636   let Latency = 8;
 637   let NumMicroOps = 2;
 638 }
 639 def : SchedAlias<WriteIMul64Ld, Zn2WriteMul64Ld>;
 640 def : SchedAlias<WriteIMul64ImmLd, Zn2WriteMul64Ld>;
 641 def : SchedAlias<WriteIMul64RegLd, Zn2WriteMul64Ld>;
 642
 643 // MULX.
 644 // r32,r32,r32.
 645 def Zn2WriteMulX32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 646   let Latency = 3;
 647   let ResourceCycles = [1, 2];
 648 }
 649 def : InstRW<[Zn2WriteMulX32], (instrs MULX32rr)>;
 650
 651 // r32,r32,m32.
 652 def Zn2WriteMulX32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 653   let Latency = 7;
 654   let ResourceCycles = [1, 2, 2];
 655 }
 656 def : InstRW<[Zn2WriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
 657
 658 // r64,r64,r64.
 659 def Zn2WriteMulX64 : SchedWriteRes<[Zn2ALU1]> {
 660   let Latency = 3;
 661 }
 662 def : InstRW<[Zn2WriteMulX64], (instrs MULX64rr)>;
 663
 664 // r64,r64,m64.
 665 def Zn2WriteMulX64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 666   let Latency = 7;
 667 }
 668 def : InstRW<[Zn2WriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
 669
 670 //-- Control transfer instructions --//
 671
 672 // J(E|R)CXZ.
 673 def Zn2WriteJCXZ : SchedWriteRes<[Zn2ALU03]>;
 674 def : InstRW<[Zn2WriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
 675
 676 // INTO
 677 def : InstRW<[WriteMicrocoded], (instrs INTO)>;
 678
 679 // LOOP.
 680 def Zn2WriteLOOP : SchedWriteRes<[Zn2ALU03]>;
 681 def : InstRW<[Zn2WriteLOOP], (instrs LOOP)>;
 682
 683 // LOOP(N)E, LOOP(N)Z
 684 def Zn2WriteLOOPE : SchedWriteRes<[Zn2ALU03]>;
 685 def : InstRW<[Zn2WriteLOOPE], (instrs LOOPE, LOOPNE)>;
 686
 687 // CALL.
 688 // r.
 689 def Zn2WriteCALLr : SchedWriteRes<[Zn2AGU, Zn2ALU03]>;
 690 def : InstRW<[Zn2WriteCALLr], (instregex "CALL(16|32)r")>;
 691
 692 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
 693
 694 // RET.
 695 def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
 696   let NumMicroOps = 2;
 697 }
 698 def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
 699                             "IRET(16|32|64)")>;
 700
 701 //-- Logic instructions --//
 702
 703 // AND OR XOR.
 704 // m,r/i.
 705 def : InstRW<[WriteALULd],
 706              (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
 707               "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
 708
 709 // Define ALU latency variants
 710 def Zn2WriteALULat2 : SchedWriteRes<[Zn2ALU]> {
 711   let Latency = 2;
 712 }
 713 def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 714   let Latency = 6;
 715 }
 716
 717 // BT.
 718 // m,i.
 719 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
 720
 721 // BTR BTS BTC.
 722 // r,r,i.
 723 def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> {
 724   let Latency = 2;
 725   let NumMicroOps = 2;
 726 }
 727 def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
 728
 729 // m,r,i.
 730 def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 731   let Latency = 6;
 732   let NumMicroOps = 2;
 733 }
 734 // m,r,i.
 735 def : SchedAlias<WriteBitTestSetImmRMW, Zn2WriteBTRSCm>;
 736 def : SchedAlias<WriteBitTestSetRegRMW, Zn2WriteBTRSCm>;
 737
 738 // BLSI BLSMSK BLSR.
 739 // r,r.
 740 def : SchedAlias<WriteBLS, Zn2WriteALULat2>;
 741 // r,m.
 742 def : SchedAlias<WriteBLSLd, Zn2WriteALULat2Ld>;
 743
 744 // CLD STD.
 745 def : InstRW<[WriteALU], (instrs STD, CLD)>;
 746
 747 // PDEP PEXT.
 748 // r,r,r.
 749 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
 750 // r,r,m.
 751 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
 752
 753 // RCR RCL.
 754 // m,i.
 755 def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>;
 756
 757 // SHR SHL SAR.
 758 // m,i.
 759 def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
 760
 761 // SHRD SHLD.
 762 // m,r
 763 def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>;
 764
 765 // r,r,cl.
 766 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>;
 767
 768 // m,r,cl.
 769 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
 770
 771 //-- Misc instructions --//
 772 // CMPXCHG8B.
 773 def Zn2WriteCMPXCHG8B : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 774   let NumMicroOps = 18;
 775 }
 776 def : InstRW<[Zn2WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
 777
 778 def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>;
 779
 780 // LEAVE
 781 def Zn2WriteLEAVE : SchedWriteRes<[Zn2ALU, Zn2AGU]> {
 782   let Latency = 8;
 783   let NumMicroOps = 2;
 784 }
 785 def : InstRW<[Zn2WriteLEAVE], (instregex "LEAVE")>;
 786
 787 // PAUSE.
 788 def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
 789
 790 // RDTSC.
 791 def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
 792
 793 // RDPMC.
 794 def : InstRW<[WriteMicrocoded], (instrs RDPMC)>;
 795
 796 // RDRAND.
 797 def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>;
 798
 799 // XGETBV.
 800 def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>;
 801
 802 //-- String instructions --//
 803 // CMPS.
 804 def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>;
 805
 806 // LODSB/W.
 807 def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>;
 808
 809 // LODSD/Q.
 810 def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>;
 811
 812 // MOVS.
 813 def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>;
 814
 815 // SCAS.
 816 def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>;
 817
 818 // STOS
 819 def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>;
 820
 821 // XADD.
 822 def Zn2XADD : SchedWriteRes<[Zn2ALU]>;
 823 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;
 824 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
 825
 826 //=== Floating Point x87 Instructions ===//
 827 //-- Move instructions --//
 828
 829 def Zn2WriteFLDr : SchedWriteRes<[Zn2FPU13]> ;
 830
 831 def Zn2WriteSTr: SchedWriteRes<[Zn2FPU23]> {
 832   let Latency = 5;
 833   let NumMicroOps = 2;
 834 }
 835
 836 // LD_F.
 837 // r.
 838 def : InstRW<[Zn2WriteFLDr], (instregex "LD_Frr")>;
 839
 840 // m.
 841 def Zn2WriteLD_F80m : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
 842   let NumMicroOps = 2;
 843 }
 844 def : InstRW<[Zn2WriteLD_F80m], (instregex "LD_F80m")>;
 845
 846 // FBLD.
 847 def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>;
 848
 849 // FST(P).
 850 // r.
 851 def : InstRW<[Zn2WriteSTr], (instregex "ST_(F|FP)rr")>;
 852
 853 // m80.
 854 def Zn2WriteST_FP80m : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
 855   let Latency = 5;
 856 }
 857 def : InstRW<[Zn2WriteST_FP80m], (instregex "ST_FP80m")>;
 858
 859 // FBSTP.
 860 // m80.
 861 def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>;
 862
 863 def Zn2WriteFXCH : SchedWriteRes<[Zn2FPU]>;
 864
 865 // FXCHG.
 866 def : InstRW<[Zn2WriteFXCH], (instrs XCH_F)>;
 867
 868 // FILD.
 869 def Zn2WriteFILD : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
 870   let Latency = 11;
 871   let NumMicroOps = 2;
 872 }
 873 def : InstRW<[Zn2WriteFILD], (instregex "ILD_F(16|32|64)m")>;
 874
 875 // FIST(P) FISTTP.
 876 def Zn2WriteFIST : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
 877   let Latency = 12;
 878 }
 879 def : InstRW<[Zn2WriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>;
 880
 881 def Zn2WriteFPU13 : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
 882   let Latency = 8;
 883 }
 884
 885 def Zn2WriteFPU3 : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
 886   let Latency = 11;
 887 }
 888
 889 // FLDZ.
 890 def : SchedAlias<WriteFLD0, Zn2WriteFPU13>;
 891
 892 // FLD1.
 893 def : SchedAlias<WriteFLD1, Zn2WriteFPU3>;
 894
 895 // FLDPI FLDL2E etc.
 896 def : SchedAlias<WriteFLDC, Zn2WriteFPU3>;
 897
 898 // FNSTSW.
 899 // AX.
 900 def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>;
 901
 902 // m16.
 903 def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>;
 904
 905 // FLDCW.
 906 def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>;
 907
 908 // FNSTCW.
 909 def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>;
 910
 911 // FINCSTP FDECSTP.
 912 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
 913
 914 // FFREE.
 915 def : InstRW<[Zn2WriteFPU3], (instregex "FFREE")>;
 916
 917 // FNSAVE.
 918 def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>;
 919
 920 // FRSTOR.
 921 def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>;
 922
 923 //-- Arithmetic instructions --//
 924
 925 def Zn2WriteFPU3Lat1 : SchedWriteRes<[Zn2FPU3]> ;
 926
 927 def Zn2WriteFPU0Lat1 : SchedWriteRes<[Zn2FPU0]> ;
 928
 929 def Zn2WriteFPU0Lat1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU0]> {
 930   let Latency = 8;
 931 }
 932
 933 // FCHS.
 934 def : InstRW<[Zn2WriteFPU3Lat1], (instregex "CHS_F")>;
 935
 936 // FCOM(P) FUCOM(P).
 937 // r.
 938 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>;
 939 // m.
 940 def : InstRW<[Zn2WriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>;
 941
 942 // FCOMPP FUCOMPP.
 943 // r.
 944 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>;
 945
 946 def Zn2WriteFPU02 : SchedWriteRes<[Zn2AGU, Zn2FPU02]>
 947 {
 948   let Latency = 9;
 949 }
 950
 951 // FCOMI(P) FUCOMI(P).
 952 // m.
 953 def : InstRW<[Zn2WriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 954
 955 def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
 956 {
 957   let Latency = 12;
 958   let NumMicroOps = 2;
 959   let ResourceCycles = [1,3];
 960 }
 961
 962 // FICOM(P).
 963 def : InstRW<[Zn2WriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
 964
 965 // FTST.
 966 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "TST_F")>;
 967
 968 // FXAM.
 969 def : InstRW<[Zn2WriteFPU3Lat1], (instrs FXAM)>;
 970
 971 // FPREM.
 972 def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
 973
 974 // FPREM1.
 975 def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
 976
 977 // FRNDINT.
 978 def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
 979
 980 // FSCALE.
 981 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
 982
 983 // FXTRACT.
 984 def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
 985
 986 // FNOP.
 987 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FNOP)>;
 988
 989 // WAIT.
 990 def : InstRW<[Zn2WriteFPU0Lat1], (instrs WAIT)>;
 991
 992 // FNCLEX.
 993 def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
 994
 995 // FNINIT.
 996 def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
 997
 998 //=== Integer MMX and XMM Instructions ===//
 999
1000 // PACKSSWB/DW.
1001 // mm <- mm.
1002 def Zn2WriteFPU12 : SchedWriteRes<[Zn2FPU12]> ;
1003 def Zn2WriteFPU12Y : SchedWriteRes<[Zn2FPU12]> {
1004   let NumMicroOps = 2;
1005 }
1006 def Zn2WriteFPU12m : SchedWriteRes<[Zn2AGU, Zn2FPU12]> ;
1007 def Zn2WriteFPU12Ym : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1008   let Latency = 8;
1009   let NumMicroOps = 2;
1010 }
1011
1012 def : InstRW<[Zn2WriteFPU12], (instrs MMX_PACKSSDWirr,
1013                                      MMX_PACKSSWBirr,
1014                                      MMX_PACKUSWBirr)>;
1015 def : InstRW<[Zn2WriteFPU12m], (instrs MMX_PACKSSDWirm,
1016                                       MMX_PACKSSWBirm,
1017                                       MMX_PACKUSWBirm)>;
1018
1019 // VPMOVSX/ZX BW BD BQ WD WQ DQ.
1020 // y <- x.
1021 def : InstRW<[Zn2WriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>;
1022 def : InstRW<[Zn2WriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>;
1023
1024 def Zn2WriteFPU013 : SchedWriteRes<[Zn2FPU013]> ;
1025 def Zn2WriteFPU013Y : SchedWriteRes<[Zn2FPU013]> ;
1026 def Zn2WriteFPU013m : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1027   let Latency = 8;
1028   let NumMicroOps = 2;
1029 }
1030 def Zn2WriteFPU013Ld : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1031   let Latency = 8;
1032   let NumMicroOps = 2;
1033 }
1034 def Zn2WriteFPU013LdY : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1035   let Latency = 8;
1036   let NumMicroOps = 2;
1037 }
1038
1039 // PBLENDW.
1040 // x,x,i / v,v,v,i
1041 def : InstRW<[Zn2WriteFPU013], (instregex "(V?)PBLENDWrri")>;
1042 // ymm
1043 def : InstRW<[Zn2WriteFPU013Y], (instrs VPBLENDWYrri)>;
1044
1045 // x,m,i / v,v,m,i
1046 def : InstRW<[Zn2WriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>;
1047 // y,m,i
1048 def : InstRW<[Zn2WriteFPU013LdY], (instrs VPBLENDWYrmi)>;
1049
1050 def Zn2WriteFPU01 : SchedWriteRes<[Zn2FPU01]> ;
1051 def Zn2WriteFPU01Y : SchedWriteRes<[Zn2FPU01]> {
1052   let NumMicroOps = 2;
1053 }
1054
1055 // VPBLENDD.
1056 // v,v,v,i.
1057 def : InstRW<[Zn2WriteFPU01], (instrs VPBLENDDrri)>;
1058 // ymm
1059 def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
1060
1061 // v,v,m,i
1062 def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1063   let NumMicroOps = 2;
1064   let Latency = 8;
1065   let ResourceCycles = [1, 2];
1066 }
1067 def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1068   let NumMicroOps = 2;
1069   let Latency = 9;
1070   let ResourceCycles = [1, 3];
1071 }
1072 def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
1073 def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
1074
1075 // MASKMOVQ.
1076 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
1077
1078 // MASKMOVDQU.
1079 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
1080
1081 // VPMASKMOVD.
1082 // ymm
1083 def : InstRW<[WriteMicrocoded],
1084                                (instregex "VPMASKMOVD(Y?)rm")>;
1085 // m, v,v.
1086 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1087
1088 // VPBROADCAST B/W.
1089 // x, m8/16.
1090 def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1091   let Latency = 8;
1092   let NumMicroOps = 2;
1093   let ResourceCycles = [1, 2];
1094 }
1095 def : InstRW<[Zn2WriteVPBROADCAST128Ld],
1096                                      (instregex "VPBROADCAST(B|W)rm")>;
1097
1098 // y, m8/16
1099 def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1100   let Latency = 8;
1101   let NumMicroOps = 2;
1102   let ResourceCycles = [1, 2];
1103 }
1104 def : InstRW<[Zn2WriteVPBROADCAST256Ld],
1105                                      (instregex "VPBROADCAST(B|W)Yrm")>;
1106
1107 // VPGATHER.
1108 def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
1109
1110 //-- Arithmetic instructions --//
1111
1112 // HADD, HSUB PS/PD
1113 // PHADD|PHSUB (S) W/D.
1114 def : SchedAlias<WritePHAdd,    Zn2WriteMicrocoded>;
1115 def : SchedAlias<WritePHAddLd,  Zn2WriteMicrocoded>;
1116 def : SchedAlias<WritePHAddX,   Zn2WriteMicrocoded>;
1117 def : SchedAlias<WritePHAddXLd, Zn2WriteMicrocoded>;
1118 def : SchedAlias<WritePHAddY,   Zn2WriteMicrocoded>;
1119 def : SchedAlias<WritePHAddYLd, Zn2WriteMicrocoded>;
1120
1121 // PCMPGTQ.
1122 def Zn2WritePCMPGTQr : SchedWriteRes<[Zn2FPU03]>;
1123 def : InstRW<[Zn2WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1124
1125 // x <- x,m.
1126 def Zn2WritePCMPGTQm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1127   let Latency = 8;
1128 }
1129 // ymm.
1130 def Zn2WritePCMPGTQYm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1131   let Latency = 8;
1132 }
1133 def : InstRW<[Zn2WritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
1134 def : InstRW<[Zn2WritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
1135
1136 //-- Logic instructions --//
1137
1138 // PSLL,PSRL,PSRA W/D/Q.
1139 // x,x / v,v,x.
1140 def Zn2WritePShift  : SchedWriteRes<[Zn2FPU2]> ;
1141 def Zn2WritePShiftY : SchedWriteRes<[Zn2FPU2]> ;
1142
1143 // PSLL,PSRL DQ.
1144 def : InstRW<[Zn2WritePShift], (instregex "(V?)PS(R|L)LDQri")>;
1145 def : InstRW<[Zn2WritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>;
1146
1147 //=== Floating Point XMM and YMM Instructions ===//
1148 //-- Move instructions --//
1149
1150 // VPERM2F128.
1151 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
1152 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>;
1153
1154 def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
1155   let NumMicroOps = 2;
1156   let Latency = 8;
1157 }
1158 // VBROADCASTF128.
1159 def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128)>;
1160
1161 // EXTRACTPS.
1162 // r32,x,i.
1163 def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1164   let Latency = 2;
1165   let ResourceCycles = [1, 2];
1166 }
1167 def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1168
1169 def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
1170   let Latency = 5;
1171   let NumMicroOps = 2;
1172   let ResourceCycles = [5, 1, 2];
1173 }
1174 // m32,x,i.
1175 def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1176
1177 // VEXTRACTF128.
1178 // x,y,i.
1179 def : InstRW<[Zn2WriteFPU013], (instrs VEXTRACTF128rr)>;
1180
1181 // m128,y,i.
1182 def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr)>;
1183
1184 def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
1185   let Latency = 2;
1186 //  let ResourceCycles = [2];
1187 }
1188 def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
1189   let Latency = 9;
1190   let NumMicroOps = 2;
1191 }
1192 // VINSERTF128.
1193 // y,y,x,i.
1194 def : InstRW<[Zn2WriteVINSERT128r], (instrs VINSERTF128rr)>;
1195 def : InstRW<[Zn2WriteVINSERT128Ld], (instrs VINSERTF128rm)>;
1196
1197 // VGATHER.
1198 def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>;
1199
1200 //-- Conversion instructions --//
1201 def Zn2WriteCVTPD2PSr: SchedWriteRes<[Zn2FPU3]> {
1202   let Latency = 3;
1203 }
1204 def Zn2WriteCVTPD2PSYr: SchedWriteRes<[Zn2FPU3]> {
1205   let Latency = 3;
1206 }
1207
1208 // CVTPD2PS.
1209 // x,x.
1210 def : SchedAlias<WriteCvtPD2PS,  Zn2WriteCVTPD2PSr>;
1211 // y,y.
1212 def : SchedAlias<WriteCvtPD2PSY, Zn2WriteCVTPD2PSYr>;
1213 // z,z.
1214 defm : X86WriteResUnsupported<WriteCvtPD2PSZ>;
1215
1216 def Zn2WriteCVTPD2PSLd: SchedWriteRes<[Zn2AGU,Zn2FPU03]> {
1217   let Latency = 10;
1218   let NumMicroOps = 2;
1219 }
1220 // x,m128.
1221 def : SchedAlias<WriteCvtPD2PSLd, Zn2WriteCVTPD2PSLd>;
1222
1223 // x,m256.
1224 def Zn2WriteCVTPD2PSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1225   let Latency = 10;
1226 }
1227 def : SchedAlias<WriteCvtPD2PSYLd, Zn2WriteCVTPD2PSYLd>;
1228 // z,m512
1229 defm : X86WriteResUnsupported<WriteCvtPD2PSZLd>;
1230
1231 // CVTSD2SS.
1232 // x,x.
1233 // Same as WriteCVTPD2PSr
1234 def : SchedAlias<WriteCvtSD2SS, Zn2WriteCVTPD2PSr>;
1235
1236 // x,m64.
1237 def : SchedAlias<WriteCvtSD2SSLd, Zn2WriteCVTPD2PSLd>;
1238
1239 // CVTPS2PD.
1240 // x,x.
1241 def Zn2WriteCVTPS2PDr : SchedWriteRes<[Zn2FPU3]> {
1242   let Latency = 3;
1243 }
1244 def : SchedAlias<WriteCvtPS2PD, Zn2WriteCVTPS2PDr>;
1245
1246 // x,m64.
1247 // y,m128.
1248 def Zn2WriteCVTPS2PDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1249   let Latency = 10;
1250   let NumMicroOps = 2;
1251 }
1252 def : SchedAlias<WriteCvtPS2PDLd, Zn2WriteCVTPS2PDLd>;
1253 def : SchedAlias<WriteCvtPS2PDYLd, Zn2WriteCVTPS2PDLd>;
1254 defm : X86WriteResUnsupported<WriteCvtPS2PDZLd>;
1255
1256 // y,x.
1257 def Zn2WriteVCVTPS2PDY : SchedWriteRes<[Zn2FPU3]> {
1258   let Latency = 3;
1259 }
1260 def : SchedAlias<WriteCvtPS2PDY, Zn2WriteVCVTPS2PDY>;
1261 defm : X86WriteResUnsupported<WriteCvtPS2PDZ>;
1262
1263 // CVTSS2SD.
1264 // x,x.
1265 def Zn2WriteCVTSS2SDr : SchedWriteRes<[Zn2FPU3]> {
1266   let Latency = 3;
1267 }
1268 def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
1269
1270 // x,m32.
1271 def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1272   let Latency = 10;
1273   let NumMicroOps = 2;
1274   let ResourceCycles = [1, 2];
1275 }
1276 def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;
1277
1278 def Zn2WriteCVTDQ2PDr: SchedWriteRes<[Zn2FPU12,Zn2FPU3]> {
1279   let Latency = 3;
1280 }
1281 // CVTDQ2PD.
1282 // x,x.
1283 def : InstRW<[Zn2WriteCVTDQ2PDr], (instregex "(V)?CVTDQ2PDrr")>;
1284
1285 // Same as xmm
1286 // y,x.
1287 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>;
1288 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PSYrr)>;
1289
1290 def Zn2WriteCVTPD2DQr: SchedWriteRes<[Zn2FPU12, Zn2FPU3]> {
1291   let Latency = 3;
1292 }
1293 // CVT(T)PD2DQ.
1294 // x,x.
1295 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)PD2DQrr")>;
1296
1297 def Zn2WriteCVTPD2DQLd: SchedWriteRes<[Zn2AGU,Zn2FPU12,Zn2FPU3]> {
1298   let Latency = 10;
1299   let NumMicroOps = 2;
1300 }
1301 // x,m128.
1302 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>;
1303 // same as xmm handling
1304 // x,y.
1305 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
1306 // x,m256.
1307 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
1308
1309 def Zn2WriteCVTPS2PIr: SchedWriteRes<[Zn2FPU3]> {
1310   let Latency = 4;
1311 }
1312 // CVT(T)PS2PI.
1313 // mm,x.
1314 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>;
1315
1316 // CVTPI2PD.
1317 // x,mm.
1318 def : InstRW<[Zn2WriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>;
1319
1320 // CVT(T)PD2PI.
1321 // mm,x.
1322 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>;
1323
1324 def Zn2WriteCVSTSI2SSr: SchedWriteRes<[Zn2FPU3]> {
1325   let Latency = 4;
1326 }
1327
1328 // same as CVTPD2DQr
1329 // CVT(T)SS2SI.
1330 // r32,x.
1331 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>;
1332 // same as CVTPD2DQm
1333 // r32,m32.
1334 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>;
1335
1336 def Zn2WriteCVSTSI2SDr: SchedWriteRes<[Zn2FPU013, Zn2FPU3]> {
1337   let Latency = 4;
1338 }
1339 // CVTSI2SD.
1340 // x,r32/64.
1341 def : InstRW<[Zn2WriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>;
1342
1343
1344 def Zn2WriteCVSTSI2SIr: SchedWriteRes<[Zn2FPU3, Zn2FPU2]> {
1345   let Latency = 4;
1346 }
1347 def Zn2WriteCVSTSI2SILd: SchedWriteRes<[Zn2AGU, Zn2FPU3, Zn2FPU2]> {
1348   let Latency = 11;
1349 }
1350 // CVTSD2SI.
1351 // r32/64
1352 def : InstRW<[Zn2WriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>;
1353 // r32,m32.
1354 def : InstRW<[Zn2WriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>;
1355
1356 // VCVTPS2PH.
1357 // x,v,i.
1358 def : SchedAlias<WriteCvtPS2PH,    Zn2WriteMicrocoded>;
1359 def : SchedAlias<WriteCvtPS2PHY,   Zn2WriteMicrocoded>;
1360 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
1361 // m,v,i.
1362 def : SchedAlias<WriteCvtPS2PHSt,  Zn2WriteMicrocoded>;
1363 def : SchedAlias<WriteCvtPS2PHYSt, Zn2WriteMicrocoded>;
1364 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
1365
1366 // VCVTPH2PS.
1367 // v,x.
1368 def : SchedAlias<WriteCvtPH2PS,    Zn2WriteMicrocoded>;
1369 def : SchedAlias<WriteCvtPH2PSY,   Zn2WriteMicrocoded>;
1370 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
1371 // v,m.
1372 def : SchedAlias<WriteCvtPH2PSLd,  Zn2WriteMicrocoded>;
1373 def : SchedAlias<WriteCvtPH2PSYLd, Zn2WriteMicrocoded>;
1374 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
1375
1376 //-- SSE4A instructions --//
1377 // EXTRQ
1378 def Zn2WriteEXTRQ: SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1379   let Latency = 2;
1380 }
1381 def : InstRW<[Zn2WriteEXTRQ], (instregex "EXTRQ")>;
1382
1383 // INSERTQ
1384 def Zn2WriteINSERTQ: SchedWriteRes<[Zn2FPU03,Zn2FPU1]> {
1385   let Latency = 4;
1386 }
1387 def : InstRW<[Zn2WriteINSERTQ], (instregex "INSERTQ")>;
1388
1389 //-- SHA instructions --//
1390 // SHA256MSG2
1391 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
1392
1393 // SHA1MSG1, SHA256MSG1
1394 // x,x.
1395 def Zn2WriteSHA1MSG1r : SchedWriteRes<[Zn2FPU12]> {
1396   let Latency = 2;
1397 }
1398 def : InstRW<[Zn2WriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
1399 // x,m.
1400 def Zn2WriteSHA1MSG1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1401   let Latency = 9;
1402 }
1403 def : InstRW<[Zn2WriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;
1404
1405 // SHA1MSG2
1406 // x,x.
1407 def Zn2WriteSHA1MSG2r : SchedWriteRes<[Zn2FPU12]> ;
1408 def : InstRW<[Zn2WriteSHA1MSG2r], (instregex "SHA1MSG2rr")>;
1409 // x,m.
1410 def Zn2WriteSHA1MSG2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1411   let Latency = 8;
1412 }
1413 def : InstRW<[Zn2WriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>;
1414
1415 // SHA1NEXTE
1416 // x,x.
1417 def Zn2WriteSHA1NEXTEr : SchedWriteRes<[Zn2FPU1]> ;
1418 def : InstRW<[Zn2WriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>;
1419 // x,m.
1420 def Zn2WriteSHA1NEXTELd : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1421   let Latency = 8;
1422 }
1423 def : InstRW<[Zn2WriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>;
1424
1425 // SHA1RNDS4
1426 // x,x.
1427 def Zn2WriteSHA1RNDS4r : SchedWriteRes<[Zn2FPU1]> {
1428   let Latency = 6;
1429 }
1430 def : InstRW<[Zn2WriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>;
1431 // x,m.
1432 def Zn2WriteSHA1RNDS4Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1433   let Latency = 13;
1434 }
1435 def : InstRW<[Zn2WriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>;
1436
1437 // SHA256RNDS2
1438 // x,x.
1439 def Zn2WriteSHA256RNDS2r : SchedWriteRes<[Zn2FPU1]> {
1440   let Latency = 4;
1441 }
1442 def : InstRW<[Zn2WriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>;
1443 // x,m.
1444 def Zn2WriteSHA256RNDS2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1445   let Latency = 11;
1446 }
1447 def : InstRW<[Zn2WriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>;
1448
1449 //-- Arithmetic instructions --//
1450
1451 // HADD, HSUB PS/PD
1452 def : SchedAlias<WriteFHAdd,    Zn2WriteMicrocoded>;
1453 def : SchedAlias<WriteFHAddLd,  Zn2WriteMicrocoded>;
1454 def : SchedAlias<WriteFHAddY,   Zn2WriteMicrocoded>;
1455 def : SchedAlias<WriteFHAddYLd, Zn2WriteMicrocoded>;
1456
1457 // VDIVPS.
1458 // TODO - convert to Zn2WriteResFpuPair
1459 // y,y,y.
1460 def Zn2WriteVDIVPSYr : SchedWriteRes<[Zn2FPU3]> {
1461   let Latency = 10;
1462   let ResourceCycles = [10];
1463 }
1464 def : SchedAlias<WriteFDivY,   Zn2WriteVDIVPSYr>;
1465
1466 // y,y,m256.
1467 def Zn2WriteVDIVPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1468   let Latency = 17;
1469   let NumMicroOps = 2;
1470   let ResourceCycles = [1, 17];
1471 }
1472 def : SchedAlias<WriteFDivYLd,  Zn2WriteVDIVPSYLd>;
1473
1474 // VDIVPD.
1475 // TODO - convert to Zn2WriteResFpuPair
1476 // y,y,y.
1477 def Zn2WriteVDIVPDY : SchedWriteRes<[Zn2FPU3]> {
1478   let Latency = 13;
1479   let ResourceCycles = [13];
1480 }
1481 def : SchedAlias<WriteFDiv64Y, Zn2WriteVDIVPDY>;
1482
1483 // y,y,m256.
1484 def Zn2WriteVDIVPDYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1485   let Latency = 20;
1486   let NumMicroOps = 2;
1487   let ResourceCycles = [1,20];
1488 }
1489 def : SchedAlias<WriteFDiv64YLd, Zn2WriteVDIVPDYLd>;
1490
1491 // DPPS.
1492 // x,x,i / v,v,v,i.
1493 def : SchedAlias<WriteDPPS,   Zn2WriteMicrocoded>;
1494 def : SchedAlias<WriteDPPSY,  Zn2WriteMicrocoded>;
1495
1496 // x,m,i / v,v,m,i.
1497 def : SchedAlias<WriteDPPSLd, Zn2WriteMicrocoded>;
1498 def : SchedAlias<WriteDPPSYLd,Zn2WriteMicrocoded>;
1499
1500 // DPPD.
1501 // x,x,i.
1502 def : SchedAlias<WriteDPPD,   Zn2WriteMicrocoded>;
1503
1504 // x,m,i.
1505 def : SchedAlias<WriteDPPDLd, Zn2WriteMicrocoded>;
1506
1507 // RSQRTSS
1508 // TODO - convert to Zn2WriteResFpuPair
1509 // x,x.
1510 def Zn2WriteRSQRTSSr : SchedWriteRes<[Zn2FPU02]> {
1511   let Latency = 5;
1512 }
1513 def : SchedAlias<WriteFRsqrt, Zn2WriteRSQRTSSr>;
1514
1515 // x,m128.
1516 def Zn2WriteRSQRTSSLd: SchedWriteRes<[Zn2AGU, Zn2FPU02]> {
1517   let Latency = 12;
1518   let NumMicroOps = 2;
1519   let ResourceCycles = [1,2];
1520 }
1521 def : SchedAlias<WriteFRsqrtLd, Zn2WriteRSQRTSSLd>;
1522
1523 // RSQRTPS
1524 // TODO - convert to Zn2WriteResFpuPair
1525 // y,y.
1526 def Zn2WriteRSQRTPSYr : SchedWriteRes<[Zn2FPU01]> {
1527   let Latency = 5;
1528   let NumMicroOps = 2;
1529   let ResourceCycles = [2];
1530 }
1531 def : SchedAlias<WriteFRsqrtY, Zn2WriteRSQRTPSYr>;
1532
1533 // y,m256.
1534 def Zn2WriteRSQRTPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1535   let Latency = 12;
1536   let NumMicroOps = 2;
1537 }
1538 def : SchedAlias<WriteFRsqrtYLd, Zn2WriteRSQRTPSYLd>;
1539
1540 //-- Other instructions --//
1541
1542 // VZEROUPPER.
1543 def : InstRW<[WriteALU], (instrs VZEROUPPER)>;
1544
1545 // VZEROALL.
1546 def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>;
1547
1548 } // SchedModel