1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/Target/TargetMachine.h"
32 #define GET_SUBTARGETINFO_HEADER
33 #include "X86GenSubtargetInfo.inc"
39 /// The X86 backend supports a number of different styles of PIC.
44 StubPIC, // Used on i386-darwin in pic mode.
45 GOT, // Used on 32 bit elf on when in pic mode.
46 RIPRel, // Used on X86-64 when in pic mode.
47 None // Set when not in pic mode.
50 } // end namespace PICStyles
52 class X86Subtarget final : public X86GenSubtargetInfo {
54 // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
55 // are not a good idea. We should be migrating away from these.
56 enum X86ProcFamilyEnum {
64 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
68 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
71 /// X86 processor family: Intel Atom, and others
72 X86ProcFamilyEnum X86ProcFamily = Others;
74 /// Which PIC style to use
75 PICStyles::Style PICStyle;
77 const TargetMachine &TM;
79 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
80 X86SSEEnum X86SSELevel = NoSSE;
82 /// MMX, 3DNow, 3DNow Athlon, or none supported.
83 X863DNowEnum X863DNowLevel = NoThreeDNow;
85 /// True if the processor supports X87 instructions.
88 /// True if the processor supports CMPXCHG8B.
89 bool HasCmpxchg8b = false;
91 /// True if this processor has NOPL instruction
92 /// (generally pentium pro+).
95 /// True if this processor has conditional move instructions
96 /// (generally pentium pro+).
99 /// True if the processor supports X86-64 instructions.
100 bool HasX86_64 = false;
102 /// True if the processor supports POPCNT.
103 bool HasPOPCNT = false;
105 /// True if the processor supports SSE4A instructions.
106 bool HasSSE4A = false;
108 /// Target has AES instructions
110 bool HasVAES = false;
112 /// Target has FXSAVE/FXRESTOR instructions
113 bool HasFXSR = false;
115 /// Target has XSAVE instructions
116 bool HasXSAVE = false;
118 /// Target has XSAVEOPT instructions
119 bool HasXSAVEOPT = false;
121 /// Target has XSAVEC instructions
122 bool HasXSAVEC = false;
124 /// Target has XSAVES instructions
125 bool HasXSAVES = false;
127 /// Target has carry-less multiplication
128 bool HasPCLMUL = false;
129 bool HasVPCLMULQDQ = false;
131 /// Target has Galois Field Arithmetic instructions
132 bool HasGFNI = false;
134 /// Target has 3-operand fused multiply-add
137 /// Target has 4-operand fused multiply-add
138 bool HasFMA4 = false;
140 /// Target has XOP instructions
143 /// Target has TBM instructions.
146 /// Target has LWP instructions
149 /// True if the processor has the MOVBE instruction.
150 bool HasMOVBE = false;
152 /// True if the processor has the RDRAND instruction.
153 bool HasRDRAND = false;
155 /// Processor has 16-bit floating point conversion instructions.
156 bool HasF16C = false;
158 /// Processor has FS/GS base insturctions.
159 bool HasFSGSBase = false;
161 /// Processor has LZCNT instruction.
162 bool HasLZCNT = false;
164 /// Processor has BMI1 instructions.
167 /// Processor has BMI2 instructions.
168 bool HasBMI2 = false;
170 /// Processor has VBMI instructions.
171 bool HasVBMI = false;
173 /// Processor has VBMI2 instructions.
174 bool HasVBMI2 = false;
176 /// Processor has Integer Fused Multiply Add
177 bool HasIFMA = false;
179 /// Processor has RTM instructions.
182 /// Processor has ADX instructions.
185 /// Processor has SHA instructions.
188 /// Processor has PRFCHW instructions.
189 bool HasPRFCHW = false;
191 /// Processor has RDSEED instructions.
192 bool HasRDSEED = false;
194 /// Processor has LAHF/SAHF instructions.
195 bool HasLAHFSAHF = false;
197 /// Processor has MONITORX/MWAITX instructions.
198 bool HasMWAITX = false;
200 /// Processor has Cache Line Zero instruction
201 bool HasCLZERO = false;
203 /// Processor has Cache Line Demote instruction
204 bool HasCLDEMOTE = false;
206 /// Processor has MOVDIRI instruction (direct store integer).
207 bool HasMOVDIRI = false;
209 /// Processor has MOVDIR64B instruction (direct store 64 bytes).
210 bool HasMOVDIR64B = false;
212 /// Processor has ptwrite instruction.
213 bool HasPTWRITE = false;
215 /// Processor has Prefetch with intent to Write instruction
216 bool HasPREFETCHWT1 = false;
218 /// True if SHLD instructions are slow.
219 bool IsSHLDSlow = false;
221 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
223 bool IsPMULLDSlow = false;
225 /// True if the PMADDWD instruction is slow compared to PMULLD.
226 bool IsPMADDWDSlow = false;
228 /// True if unaligned memory accesses of 16-bytes are slow.
229 bool IsUAMem16Slow = false;
231 /// True if unaligned memory accesses of 32-bytes are slow.
232 bool IsUAMem32Slow = false;
234 /// True if SSE operations can have unaligned memory operands.
235 /// This may require setting a configuration bit in the processor.
236 bool HasSSEUnalignedMem = false;
238 /// True if this processor has the CMPXCHG16B instruction;
239 /// this is true for most x86-64 chips, but not the first AMD chips.
240 bool HasCmpxchg16b = false;
242 /// True if the LEA instruction should be used for adjusting
243 /// the stack pointer. This is an optimization for Intel Atom processors.
244 bool UseLeaForSP = false;
246 /// True if POPCNT instruction has a false dependency on the destination register.
247 bool HasPOPCNTFalseDeps = false;
249 /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
250 bool HasLZCNTFalseDeps = false;
252 /// True if its preferable to combine to a single shuffle using a variable
253 /// mask over multiple fixed shuffles.
254 bool HasFastVariableShuffle = false;
256 /// True if vzeroupper instructions should be inserted after code that uses
257 /// ymm or zmm registers.
258 bool InsertVZEROUPPER = false;
260 /// True if there is no performance penalty for writing NOPs with up to
262 bool HasFast11ByteNOP = false;
264 /// True if there is no performance penalty for writing NOPs with up to
266 bool HasFast15ByteNOP = false;
268 /// True if gather is reasonably fast. This is true for Skylake client and
269 /// all AVX-512 CPUs.
270 bool HasFastGather = false;
272 /// True if hardware SQRTSS instruction is at least as fast (latency) as
273 /// RSQRTSS followed by a Newton-Raphson iteration.
274 bool HasFastScalarFSQRT = false;
276 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
277 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
278 bool HasFastVectorFSQRT = false;
280 /// True if 8-bit divisions are significantly faster than
281 /// 32-bit divisions and should be used when possible.
282 bool HasSlowDivide32 = false;
284 /// True if 32-bit divides are significantly faster than
285 /// 64-bit divisions and should be used when possible.
286 bool HasSlowDivide64 = false;
288 /// True if LZCNT instruction is fast.
289 bool HasFastLZCNT = false;
291 /// True if SHLD based rotate is fast.
292 bool HasFastSHLDRotate = false;
294 /// True if the processor supports macrofusion.
295 bool HasMacroFusion = false;
297 /// True if the processor supports branch fusion.
298 bool HasBranchFusion = false;
300 /// True if the processor has enhanced REP MOVSB/STOSB.
301 bool HasERMSB = false;
303 /// True if the short functions should be padded to prevent
304 /// a stall when returning too early.
305 bool PadShortFunctions = false;
307 /// True if two memory operand instructions should use a temporary register
309 bool SlowTwoMemOps = false;
311 /// True if the LEA instruction inputs have to be ready at address generation
313 bool LEAUsesAG = false;
315 /// True if the LEA instruction with certain arguments is slow
316 bool SlowLEA = false;
318 /// True if the LEA instruction has all three source operands: base, index,
319 /// and offset or if the LEA instruction uses base and index registers where
320 /// the base is EBP, RBP,or R13
321 bool Slow3OpsLEA = false;
323 /// True if INC and DEC instructions are slow when writing to flags
324 bool SlowIncDec = false;
326 /// Processor has AVX-512 PreFetch Instructions
329 /// Processor has AVX-512 Exponential and Reciprocal Instructions
332 /// Processor has AVX-512 Conflict Detection Instructions
335 /// Processor has AVX-512 population count Instructions
336 bool HasVPOPCNTDQ = false;
338 /// Processor has AVX-512 Doubleword and Quadword instructions
341 /// Processor has AVX-512 Byte and Word instructions
344 /// Processor has AVX-512 Vector Length eXtenstions
347 /// Processor has PKU extenstions
350 /// Processor has AVX-512 Vector Neural Network Instructions
351 bool HasVNNI = false;
353 /// Processor has AVX-512 bfloat16 floating-point extensions
354 bool HasBF16 = false;
356 /// Processor supports ENQCMD instructions
357 bool HasENQCMD = false;
359 /// Processor has AVX-512 Bit Algorithms instructions
360 bool HasBITALG = false;
362 /// Processor has AVX-512 vp2intersect instructions
363 bool HasVP2INTERSECT = false;
365 /// Deprecated flag for MPX instructions.
366 bool DeprecatedHasMPX = false;
368 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
369 /// using Shadow Stack
370 bool HasSHSTK = false;
372 /// Processor supports Invalidate Process-Context Identifier
373 bool HasINVPCID = false;
375 /// Processor has Software Guard Extensions
378 /// Processor supports Flush Cache Line instruction
379 bool HasCLFLUSHOPT = false;
381 /// Processor supports Cache Line Write Back instruction
382 bool HasCLWB = false;
384 /// Processor supports Write Back No Invalidate instruction
385 bool HasWBNOINVD = false;
387 /// Processor support RDPID instruction
388 bool HasRDPID = false;
390 /// Processor supports WaitPKG instructions
391 bool HasWAITPKG = false;
393 /// Processor supports PCONFIG instruction
394 bool HasPCONFIG = false;
396 /// Processor has a single uop BEXTR implementation.
397 bool HasFastBEXTR = false;
399 /// Try harder to combine to horizontal vector ops if they are fast.
400 bool HasFastHorizontalOps = false;
402 /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
403 bool HasFastScalarShiftMasks = false;
405 /// Prefer a left/right vector logical shifts pair over a shift+and pair.
406 bool HasFastVectorShiftMasks = false;
408 /// Use a retpoline thunk rather than indirect calls to block speculative
410 bool UseRetpolineIndirectCalls = false;
412 /// Use a retpoline thunk or remove any indirect branch to block speculative
414 bool UseRetpolineIndirectBranches = false;
416 /// Deprecated flag, query `UseRetpolineIndirectCalls` and
417 /// `UseRetpolineIndirectBranches` instead.
418 bool DeprecatedUseRetpoline = false;
420 /// When using a retpoline thunk, call an externally provided thunk rather
421 /// than emitting one inside the compiler.
422 bool UseRetpolineExternalThunk = false;
424 /// Use software floating point for code generation.
425 bool UseSoftFloat = false;
427 /// Use alias analysis during code generation.
430 /// The minimum alignment known to hold of the stack frame on
431 /// entry to the function and which must be maintained by every function.
432 Align stackAlignment = Align(4);
434 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
436 // FIXME: this is a known good value for Yonah. How about others?
437 unsigned MaxInlineSizeThreshold = 128;
439 /// Indicates target prefers 128 bit instructions.
440 bool Prefer128Bit = false;
442 /// Indicates target prefers 256 bit instructions.
443 bool Prefer256Bit = false;
445 /// Indicates target prefers AVX512 mask registers.
446 bool PreferMaskRegisters = false;
448 /// Threeway branch is profitable in this subtarget.
449 bool ThreewayBranchProfitable = false;
451 /// Use Goldmont specific floating point div/sqrt costs.
452 bool UseGLMDivSqrtCosts = false;
454 /// What processor and OS we're targeting.
457 /// GlobalISel related APIs.
458 std::unique_ptr<CallLowering> CallLoweringInfo;
459 std::unique_ptr<LegalizerInfo> Legalizer;
460 std::unique_ptr<RegisterBankInfo> RegBankInfo;
461 std::unique_ptr<InstructionSelector> InstSelector;
464 /// Override the stack alignment.
465 MaybeAlign StackAlignOverride;
467 /// Preferred vector width from function attribute.
468 unsigned PreferVectorWidthOverride;
470 /// Resolved preferred vector width from function attribute and subtarget
472 unsigned PreferVectorWidth = UINT32_MAX;
474 /// Required vector width from function attribute.
475 unsigned RequiredVectorWidth;
477 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
480 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
483 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
486 /// Contains the Overhead of gather\scatter instructions
487 int GatherOverhead = 1024;
488 int ScatterOverhead = 1024;
490 X86SelectionDAGInfo TSInfo;
491 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
492 // X86TargetLowering needs.
493 X86InstrInfo InstrInfo;
494 X86TargetLowering TLInfo;
495 X86FrameLowering FrameLowering;
498 /// This constructor initializes the data members to match that
499 /// of the specified triple.
501 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
502 const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
503 unsigned PreferVectorWidthOverride,
504 unsigned RequiredVectorWidth);
506 const X86TargetLowering *getTargetLowering() const override {
510 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
512 const X86FrameLowering *getFrameLowering() const override {
513 return &FrameLowering;
516 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
520 const X86RegisterInfo *getRegisterInfo() const override {
521 return &getInstrInfo()->getRegisterInfo();
524 /// Returns the minimum alignment known to hold of the
525 /// stack frame on entry to the function and which must be maintained by every
526 /// function for this subtarget.
527 Align getStackAlignment() const { return stackAlignment; }
529 /// Returns the maximum memset / memcpy size
530 /// that still makes it profitable to inline the call.
531 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
533 /// ParseSubtargetFeatures - Parses features string setting specified
534 /// subtarget options. Definition of function is auto generated by tblgen.
535 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
537 /// Methods used by Global ISel
538 const CallLowering *getCallLowering() const override;
539 InstructionSelector *getInstructionSelector() const override;
540 const LegalizerInfo *getLegalizerInfo() const override;
541 const RegisterBankInfo *getRegBankInfo() const override;
544 /// Initialize the full set of dependencies so we can use an initializer
545 /// list for X86Subtarget.
546 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
547 void initSubtargetFeatures(StringRef CPU, StringRef FS);
550 /// Is this x86_64? (disregarding specific ABI / programming model)
551 bool is64Bit() const {
555 bool is32Bit() const {
559 bool is16Bit() const {
563 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
564 bool isTarget64BitILP32() const {
565 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
566 TargetTriple.isOSNaCl());
569 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
570 bool isTarget64BitLP64() const {
571 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
572 !TargetTriple.isOSNaCl());
575 PICStyles::Style getPICStyle() const { return PICStyle; }
576 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
578 bool hasX87() const { return HasX87; }
579 bool hasCmpxchg8b() const { return HasCmpxchg8b; }
580 bool hasNOPL() const { return HasNOPL; }
581 // SSE codegen depends on cmovs, and all SSE1+ processors support them.
582 // All 64-bit processors support cmov.
583 bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
584 bool hasSSE1() const { return X86SSELevel >= SSE1; }
585 bool hasSSE2() const { return X86SSELevel >= SSE2; }
586 bool hasSSE3() const { return X86SSELevel >= SSE3; }
587 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
588 bool hasSSE41() const { return X86SSELevel >= SSE41; }
589 bool hasSSE42() const { return X86SSELevel >= SSE42; }
590 bool hasAVX() const { return X86SSELevel >= AVX; }
591 bool hasAVX2() const { return X86SSELevel >= AVX2; }
592 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
593 bool hasInt256() const { return hasAVX2(); }
594 bool hasSSE4A() const { return HasSSE4A; }
595 bool hasMMX() const { return X863DNowLevel >= MMX; }
596 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
597 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
598 bool hasPOPCNT() const { return HasPOPCNT; }
599 bool hasAES() const { return HasAES; }
600 bool hasVAES() const { return HasVAES; }
601 bool hasFXSR() const { return HasFXSR; }
602 bool hasXSAVE() const { return HasXSAVE; }
603 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
604 bool hasXSAVEC() const { return HasXSAVEC; }
605 bool hasXSAVES() const { return HasXSAVES; }
606 bool hasPCLMUL() const { return HasPCLMUL; }
607 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
608 bool hasGFNI() const { return HasGFNI; }
609 // Prefer FMA4 to FMA - its better for commutation/memory folding and
610 // has equal or better performance on all supported targets.
611 bool hasFMA() const { return HasFMA; }
612 bool hasFMA4() const { return HasFMA4; }
613 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
614 bool hasXOP() const { return HasXOP; }
615 bool hasTBM() const { return HasTBM; }
616 bool hasLWP() const { return HasLWP; }
617 bool hasMOVBE() const { return HasMOVBE; }
618 bool hasRDRAND() const { return HasRDRAND; }
619 bool hasF16C() const { return HasF16C; }
620 bool hasFSGSBase() const { return HasFSGSBase; }
621 bool hasLZCNT() const { return HasLZCNT; }
622 bool hasBMI() const { return HasBMI; }
623 bool hasBMI2() const { return HasBMI2; }
624 bool hasVBMI() const { return HasVBMI; }
625 bool hasVBMI2() const { return HasVBMI2; }
626 bool hasIFMA() const { return HasIFMA; }
627 bool hasRTM() const { return HasRTM; }
628 bool hasADX() const { return HasADX; }
629 bool hasSHA() const { return HasSHA; }
630 bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
631 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
632 bool hasSSEPrefetch() const {
633 // We implicitly enable these when we have a write prefix supporting cache
634 // level OR if we have prfchw, but don't already have a read prefetch from
636 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
638 bool hasRDSEED() const { return HasRDSEED; }
639 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
640 bool hasMWAITX() const { return HasMWAITX; }
641 bool hasCLZERO() const { return HasCLZERO; }
642 bool hasCLDEMOTE() const { return HasCLDEMOTE; }
643 bool hasMOVDIRI() const { return HasMOVDIRI; }
644 bool hasMOVDIR64B() const { return HasMOVDIR64B; }
645 bool hasPTWRITE() const { return HasPTWRITE; }
646 bool isSHLDSlow() const { return IsSHLDSlow; }
647 bool isPMULLDSlow() const { return IsPMULLDSlow; }
648 bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
649 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
650 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
651 int getGatherOverhead() const { return GatherOverhead; }
652 int getScatterOverhead() const { return ScatterOverhead; }
653 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
654 bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
655 bool useLeaForSP() const { return UseLeaForSP; }
656 bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
657 bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
658 bool hasFastVariableShuffle() const {
659 return HasFastVariableShuffle;
661 bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
662 bool hasFastGather() const { return HasFastGather; }
663 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
664 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
665 bool hasFastLZCNT() const { return HasFastLZCNT; }
666 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
667 bool hasFastBEXTR() const { return HasFastBEXTR; }
668 bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
669 bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
670 bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
671 bool hasMacroFusion() const { return HasMacroFusion; }
672 bool hasBranchFusion() const { return HasBranchFusion; }
673 bool hasERMSB() const { return HasERMSB; }
674 bool hasSlowDivide32() const { return HasSlowDivide32; }
675 bool hasSlowDivide64() const { return HasSlowDivide64; }
676 bool padShortFunctions() const { return PadShortFunctions; }
677 bool slowTwoMemOps() const { return SlowTwoMemOps; }
678 bool LEAusesAG() const { return LEAUsesAG; }
679 bool slowLEA() const { return SlowLEA; }
680 bool slow3OpsLEA() const { return Slow3OpsLEA; }
681 bool slowIncDec() const { return SlowIncDec; }
682 bool hasCDI() const { return HasCDI; }
683 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
684 bool hasPFI() const { return HasPFI; }
685 bool hasERI() const { return HasERI; }
686 bool hasDQI() const { return HasDQI; }
687 bool hasBWI() const { return HasBWI; }
688 bool hasVLX() const { return HasVLX; }
689 bool hasPKU() const { return HasPKU; }
690 bool hasVNNI() const { return HasVNNI; }
691 bool hasBF16() const { return HasBF16; }
692 bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
693 bool hasBITALG() const { return HasBITALG; }
694 bool hasSHSTK() const { return HasSHSTK; }
695 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
696 bool hasCLWB() const { return HasCLWB; }
697 bool hasWBNOINVD() const { return HasWBNOINVD; }
698 bool hasRDPID() const { return HasRDPID; }
699 bool hasWAITPKG() const { return HasWAITPKG; }
700 bool hasPCONFIG() const { return HasPCONFIG; }
701 bool hasSGX() const { return HasSGX; }
702 bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
703 bool hasINVPCID() const { return HasINVPCID; }
704 bool hasENQCMD() const { return HasENQCMD; }
705 bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
706 bool useRetpolineIndirectBranches() const {
707 return UseRetpolineIndirectBranches;
709 bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
710 bool preferMaskRegisters() const { return PreferMaskRegisters; }
711 bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
713 unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
714 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
716 // Helper functions to determine when we should allow widening to 512-bit
718 // TODO: Currently we're always allowing widening on CPUs without VLX,
719 // because for many cases we don't have a better option.
720 bool canExtendTo512DQ() const {
721 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
723 bool canExtendTo512BW() const {
724 return hasBWI() && canExtendTo512DQ();
727 // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
728 // disable them in the legalizer.
729 bool useAVX512Regs() const {
730 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
733 bool useBWIRegs() const {
734 return hasBWI() && useAVX512Regs();
737 bool isXRaySupported() const override { return is64Bit(); }
739 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
741 /// TODO: to be removed later and replaced with suitable properties
742 bool isAtom() const { return X86ProcFamily == IntelAtom; }
743 bool isSLM() const { return X86ProcFamily == IntelSLM; }
744 bool useSoftFloat() const { return UseSoftFloat; }
745 bool useAA() const override { return UseAA; }
747 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
748 /// no-sse2). There isn't any reason to disable it if the target processor
750 bool hasMFence() const { return hasSSE2() || is64Bit(); }
752 const Triple &getTargetTriple() const { return TargetTriple; }
754 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
755 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
756 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
757 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
758 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
760 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
761 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
762 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
764 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
765 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
766 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
767 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
768 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
769 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
770 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
771 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
772 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
774 bool isTargetWindowsMSVC() const {
775 return TargetTriple.isWindowsMSVCEnvironment();
778 bool isTargetWindowsCoreCLR() const {
779 return TargetTriple.isWindowsCoreCLREnvironment();
782 bool isTargetWindowsCygwin() const {
783 return TargetTriple.isWindowsCygwinEnvironment();
786 bool isTargetWindowsGNU() const {
787 return TargetTriple.isWindowsGNUEnvironment();
790 bool isTargetWindowsItanium() const {
791 return TargetTriple.isWindowsItaniumEnvironment();
794 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
796 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
798 bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
800 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
802 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
803 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
805 bool isPICStyleStubPIC() const {
806 return PICStyle == PICStyles::Style::StubPIC;
809 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
811 bool isCallingConvWin64(CallingConv::ID CC) const {
813 // On Win64, all these conventions just use the default convention.
815 case CallingConv::Fast:
816 case CallingConv::Tail:
817 case CallingConv::Swift:
818 case CallingConv::X86_FastCall:
819 case CallingConv::X86_StdCall:
820 case CallingConv::X86_ThisCall:
821 case CallingConv::X86_VectorCall:
822 case CallingConv::Intel_OCL_BI:
823 return isTargetWin64();
824 // This convention allows using the Win64 convention on other targets.
825 case CallingConv::Win64:
827 // This convention allows using the SysV convention on Windows targets.
828 case CallingConv::X86_64_SysV:
830 // Otherwise, who knows what this is.
836 /// Classify a global variable reference for the current subtarget according
837 /// to how we should reference it in a non-pcrel context.
838 unsigned char classifyLocalReference(const GlobalValue *GV) const;
840 unsigned char classifyGlobalReference(const GlobalValue *GV,
841 const Module &M) const;
842 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
844 /// Classify a global function reference for the current subtarget.
845 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
846 const Module &M) const;
847 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
849 /// Classify a blockaddress reference for the current subtarget according to
850 /// how we should reference it in a non-pcrel context.
851 unsigned char classifyBlockAddressReference() const;
853 /// Return true if the subtarget allows calls to immediate address.
854 bool isLegalToCallImmediateAddr() const;
856 /// If we are using retpolines, we need to expand indirectbr to avoid it
857 /// lowering to an actual indirect jump.
858 bool enableIndirectBrExpand() const override {
859 return useRetpolineIndirectBranches();
862 /// Enable the MachineScheduler pass for all X86 subtargets.
863 bool enableMachineScheduler() const override { return true; }
865 bool enableEarlyIfConversion() const override;
867 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
868 &Mutations) const override;
870 AntiDepBreakMode getAntiDepBreakMode() const override {
871 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
874 bool enableAdvancedRASplitCost() const override { return true; }
877 } // end namespace llvm
879 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H