1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file is part of the XCore Disassembler.
12 //===----------------------------------------------------------------------===//
14 #include "TargetInfo/XCoreTargetInfo.h"
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/TargetRegistry.h"
26 #define DEBUG_TYPE "xcore-disassembler"
28 typedef MCDisassembler::DecodeStatus DecodeStatus;
32 /// A disassembler class for XCore.
33 class XCoreDisassembler : public MCDisassembler {
35 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
36 MCDisassembler(STI, Ctx) {}
38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
40 raw_ostream &CStream) const override;
44 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
45 uint64_t &Size, uint16_t &Insn) {
46 // We want to read exactly 2 Bytes of data.
47 if (Bytes.size() < 2) {
51 // Encoded as a little-endian 16-bit word in the stream.
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
56 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
57 uint64_t &Size, uint32_t &Insn) {
58 // We want to read exactly 4 Bytes of data.
59 if (Bytes.size() < 4) {
63 // Encoded as a little-endian 32-bit word in the stream.
65 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
69 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
70 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
71 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
72 return *(RegInfo->getRegClass(RC).begin() + RegNo);
75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
86 uint64_t Address, const void *Decoder);
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
89 uint64_t Address, const void *Decoder);
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
104 const void *Decoder);
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
109 const void *Decoder);
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
114 const void *Decoder);
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
119 const void *Decoder);
121 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
124 const void *Decoder);
126 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
129 const void *Decoder);
131 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
134 const void *Decoder);
136 static DecodeStatus Decode3RInstruction(MCInst &Inst,
139 const void *Decoder);
141 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
144 const void *Decoder);
146 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
149 const void *Decoder);
151 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
154 const void *Decoder);
156 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
194 const void *Decoder);
196 #include "XCoreGenDisassemblerTables.inc"
198 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
204 return MCDisassembler::Fail;
205 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
206 Inst.addOperand(MCOperand::createReg(Reg));
207 return MCDisassembler::Success;
210 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
216 return MCDisassembler::Fail;
217 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
218 Inst.addOperand(MCOperand::createReg(Reg));
219 return MCDisassembler::Success;
222 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
223 uint64_t Address, const void *Decoder) {
225 return MCDisassembler::Fail;
226 static const unsigned Values[] = {
227 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
229 Inst.addOperand(MCOperand::createImm(Values[Val]));
230 return MCDisassembler::Success;
233 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder) {
235 Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
236 return MCDisassembler::Success;
240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
241 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
243 return MCDisassembler::Fail;
244 if (fieldFromInstruction(Insn, 5, 1)) {
246 return MCDisassembler::Fail;
250 unsigned Op1High = Combined % 3;
251 unsigned Op2High = Combined / 3;
252 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
254 return MCDisassembler::Success;
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
260 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
262 return MCDisassembler::Fail;
264 unsigned Op1High = Combined % 3;
265 unsigned Op2High = (Combined / 3) % 3;
266 unsigned Op3High = Combined / 9;
267 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
269 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
270 return MCDisassembler::Success;
274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
275 const void *Decoder) {
276 // Try and decode as a 3R instruction.
277 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
280 Inst.setOpcode(XCore::STW_2rus);
281 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
283 Inst.setOpcode(XCore::LDW_2rus);
284 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
286 Inst.setOpcode(XCore::ADD_3r);
287 return Decode3RInstruction(Inst, Insn, Address, Decoder);
289 Inst.setOpcode(XCore::SUB_3r);
290 return Decode3RInstruction(Inst, Insn, Address, Decoder);
292 Inst.setOpcode(XCore::SHL_3r);
293 return Decode3RInstruction(Inst, Insn, Address, Decoder);
295 Inst.setOpcode(XCore::SHR_3r);
296 return Decode3RInstruction(Inst, Insn, Address, Decoder);
298 Inst.setOpcode(XCore::EQ_3r);
299 return Decode3RInstruction(Inst, Insn, Address, Decoder);
301 Inst.setOpcode(XCore::AND_3r);
302 return Decode3RInstruction(Inst, Insn, Address, Decoder);
304 Inst.setOpcode(XCore::OR_3r);
305 return Decode3RInstruction(Inst, Insn, Address, Decoder);
307 Inst.setOpcode(XCore::LDW_3r);
308 return Decode3RInstruction(Inst, Insn, Address, Decoder);
310 Inst.setOpcode(XCore::LD16S_3r);
311 return Decode3RInstruction(Inst, Insn, Address, Decoder);
313 Inst.setOpcode(XCore::LD8U_3r);
314 return Decode3RInstruction(Inst, Insn, Address, Decoder);
316 Inst.setOpcode(XCore::ADD_2rus);
317 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
319 Inst.setOpcode(XCore::SUB_2rus);
320 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
322 Inst.setOpcode(XCore::SHL_2rus);
323 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
325 Inst.setOpcode(XCore::SHR_2rus);
326 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
328 Inst.setOpcode(XCore::EQ_2rus);
329 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
331 Inst.setOpcode(XCore::TSETR_3r);
332 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
334 Inst.setOpcode(XCore::LSS_3r);
335 return Decode3RInstruction(Inst, Insn, Address, Decoder);
337 Inst.setOpcode(XCore::LSU_3r);
338 return Decode3RInstruction(Inst, Insn, Address, Decoder);
340 return MCDisassembler::Fail;
344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
345 const void *Decoder) {
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
348 if (S != MCDisassembler::Success)
349 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
351 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
358 const void *Decoder) {
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
361 if (S != MCDisassembler::Success)
362 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
364 Inst.addOperand(MCOperand::createImm(Op1));
365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
371 const void *Decoder) {
373 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
374 if (S != MCDisassembler::Success)
375 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
377 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
378 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
384 const void *Decoder) {
386 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
387 if (S != MCDisassembler::Success)
388 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
390 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
391 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
392 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
398 const void *Decoder) {
400 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
401 if (S != MCDisassembler::Success)
402 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
404 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
405 Inst.addOperand(MCOperand::createImm(Op2));
410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
411 const void *Decoder) {
413 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
414 if (S != MCDisassembler::Success)
415 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
417 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
418 DecodeBitpOperand(Inst, Op2, Address, Decoder);
423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
424 const void *Decoder) {
426 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
427 if (S != MCDisassembler::Success)
428 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
430 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
431 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
432 DecodeBitpOperand(Inst, Op2, Address, Decoder);
437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
438 const void *Decoder) {
439 // Try and decode as a L3R / L2RUS instruction.
440 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
441 fieldFromInstruction(Insn, 27, 5) << 4;
444 Inst.setOpcode(XCore::STW_l3r);
445 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
447 Inst.setOpcode(XCore::XOR_l3r);
448 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
450 Inst.setOpcode(XCore::ASHR_l3r);
451 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
453 Inst.setOpcode(XCore::LDAWF_l3r);
454 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
456 Inst.setOpcode(XCore::LDAWB_l3r);
457 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
459 Inst.setOpcode(XCore::LDA16F_l3r);
460 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
462 Inst.setOpcode(XCore::LDA16B_l3r);
463 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
465 Inst.setOpcode(XCore::MUL_l3r);
466 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
468 Inst.setOpcode(XCore::DIVS_l3r);
469 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
471 Inst.setOpcode(XCore::DIVU_l3r);
472 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
474 Inst.setOpcode(XCore::ST16_l3r);
475 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
477 Inst.setOpcode(XCore::ST8_l3r);
478 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
480 Inst.setOpcode(XCore::ASHR_l2rus);
481 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
483 Inst.setOpcode(XCore::OUTPW_l2rus);
484 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
486 Inst.setOpcode(XCore::INPW_l2rus);
487 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
489 Inst.setOpcode(XCore::LDAWF_l2rus);
490 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
492 Inst.setOpcode(XCore::LDAWB_l2rus);
493 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
495 Inst.setOpcode(XCore::CRC_l3r);
496 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
498 Inst.setOpcode(XCore::REMS_l3r);
499 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
501 Inst.setOpcode(XCore::REMU_l3r);
502 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
504 return MCDisassembler::Fail;
508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
509 const void *Decoder) {
511 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
513 if (S != MCDisassembler::Success)
514 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
516 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
517 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
523 const void *Decoder) {
525 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
527 if (S != MCDisassembler::Success)
528 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
530 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
531 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
537 const void *Decoder) {
538 unsigned Op1, Op2, Op3;
539 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
540 if (S == MCDisassembler::Success) {
541 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
542 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
543 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
550 const void *Decoder) {
551 unsigned Op1, Op2, Op3;
552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
553 if (S == MCDisassembler::Success) {
554 Inst.addOperand(MCOperand::createImm(Op1));
555 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
563 const void *Decoder) {
564 unsigned Op1, Op2, Op3;
565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
566 if (S == MCDisassembler::Success) {
567 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
568 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
569 Inst.addOperand(MCOperand::createImm(Op3));
575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
576 const void *Decoder) {
577 unsigned Op1, Op2, Op3;
578 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
579 if (S == MCDisassembler::Success) {
580 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
581 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
582 DecodeBitpOperand(Inst, Op3, Address, Decoder);
588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
589 const void *Decoder) {
590 unsigned Op1, Op2, Op3;
592 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
593 if (S == MCDisassembler::Success) {
594 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
595 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
596 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
603 const void *Decoder) {
604 unsigned Op1, Op2, Op3;
606 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
607 if (S == MCDisassembler::Success) {
608 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
609 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
610 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
611 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
618 const void *Decoder) {
619 unsigned Op1, Op2, Op3;
621 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
622 if (S == MCDisassembler::Success) {
623 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
624 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
625 Inst.addOperand(MCOperand::createImm(Op3));
631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
632 const void *Decoder) {
633 unsigned Op1, Op2, Op3;
635 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
636 if (S == MCDisassembler::Success) {
637 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
638 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
639 DecodeBitpOperand(Inst, Op3, Address, Decoder);
645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
646 const void *Decoder) {
647 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
649 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
650 if (S != MCDisassembler::Success)
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
653 if (S != MCDisassembler::Success)
655 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
657 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
658 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
659 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
660 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
666 const void *Decoder) {
667 // Try and decode as a L6R instruction.
669 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
672 Inst.setOpcode(XCore::LMUL_l6r);
673 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
675 return MCDisassembler::Fail;
679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
680 const void *Decoder) {
681 unsigned Op1, Op2, Op3, Op4, Op5;
683 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
684 if (S != MCDisassembler::Success)
685 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
687 if (S != MCDisassembler::Success)
688 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
690 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
692 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
693 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
694 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
700 const void *Decoder) {
701 unsigned Op1, Op2, Op3;
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
704 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
705 if (S == MCDisassembler::Success) {
706 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
709 if (S == MCDisassembler::Success) {
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
711 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
712 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
719 const void *Decoder) {
720 unsigned Op1, Op2, Op3;
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
723 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
724 if (S == MCDisassembler::Success) {
725 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
726 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
728 if (S == MCDisassembler::Success) {
729 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
730 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
731 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
732 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
737 MCDisassembler::DecodeStatus
738 XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,
739 ArrayRef<uint8_t> Bytes, uint64_t Address,
740 raw_ostream &cStream) const {
743 if (!readInstruction16(Bytes, Address, Size, insn16)) {
747 // Calling the auto-generated decoder function.
748 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
750 if (Result != Fail) {
757 if (!readInstruction32(Bytes, Address, Size, insn32)) {
761 // Calling the auto-generated decoder function.
762 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
763 if (Result != Fail) {
771 static MCDisassembler *createXCoreDisassembler(const Target &T,
772 const MCSubtargetInfo &STI,
774 return new XCoreDisassembler(STI, Ctx);
777 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreDisassembler() {
778 // Register the disassembler.
779 TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),
780 createXCoreDisassembler);