1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the XCoreTargetLowering class.
11 //===----------------------------------------------------------------------===//
13 #include "XCoreISelLowering.h"
15 #include "XCoreMachineFunctionInfo.h"
16 #include "XCoreSubtarget.h"
17 #include "XCoreTargetMachine.h"
18 #include "XCoreTargetObjectFile.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/KnownBits.h"
37 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "xcore-lower"
44 const char *XCoreTargetLowering::
45 getTargetNodeName(unsigned Opcode) const
47 switch ((XCoreISD::NodeType)Opcode)
49 case XCoreISD::FIRST_NUMBER : break;
50 case XCoreISD::BL : return "XCoreISD::BL";
51 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
52 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
53 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
54 case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
55 case XCoreISD::STWSP : return "XCoreISD::STWSP";
56 case XCoreISD::RETSP : return "XCoreISD::RETSP";
57 case XCoreISD::LADD : return "XCoreISD::LADD";
58 case XCoreISD::LSUB : return "XCoreISD::LSUB";
59 case XCoreISD::LMUL : return "XCoreISD::LMUL";
60 case XCoreISD::MACCU : return "XCoreISD::MACCU";
61 case XCoreISD::MACCS : return "XCoreISD::MACCS";
62 case XCoreISD::CRC8 : return "XCoreISD::CRC8";
63 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
64 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
65 case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
66 case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
67 case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
72 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
73 const XCoreSubtarget &Subtarget)
74 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
79 // Compute derived properties from the register classes
80 computeRegisterProperties(Subtarget.getRegisterInfo());
82 setStackPointerRegisterToSaveRestore(XCore::SP);
84 setSchedulingPreference(Sched::Source);
86 // Use i32 for setcc operations results (slt, sgt, ...).
87 setBooleanContents(ZeroOrOneBooleanContent);
88 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
90 // XCore does not have the NodeTypes below.
91 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
95 setOperationAction(ISD::ADD, MVT::i64, Custom);
96 setOperationAction(ISD::SUB, MVT::i64, Custom);
97 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
98 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
99 setOperationAction(ISD::MULHS, MVT::i32, Expand);
100 setOperationAction(ISD::MULHU, MVT::i32, Expand);
101 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
102 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
103 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
106 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
107 setOperationAction(ISD::ROTL , MVT::i32, Expand);
108 setOperationAction(ISD::ROTR , MVT::i32, Expand);
110 setOperationAction(ISD::TRAP, MVT::Other, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
115 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
116 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
118 // Conversion of i64 -> double produces constantpool nodes
119 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
122 for (MVT VT : MVT::integer_valuetypes()) {
123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
131 // Custom expand misaligned loads / stores.
132 setOperationAction(ISD::LOAD, MVT::i32, Custom);
133 setOperationAction(ISD::STORE, MVT::i32, Custom);
136 setOperationAction(ISD::VAEND, MVT::Other, Expand);
137 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
138 setOperationAction(ISD::VAARG, MVT::Other, Custom);
139 setOperationAction(ISD::VASTART, MVT::Other, Custom);
142 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
143 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
144 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
146 // Exception handling
147 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
148 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
151 // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic.
152 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
153 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
154 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
155 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
157 // TRAMPOLINE is custom lowered.
158 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
159 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
161 // We want to custom lower some of our intrinsics.
162 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
164 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4;
165 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
166 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
168 // We have target-specific dag combine patterns for the following nodes:
169 setTargetDAGCombine(ISD::STORE);
170 setTargetDAGCombine(ISD::ADD);
171 setTargetDAGCombine(ISD::INTRINSIC_VOID);
172 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
174 setMinFunctionAlignment(1);
175 setPrefFunctionAlignment(2);
178 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
179 if (Val.getOpcode() != ISD::LOAD)
182 EVT VT1 = Val.getValueType();
183 if (!VT1.isSimple() || !VT1.isInteger() ||
184 !VT2.isSimple() || !VT2.isInteger())
187 switch (VT1.getSimpleVT().SimpleTy) {
196 SDValue XCoreTargetLowering::
197 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
198 switch (Op.getOpcode())
200 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
201 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
202 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
203 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
204 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
205 case ISD::LOAD: return LowerLOAD(Op, DAG);
206 case ISD::STORE: return LowerSTORE(Op, DAG);
207 case ISD::VAARG: return LowerVAARG(Op, DAG);
208 case ISD::VASTART: return LowerVASTART(Op, DAG);
209 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
210 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
211 // FIXME: Remove these when LegalizeDAGTypes lands.
213 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
214 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
215 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
216 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
217 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
218 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
219 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
220 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
221 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
222 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
224 llvm_unreachable("unimplemented operand");
228 /// ReplaceNodeResults - Replace the results of node with an illegal result
229 /// type with new values built out of custom code.
230 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
231 SmallVectorImpl<SDValue>&Results,
232 SelectionDAG &DAG) const {
233 switch (N->getOpcode()) {
235 llvm_unreachable("Don't know how to custom expand this!");
238 Results.push_back(ExpandADDSUB(N, DAG));
243 //===----------------------------------------------------------------------===//
244 // Misc Lower Operation implementation
245 //===----------------------------------------------------------------------===//
247 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
248 const GlobalValue *GV,
249 SelectionDAG &DAG) const {
250 // FIXME there is no actual debug info here
253 if (GV->getValueType()->isFunctionTy())
254 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
256 const auto *GVar = dyn_cast<GlobalVariable>(GV);
257 if ((GV->hasSection() && GV->getSection().startswith(".cp.")) ||
258 (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
259 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
261 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
264 static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) {
265 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small)
268 Type *ObjType = GV->getValueType();
269 if (!ObjType->isSized())
272 auto &DL = GV->getParent()->getDataLayout();
273 unsigned ObjSize = DL.getTypeAllocSize(ObjType);
274 return ObjSize < CodeModelLargeSize && ObjSize != 0;
277 SDValue XCoreTargetLowering::
278 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
280 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
281 const GlobalValue *GV = GN->getGlobal();
283 int64_t Offset = GN->getOffset();
284 if (IsSmallObject(GV, *this)) {
285 // We can only fold positive offsets that are a multiple of the word size.
286 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0);
287 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
288 GA = getGlobalAddressWrapper(GA, GV, DAG);
289 // Handle the rest of the offset.
290 if (Offset != FoldedOffset) {
291 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32);
292 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
296 // Ideally we would not fold in offset with an index <= 11.
297 Type *Ty = Type::getInt8PtrTy(*DAG.getContext());
298 Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
299 Ty = Type::getInt32Ty(*DAG.getContext());
300 Constant *Idx = ConstantInt::get(Ty, Offset);
301 Constant *GAI = ConstantExpr::getGetElementPtr(
302 Type::getInt8Ty(*DAG.getContext()), GA, Idx);
303 SDValue CP = DAG.getConstantPool(GAI, MVT::i32);
304 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL,
305 DAG.getEntryNode(), CP, MachinePointerInfo());
309 SDValue XCoreTargetLowering::
310 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
313 auto PtrVT = getPointerTy(DAG.getDataLayout());
314 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
315 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
317 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result);
320 SDValue XCoreTargetLowering::
321 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
323 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
324 // FIXME there isn't really debug info here
326 EVT PtrVT = Op.getValueType();
328 if (CP->isMachineConstantPoolEntry()) {
329 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
330 CP->getAlignment(), CP->getOffset());
332 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
333 CP->getAlignment(), CP->getOffset());
335 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
338 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
339 return MachineJumpTableInfo::EK_Inline;
342 SDValue XCoreTargetLowering::
343 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
345 SDValue Chain = Op.getOperand(0);
346 SDValue Table = Op.getOperand(1);
347 SDValue Index = Op.getOperand(2);
349 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
350 unsigned JTI = JT->getIndex();
351 MachineFunction &MF = DAG.getMachineFunction();
352 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
353 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
355 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
356 if (NumEntries <= 32) {
357 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
359 assert((NumEntries >> 31) == 0);
360 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
361 DAG.getConstant(1, dl, MVT::i32));
362 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
366 SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(
367 const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset,
368 SelectionDAG &DAG) const {
369 auto PtrVT = getPointerTy(DAG.getDataLayout());
370 if ((Offset & 0x3) == 0) {
371 return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo());
373 // Lower to pair of consecutive word aligned loads plus some bit shifting.
374 int32_t HighOffset = alignTo(Offset, 4);
375 int32_t LowOffset = HighOffset - 4;
376 SDValue LowAddr, HighAddr;
377 if (GlobalAddressSDNode *GASD =
378 dyn_cast<GlobalAddressSDNode>(Base.getNode())) {
379 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
381 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
384 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
385 DAG.getConstant(LowOffset, DL, MVT::i32));
386 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
387 DAG.getConstant(HighOffset, DL, MVT::i32));
389 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32);
390 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32);
392 SDValue Low = DAG.getLoad(PtrVT, DL, Chain, LowAddr, MachinePointerInfo());
393 SDValue High = DAG.getLoad(PtrVT, DL, Chain, HighAddr, MachinePointerInfo());
394 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
395 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
396 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
397 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
399 SDValue Ops[] = { Result, Chain };
400 return DAG.getMergeValues(Ops, DL);
403 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
405 KnownBits Known = DAG.computeKnownBits(Value);
406 return Known.countMinTrailingZeros() >= 2;
409 SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 LLVMContext &Context = *DAG.getContext();
412 LoadSDNode *LD = cast<LoadSDNode>(Op);
413 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
414 "Unexpected extension type");
415 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
417 if (allowsMemoryAccess(Context, DAG.getDataLayout(), LD->getMemoryVT(),
418 *LD->getMemOperand()))
421 SDValue Chain = LD->getChain();
422 SDValue BasePtr = LD->getBasePtr();
425 if (!LD->isVolatile()) {
426 const GlobalValue *GV;
428 if (DAG.isBaseWithConstantOffset(BasePtr) &&
429 isWordAligned(BasePtr->getOperand(0), DAG)) {
430 SDValue NewBasePtr = BasePtr->getOperand(0);
431 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
432 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
435 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
436 MinAlign(GV->getAlignment(), 4) == 4) {
437 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
438 BasePtr->getValueType(0));
439 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
444 if (LD->getAlignment() == 2) {
446 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
447 LD->getPointerInfo(), MVT::i16,
448 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
449 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
450 DAG.getConstant(2, DL, MVT::i32));
452 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
453 LD->getPointerInfo().getWithOffset(2), MVT::i16,
454 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
455 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
456 DAG.getConstant(16, DL, MVT::i32));
457 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
458 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
460 SDValue Ops[] = { Result, Chain };
461 return DAG.getMergeValues(Ops, DL);
464 // Lower to a call to __misaligned_load(BasePtr).
465 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(Context);
466 TargetLowering::ArgListTy Args;
467 TargetLowering::ArgListEntry Entry;
470 Entry.Node = BasePtr;
471 Args.push_back(Entry);
473 TargetLowering::CallLoweringInfo CLI(DAG);
474 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
475 CallingConv::C, IntPtrTy,
476 DAG.getExternalSymbol("__misaligned_load",
477 getPointerTy(DAG.getDataLayout())),
480 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
481 SDValue Ops[] = { CallResult.first, CallResult.second };
482 return DAG.getMergeValues(Ops, DL);
485 SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
486 LLVMContext &Context = *DAG.getContext();
487 StoreSDNode *ST = cast<StoreSDNode>(Op);
488 assert(!ST->isTruncatingStore() && "Unexpected store type");
489 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
491 if (allowsMemoryAccess(Context, DAG.getDataLayout(), ST->getMemoryVT(),
492 *ST->getMemOperand()))
495 SDValue Chain = ST->getChain();
496 SDValue BasePtr = ST->getBasePtr();
497 SDValue Value = ST->getValue();
500 if (ST->getAlignment() == 2) {
502 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
503 DAG.getConstant(16, dl, MVT::i32));
504 SDValue StoreLow = DAG.getTruncStore(
505 Chain, dl, Low, BasePtr, ST->getPointerInfo(), MVT::i16,
506 /* Alignment = */ 2, ST->getMemOperand()->getFlags());
507 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
508 DAG.getConstant(2, dl, MVT::i32));
509 SDValue StoreHigh = DAG.getTruncStore(
510 Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2),
511 MVT::i16, /* Alignment = */ 2, ST->getMemOperand()->getFlags());
512 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
515 // Lower to a call to __misaligned_store(BasePtr, Value).
516 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(Context);
517 TargetLowering::ArgListTy Args;
518 TargetLowering::ArgListEntry Entry;
521 Entry.Node = BasePtr;
522 Args.push_back(Entry);
525 Args.push_back(Entry);
527 TargetLowering::CallLoweringInfo CLI(DAG);
528 CLI.setDebugLoc(dl).setChain(Chain).setCallee(
529 CallingConv::C, Type::getVoidTy(Context),
530 DAG.getExternalSymbol("__misaligned_store",
531 getPointerTy(DAG.getDataLayout())),
534 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
535 return CallResult.second;
538 SDValue XCoreTargetLowering::
539 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
541 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
542 "Unexpected operand to lower!");
544 SDValue LHS = Op.getOperand(0);
545 SDValue RHS = Op.getOperand(1);
546 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
547 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
548 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
550 SDValue Lo(Hi.getNode(), 1);
551 SDValue Ops[] = { Lo, Hi };
552 return DAG.getMergeValues(Ops, dl);
555 SDValue XCoreTargetLowering::
556 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
558 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
559 "Unexpected operand to lower!");
561 SDValue LHS = Op.getOperand(0);
562 SDValue RHS = Op.getOperand(1);
563 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
564 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
565 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
567 SDValue Lo(Hi.getNode(), 1);
568 SDValue Ops[] = { Lo, Hi };
569 return DAG.getMergeValues(Ops, dl);
572 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
573 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
574 /// each intermediate result in the calculation must also have a single use.
575 /// If the Op is in the correct form the constituent parts are written to Mul0,
576 /// Mul1, Addend0 and Addend1.
578 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
579 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
581 if (Op.getOpcode() != ISD::ADD)
583 SDValue N0 = Op.getOperand(0);
584 SDValue N1 = Op.getOperand(1);
587 if (N0.getOpcode() == ISD::ADD) {
590 } else if (N1.getOpcode() == ISD::ADD) {
596 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
598 if (OtherOp.getOpcode() == ISD::MUL) {
599 // add(add(a,b),mul(x,y))
600 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
602 Mul0 = OtherOp.getOperand(0);
603 Mul1 = OtherOp.getOperand(1);
604 Addend0 = AddOp.getOperand(0);
605 Addend1 = AddOp.getOperand(1);
608 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
609 // add(add(mul(x,y),a),b)
610 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
612 Mul0 = AddOp.getOperand(0).getOperand(0);
613 Mul1 = AddOp.getOperand(0).getOperand(1);
614 Addend0 = AddOp.getOperand(1);
618 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
619 // add(add(a,mul(x,y)),b)
620 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
622 Mul0 = AddOp.getOperand(1).getOperand(0);
623 Mul1 = AddOp.getOperand(1).getOperand(1);
624 Addend0 = AddOp.getOperand(0);
631 SDValue XCoreTargetLowering::
632 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
636 if (N->getOperand(0).getOpcode() == ISD::MUL) {
637 Mul = N->getOperand(0);
638 Other = N->getOperand(1);
639 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
640 Mul = N->getOperand(1);
641 Other = N->getOperand(0);
646 SDValue LL, RL, AddendL, AddendH;
647 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
648 Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));
649 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
650 Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
651 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
652 Other, DAG.getConstant(0, dl, MVT::i32));
653 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
654 Other, DAG.getConstant(1, dl, MVT::i32));
655 APInt HighMask = APInt::getHighBitsSet(64, 32);
656 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
657 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
658 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
659 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
660 // The inputs are both zero-extended.
661 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
662 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
664 SDValue Lo(Hi.getNode(), 1);
665 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
667 if (LHSSB > 32 && RHSSB > 32) {
668 // The inputs are both sign-extended.
669 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
670 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
672 SDValue Lo(Hi.getNode(), 1);
673 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
676 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
677 Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));
678 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
679 Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));
680 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
681 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
683 SDValue Lo(Hi.getNode(), 1);
684 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
685 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
686 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
687 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
688 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
691 SDValue XCoreTargetLowering::
692 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
694 assert(N->getValueType(0) == MVT::i64 &&
695 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
696 "Unknown operand to lower!");
698 if (N->getOpcode() == ISD::ADD)
699 if (SDValue Result = TryExpandADDWithMul(N, DAG))
704 // Extract components
705 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
707 DAG.getConstant(0, dl, MVT::i32));
708 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
710 DAG.getConstant(1, dl, MVT::i32));
711 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
713 DAG.getConstant(0, dl, MVT::i32));
714 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
716 DAG.getConstant(1, dl, MVT::i32));
719 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
721 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
722 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
724 SDValue Carry(Lo.getNode(), 1);
726 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
728 SDValue Ignored(Hi.getNode(), 1);
730 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
733 SDValue XCoreTargetLowering::
734 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
736 // Whist llvm does not support aggregate varargs we can ignore
737 // the possibility of the ValueType being an implicit byVal vararg.
738 SDNode *Node = Op.getNode();
739 EVT VT = Node->getValueType(0); // not an aggregate
740 SDValue InChain = Node->getOperand(0);
741 SDValue VAListPtr = Node->getOperand(1);
742 EVT PtrVT = VAListPtr.getValueType();
743 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
746 DAG.getLoad(PtrVT, dl, InChain, VAListPtr, MachinePointerInfo(SV));
747 // Increment the pointer, VAList, to the next vararg
748 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
749 DAG.getIntPtrConstant(VT.getSizeInBits() / 8,
751 // Store the incremented VAList to the legalized pointer
752 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
753 MachinePointerInfo(SV));
754 // Load the actual argument out of the pointer VAList
755 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo());
758 SDValue XCoreTargetLowering::
759 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
762 // vastart stores the address of the VarArgsFrameIndex slot into the
763 // memory location argument
764 MachineFunction &MF = DAG.getMachineFunction();
765 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
766 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
767 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
768 MachinePointerInfo());
771 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
772 SelectionDAG &DAG) const {
773 // This nodes represent llvm.frameaddress on the DAG.
774 // It takes one operand, the index of the frame address to return.
775 // An index of zero corresponds to the current function's frame address.
776 // An index of one to the parent's frame address, and so on.
777 // Depths > 0 not supported yet!
778 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
781 MachineFunction &MF = DAG.getMachineFunction();
782 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
783 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op),
784 RegInfo->getFrameRegister(MF), MVT::i32);
787 SDValue XCoreTargetLowering::
788 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
789 // This nodes represent llvm.returnaddress on the DAG.
790 // It takes one operand, the index of the return address to return.
791 // An index of zero corresponds to the current function's return address.
792 // An index of one to the parent's return address, and so on.
793 // Depths > 0 not supported yet!
794 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
797 MachineFunction &MF = DAG.getMachineFunction();
798 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
799 int FI = XFI->createLRSpillSlot(MF);
800 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
801 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
802 DAG.getEntryNode(), FIN,
803 MachinePointerInfo::getFixedStack(MF, FI));
806 SDValue XCoreTargetLowering::
807 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
808 // This node represents offset from frame pointer to first on-stack argument.
809 // This is needed for correct stack adjustment during unwind.
810 // However, we don't know the offset until after the frame has be finalised.
811 // This is done during the XCoreFTAOElim pass.
812 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32);
815 SDValue XCoreTargetLowering::
816 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
817 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)
818 // This node represents 'eh_return' gcc dwarf builtin, which is used to
819 // return from exception. The general meaning is: adjust stack by OFFSET and
820 // pass execution to HANDLER.
821 MachineFunction &MF = DAG.getMachineFunction();
822 SDValue Chain = Op.getOperand(0);
823 SDValue Offset = Op.getOperand(1);
824 SDValue Handler = Op.getOperand(2);
827 // Absolute SP = (FP + FrameToArgs) + Offset
828 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
829 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
830 RegInfo->getFrameRegister(MF), MVT::i32);
831 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl,
833 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs);
834 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset);
836 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
837 // which leaves 2 caller saved registers, R2 & R3 for us to use.
838 unsigned StackReg = XCore::R2;
839 unsigned HandlerReg = XCore::R3;
841 SDValue OutChains[] = {
842 DAG.getCopyToReg(Chain, dl, StackReg, Stack),
843 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
846 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
848 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
849 DAG.getRegister(StackReg, MVT::i32),
850 DAG.getRegister(HandlerReg, MVT::i32));
854 SDValue XCoreTargetLowering::
855 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
856 return Op.getOperand(0);
859 SDValue XCoreTargetLowering::
860 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
861 SDValue Chain = Op.getOperand(0);
862 SDValue Trmp = Op.getOperand(1); // trampoline
863 SDValue FPtr = Op.getOperand(2); // nested function
864 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
866 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
869 // LDAPF_u10 r11, nest
870 // LDW_2rus r11, r11[0]
871 // STWSP_ru6 r11, sp[0]
872 // LDAPF_u10 r11, fptr
873 // LDW_2rus r11, r11[0]
879 SDValue OutChains[5];
885 DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr,
886 MachinePointerInfo(TrmpAddr));
888 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
889 DAG.getConstant(4, dl, MVT::i32));
891 DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr,
892 MachinePointerInfo(TrmpAddr, 4));
894 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
895 DAG.getConstant(8, dl, MVT::i32));
897 DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr,
898 MachinePointerInfo(TrmpAddr, 8));
900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
901 DAG.getConstant(12, dl, MVT::i32));
903 DAG.getStore(Chain, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 12));
905 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
906 DAG.getConstant(16, dl, MVT::i32));
908 DAG.getStore(Chain, dl, FPtr, Addr, MachinePointerInfo(TrmpAddr, 16));
910 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
913 SDValue XCoreTargetLowering::
914 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
916 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
918 case Intrinsic::xcore_crc8:
919 EVT VT = Op.getValueType();
921 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
922 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
923 SDValue Crc(Data.getNode(), 1);
924 SDValue Results[] = { Crc, Data };
925 return DAG.getMergeValues(Results, DL);
930 SDValue XCoreTargetLowering::
931 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
933 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
936 SDValue XCoreTargetLowering::
937 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
938 AtomicSDNode *N = cast<AtomicSDNode>(Op);
939 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
940 assert((N->getOrdering() == AtomicOrdering::Unordered ||
941 N->getOrdering() == AtomicOrdering::Monotonic) &&
942 "setInsertFencesForAtomic(true) expects unordered / monotonic");
943 if (N->getMemoryVT() == MVT::i32) {
944 if (N->getAlignment() < 4)
945 report_fatal_error("atomic load must be aligned");
946 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
947 N->getChain(), N->getBasePtr(), N->getPointerInfo(),
948 N->getAlignment(), N->getMemOperand()->getFlags(),
949 N->getAAInfo(), N->getRanges());
951 if (N->getMemoryVT() == MVT::i16) {
952 if (N->getAlignment() < 2)
953 report_fatal_error("atomic load must be aligned");
954 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
955 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
956 N->getAlignment(), N->getMemOperand()->getFlags(),
959 if (N->getMemoryVT() == MVT::i8)
960 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
961 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
962 N->getAlignment(), N->getMemOperand()->getFlags(),
967 SDValue XCoreTargetLowering::
968 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
969 AtomicSDNode *N = cast<AtomicSDNode>(Op);
970 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
971 assert((N->getOrdering() == AtomicOrdering::Unordered ||
972 N->getOrdering() == AtomicOrdering::Monotonic) &&
973 "setInsertFencesForAtomic(true) expects unordered / monotonic");
974 if (N->getMemoryVT() == MVT::i32) {
975 if (N->getAlignment() < 4)
976 report_fatal_error("atomic store must be aligned");
977 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(),
978 N->getPointerInfo(), N->getAlignment(),
979 N->getMemOperand()->getFlags(), N->getAAInfo());
981 if (N->getMemoryVT() == MVT::i16) {
982 if (N->getAlignment() < 2)
983 report_fatal_error("atomic store must be aligned");
984 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
985 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
986 N->getAlignment(), N->getMemOperand()->getFlags(),
989 if (N->getMemoryVT() == MVT::i8)
990 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
991 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
992 N->getAlignment(), N->getMemOperand()->getFlags(),
997 MachineMemOperand::Flags
998 XCoreTargetLowering::getMMOFlags(const Instruction &I) const {
999 // Because of how we convert atomic_load and atomic_store to normal loads and
1000 // stores in the DAG, we need to ensure that the MMOs are marked volatile
1001 // since DAGCombine hasn't been updated to account for atomic, but non
1002 // volatile loads. (See D57601)
1003 if (auto *SI = dyn_cast<StoreInst>(&I))
1005 return MachineMemOperand::MOVolatile;
1006 if (auto *LI = dyn_cast<LoadInst>(&I))
1008 return MachineMemOperand::MOVolatile;
1009 if (auto *AI = dyn_cast<AtomicRMWInst>(&I))
1011 return MachineMemOperand::MOVolatile;
1012 if (auto *AI = dyn_cast<AtomicCmpXchgInst>(&I))
1014 return MachineMemOperand::MOVolatile;
1015 return MachineMemOperand::MONone;
1018 //===----------------------------------------------------------------------===//
1019 // Calling Convention Implementation
1020 //===----------------------------------------------------------------------===//
1022 #include "XCoreGenCallingConv.inc"
1024 //===----------------------------------------------------------------------===//
1025 // Call Calling Convention Implementation
1026 //===----------------------------------------------------------------------===//
1028 /// XCore call implementation
1030 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1031 SmallVectorImpl<SDValue> &InVals) const {
1032 SelectionDAG &DAG = CLI.DAG;
1034 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1035 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1036 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1037 SDValue Chain = CLI.Chain;
1038 SDValue Callee = CLI.Callee;
1039 bool &isTailCall = CLI.IsTailCall;
1040 CallingConv::ID CallConv = CLI.CallConv;
1041 bool isVarArg = CLI.IsVarArg;
1043 // XCore target does not yet support tail call optimization.
1046 // For now, only CallingConv::C implemented
1050 report_fatal_error("Unsupported calling convention");
1051 case CallingConv::Fast:
1052 case CallingConv::C:
1053 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
1054 Outs, OutVals, Ins, dl, DAG, InVals);
1058 /// LowerCallResult - Lower the result values of a call into the
1059 /// appropriate copies out of appropriate physical registers / memory locations.
1060 static SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1061 const SmallVectorImpl<CCValAssign> &RVLocs,
1062 const SDLoc &dl, SelectionDAG &DAG,
1063 SmallVectorImpl<SDValue> &InVals) {
1064 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
1065 // Copy results out of physical registers.
1066 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1067 const CCValAssign &VA = RVLocs[i];
1068 if (VA.isRegLoc()) {
1069 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1070 InFlag).getValue(1);
1071 InFlag = Chain.getValue(2);
1072 InVals.push_back(Chain.getValue(0));
1074 assert(VA.isMemLoc());
1075 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1077 // Reserve space for this result.
1078 InVals.push_back(SDValue());
1082 // Copy results out of memory.
1083 SmallVector<SDValue, 4> MemOpChains;
1084 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
1085 int offset = ResultMemLocs[i].first;
1086 unsigned index = ResultMemLocs[i].second;
1087 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1088 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };
1089 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
1090 InVals[index] = load;
1091 MemOpChains.push_back(load.getValue(1));
1094 // Transform all loads nodes into one single node because
1095 // all load nodes are independent of each other.
1096 if (!MemOpChains.empty())
1097 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1102 /// LowerCCCCallTo - functions arguments are copied from virtual
1103 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
1104 /// CALLSEQ_END are emitted.
1105 /// TODO: isTailCall, sret.
1106 SDValue XCoreTargetLowering::LowerCCCCallTo(
1107 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
1108 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
1109 const SmallVectorImpl<SDValue> &OutVals,
1110 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1111 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1113 // Analyze operands of the call, assigning locations to each operand.
1114 SmallVector<CCValAssign, 16> ArgLocs;
1115 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1118 // The ABI dictates there should be one stack slot available to the callee
1119 // on function entry (for saving lr).
1120 CCInfo.AllocateStack(4, 4);
1122 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1124 SmallVector<CCValAssign, 16> RVLocs;
1125 // Analyze return values to determine the number of bytes of stack required.
1126 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1128 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
1129 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1131 // Get a count of how many bytes are to be pushed on the stack.
1132 unsigned NumBytes = RetCCInfo.getNextStackOffset();
1133 auto PtrVT = getPointerTy(DAG.getDataLayout());
1135 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1137 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
1138 SmallVector<SDValue, 12> MemOpChains;
1140 // Walk the register/memloc assignments, inserting copies/loads.
1141 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1142 CCValAssign &VA = ArgLocs[i];
1143 SDValue Arg = OutVals[i];
1145 // Promote the value if needed.
1146 switch (VA.getLocInfo()) {
1147 default: llvm_unreachable("Unknown loc info!");
1148 case CCValAssign::Full: break;
1149 case CCValAssign::SExt:
1150 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1152 case CCValAssign::ZExt:
1153 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1155 case CCValAssign::AExt:
1156 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1160 // Arguments that can be passed on register must be kept at
1161 // RegsToPass vector
1162 if (VA.isRegLoc()) {
1163 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1165 assert(VA.isMemLoc());
1167 int Offset = VA.getLocMemOffset();
1169 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
1171 DAG.getConstant(Offset/4, dl,
1176 // Transform all store nodes into one single node because
1177 // all store nodes are independent of each other.
1178 if (!MemOpChains.empty())
1179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1181 // Build a sequence of copy-to-reg nodes chained together with token
1182 // chain and flag operands which copy the outgoing args into registers.
1183 // The InFlag in necessary since all emitted instructions must be
1186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1187 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1188 RegsToPass[i].second, InFlag);
1189 InFlag = Chain.getValue(1);
1192 // If the callee is a GlobalAddress node (quite common, every direct call is)
1193 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1194 // Likewise ExternalSymbol -> TargetExternalSymbol.
1195 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1196 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
1197 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1198 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
1200 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
1201 // = Chain, Callee, Reg#1, Reg#2, ...
1203 // Returns a chain & a flag for retval copy to use.
1204 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1205 SmallVector<SDValue, 8> Ops;
1206 Ops.push_back(Chain);
1207 Ops.push_back(Callee);
1209 // Add argument registers to the end of the list so that they are
1210 // known live into the call.
1211 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1212 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1213 RegsToPass[i].second.getValueType()));
1215 if (InFlag.getNode())
1216 Ops.push_back(InFlag);
1218 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
1219 InFlag = Chain.getValue(1);
1221 // Create the CALLSEQ_END node.
1222 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
1223 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
1224 InFlag = Chain.getValue(1);
1226 // Handle result values, copying them out of physregs into vregs that we
1228 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1231 //===----------------------------------------------------------------------===//
1232 // Formal Arguments Calling Convention Implementation
1233 //===----------------------------------------------------------------------===//
1236 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
1239 /// XCore formal arguments implementation
1240 SDValue XCoreTargetLowering::LowerFormalArguments(
1241 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1242 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1243 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1247 report_fatal_error("Unsupported calling convention");
1248 case CallingConv::C:
1249 case CallingConv::Fast:
1250 return LowerCCCArguments(Chain, CallConv, isVarArg,
1251 Ins, dl, DAG, InVals);
1255 /// LowerCCCArguments - transform physical registers into
1256 /// virtual registers and generate load operations for
1257 /// arguments places on the stack.
1259 SDValue XCoreTargetLowering::LowerCCCArguments(
1260 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1261 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1262 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1263 MachineFunction &MF = DAG.getMachineFunction();
1264 MachineFrameInfo &MFI = MF.getFrameInfo();
1265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1266 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1268 // Assign locations to all of the incoming arguments.
1269 SmallVector<CCValAssign, 16> ArgLocs;
1270 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1273 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1275 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1277 unsigned LRSaveSize = StackSlotSize;
1280 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
1282 // All getCopyFromReg ops must precede any getMemcpys to prevent the
1283 // scheduler clobbering a register before it has been copied.
1285 // 1. CopyFromReg (and load) arg & vararg registers.
1286 // 2. Chain CopyFromReg nodes into a TokenFactor.
1287 // 3. Memcpy 'byVal' args & push final InVals.
1288 // 4. Chain mem ops nodes into a TokenFactor.
1289 SmallVector<SDValue, 4> CFRegNode;
1290 SmallVector<ArgDataPair, 4> ArgData;
1291 SmallVector<SDValue, 4> MemOps;
1293 // 1a. CopyFromReg (and load) arg registers.
1294 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1296 CCValAssign &VA = ArgLocs[i];
1299 if (VA.isRegLoc()) {
1300 // Arguments passed in registers
1301 EVT RegVT = VA.getLocVT();
1302 switch (RegVT.getSimpleVT().SimpleTy) {
1306 errs() << "LowerFormalArguments Unhandled argument type: "
1307 << RegVT.getEVTString() << "\n";
1309 llvm_unreachable(nullptr);
1312 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1313 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1315 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
1319 assert(VA.isMemLoc());
1320 // Load the argument to a virtual register
1321 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1322 if (ObjSize > StackSlotSize) {
1323 errs() << "LowerFormalArguments Unhandled argument type: "
1324 << EVT(VA.getLocVT()).getEVTString()
1327 // Create the frame index object for this incoming parameter...
1328 int FI = MFI.CreateFixedObject(ObjSize,
1329 LRSaveSize + VA.getLocMemOffset(),
1332 // Create the SelectionDAG nodes corresponding to a load
1333 //from this parameter
1334 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1335 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1336 MachinePointerInfo::getFixedStack(MF, FI));
1338 const ArgDataPair ADP = { ArgIn, Ins[i].Flags };
1339 ArgData.push_back(ADP);
1342 // 1b. CopyFromReg vararg registers.
1344 // Argument registers
1345 static const MCPhysReg ArgRegs[] = {
1346 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1348 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1349 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1350 if (FirstVAReg < array_lengthof(ArgRegs)) {
1352 // Save remaining registers, storing higher register numbers at a higher
1354 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1355 // Create a stack slot
1356 int FI = MFI.CreateFixedObject(4, offset, true);
1357 if (i == (int)FirstVAReg) {
1358 XFI->setVarArgsFrameIndex(FI);
1360 offset -= StackSlotSize;
1361 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1362 // Move argument from phys reg -> virt reg
1363 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1364 RegInfo.addLiveIn(ArgRegs[i], VReg);
1365 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1366 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
1367 // Move argument from virt reg -> stack
1369 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
1370 MemOps.push_back(Store);
1373 // This will point to the next argument passed via stack.
1374 XFI->setVarArgsFrameIndex(
1375 MFI.CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1380 // 2. chain CopyFromReg nodes into a TokenFactor.
1381 if (!CFRegNode.empty())
1382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
1384 // 3. Memcpy 'byVal' args & push final InVals.
1385 // Aggregates passed "byVal" need to be copied by the callee.
1386 // The callee will use a pointer to this copy, rather than the original
1388 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(),
1389 ArgDE = ArgData.end();
1390 ArgDI != ArgDE; ++ArgDI) {
1391 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) {
1392 unsigned Size = ArgDI->Flags.getByValSize();
1393 unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign());
1394 // Create a new object on the stack and copy the pointee into it.
1395 int FI = MFI.CreateStackObject(Size, Align, false);
1396 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1397 InVals.push_back(FIN);
1398 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
1399 DAG.getConstant(Size, dl, MVT::i32),
1400 Align, false, false, false,
1401 MachinePointerInfo(),
1402 MachinePointerInfo()));
1404 InVals.push_back(ArgDI->SDV);
1408 // 4, chain mem ops nodes into a TokenFactor.
1409 if (!MemOps.empty()) {
1410 MemOps.push_back(Chain);
1411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1417 //===----------------------------------------------------------------------===//
1418 // Return Value Calling Convention Implementation
1419 //===----------------------------------------------------------------------===//
1421 bool XCoreTargetLowering::
1422 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1424 const SmallVectorImpl<ISD::OutputArg> &Outs,
1425 LLVMContext &Context) const {
1426 SmallVector<CCValAssign, 16> RVLocs;
1427 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1428 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1430 if (CCInfo.getNextStackOffset() != 0 && isVarArg)
1436 XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1438 const SmallVectorImpl<ISD::OutputArg> &Outs,
1439 const SmallVectorImpl<SDValue> &OutVals,
1440 const SDLoc &dl, SelectionDAG &DAG) const {
1442 XCoreFunctionInfo *XFI =
1443 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1444 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1446 // CCValAssign - represent the assignment of
1447 // the return value to a location
1448 SmallVector<CCValAssign, 16> RVLocs;
1450 // CCState - Info about the registers and stack slot.
1451 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1454 // Analyze return values.
1456 CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
1458 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1461 SmallVector<SDValue, 4> RetOps(1, Chain);
1463 // Return on XCore is always a "retsp 0"
1464 RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));
1466 SmallVector<SDValue, 4> MemOpChains;
1467 // Handle return values that must be copied to memory.
1468 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1469 CCValAssign &VA = RVLocs[i];
1472 assert(VA.isMemLoc());
1474 report_fatal_error("Can't return value from vararg function in memory");
1477 int Offset = VA.getLocMemOffset();
1478 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
1479 // Create the frame index object for the memory location.
1480 int FI = MFI.CreateFixedObject(ObjSize, Offset, false);
1482 // Create a SelectionDAG node corresponding to a store
1483 // to this memory location.
1484 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1485 MemOpChains.push_back(DAG.getStore(
1486 Chain, dl, OutVals[i], FIN,
1487 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
1490 // Transform all store nodes into one single node because
1491 // all stores are independent of each other.
1492 if (!MemOpChains.empty())
1493 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1495 // Now handle return values copied to registers.
1496 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1497 CCValAssign &VA = RVLocs[i];
1500 // Copy the result values into the output registers.
1501 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1503 // guarantee that all emitted copies are
1504 // stuck together, avoiding something bad
1505 Flag = Chain.getValue(1);
1506 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1509 RetOps[0] = Chain; // Update chain.
1511 // Add the flag if we have it.
1513 RetOps.push_back(Flag);
1515 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
1518 //===----------------------------------------------------------------------===//
1519 // Other Lowering Code
1520 //===----------------------------------------------------------------------===//
1523 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1524 MachineBasicBlock *BB) const {
1525 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1526 DebugLoc dl = MI.getDebugLoc();
1527 assert((MI.getOpcode() == XCore::SELECT_CC) &&
1528 "Unexpected instr type to insert");
1530 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1531 // control-flow pattern. The incoming instruction knows the destination vreg
1532 // to set, the condition code register to branch on, the true/false values to
1533 // select between, and a branch opcode to use.
1534 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1535 MachineFunction::iterator It = ++BB->getIterator();
1540 // cmpTY ccX, r1, r2
1542 // fallthrough --> copy0MBB
1543 MachineBasicBlock *thisMBB = BB;
1544 MachineFunction *F = BB->getParent();
1545 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1546 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1547 F->insert(It, copy0MBB);
1548 F->insert(It, sinkMBB);
1550 // Transfer the remainder of BB and its successor edges to sinkMBB.
1551 sinkMBB->splice(sinkMBB->begin(), BB,
1552 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1553 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1555 // Next, add the true and fallthrough blocks as its successors.
1556 BB->addSuccessor(copy0MBB);
1557 BB->addSuccessor(sinkMBB);
1559 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1560 .addReg(MI.getOperand(1).getReg())
1564 // %FalseValue = ...
1565 // # fallthrough to sinkMBB
1568 // Update machine-CFG edges
1569 BB->addSuccessor(sinkMBB);
1572 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
1576 .addReg(MI.getOperand(3).getReg())
1578 .addReg(MI.getOperand(2).getReg())
1581 MI.eraseFromParent(); // The pseudo instruction is gone now.
1585 //===----------------------------------------------------------------------===//
1586 // Target Optimization Hooks
1587 //===----------------------------------------------------------------------===//
1589 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1590 DAGCombinerInfo &DCI) const {
1591 SelectionDAG &DAG = DCI.DAG;
1593 switch (N->getOpcode()) {
1595 case ISD::INTRINSIC_VOID:
1596 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
1597 case Intrinsic::xcore_outt:
1598 case Intrinsic::xcore_outct:
1599 case Intrinsic::xcore_chkct: {
1600 SDValue OutVal = N->getOperand(3);
1601 // These instructions ignore the high bits.
1602 if (OutVal.hasOneUse()) {
1603 unsigned BitWidth = OutVal.getValueSizeInBits();
1604 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
1606 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1607 !DCI.isBeforeLegalizeOps());
1608 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1609 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) ||
1610 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO))
1611 DCI.CommitTargetLoweringOpt(TLO);
1615 case Intrinsic::xcore_setpt: {
1616 SDValue Time = N->getOperand(3);
1617 // This instruction ignores the high bits.
1618 if (Time.hasOneUse()) {
1619 unsigned BitWidth = Time.getValueSizeInBits();
1620 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
1622 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1623 !DCI.isBeforeLegalizeOps());
1624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1625 if (TLI.ShrinkDemandedConstant(Time, DemandedMask, TLO) ||
1626 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO))
1627 DCI.CommitTargetLoweringOpt(TLO);
1633 case XCoreISD::LADD: {
1634 SDValue N0 = N->getOperand(0);
1635 SDValue N1 = N->getOperand(1);
1636 SDValue N2 = N->getOperand(2);
1637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1639 EVT VT = N0.getValueType();
1641 // canonicalize constant to RHS
1643 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1645 // fold (ladd 0, 0, x) -> 0, x & 1
1646 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1647 SDValue Carry = DAG.getConstant(0, dl, VT);
1648 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1649 DAG.getConstant(1, dl, VT));
1650 SDValue Ops[] = { Result, Carry };
1651 return DAG.getMergeValues(Ops, dl);
1654 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1656 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1657 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1658 VT.getSizeInBits() - 1);
1659 KnownBits Known = DAG.computeKnownBits(N2);
1660 if ((Known.Zero & Mask) == Mask) {
1661 SDValue Carry = DAG.getConstant(0, dl, VT);
1662 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1663 SDValue Ops[] = { Result, Carry };
1664 return DAG.getMergeValues(Ops, dl);
1669 case XCoreISD::LSUB: {
1670 SDValue N0 = N->getOperand(0);
1671 SDValue N1 = N->getOperand(1);
1672 SDValue N2 = N->getOperand(2);
1673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1675 EVT VT = N0.getValueType();
1677 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1678 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1679 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1680 VT.getSizeInBits() - 1);
1681 KnownBits Known = DAG.computeKnownBits(N2);
1682 if ((Known.Zero & Mask) == Mask) {
1683 SDValue Borrow = N2;
1684 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1685 DAG.getConstant(0, dl, VT), N2);
1686 SDValue Ops[] = { Result, Borrow };
1687 return DAG.getMergeValues(Ops, dl);
1691 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1693 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1694 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1695 VT.getSizeInBits() - 1);
1696 KnownBits Known = DAG.computeKnownBits(N2);
1697 if ((Known.Zero & Mask) == Mask) {
1698 SDValue Borrow = DAG.getConstant(0, dl, VT);
1699 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1700 SDValue Ops[] = { Result, Borrow };
1701 return DAG.getMergeValues(Ops, dl);
1706 case XCoreISD::LMUL: {
1707 SDValue N0 = N->getOperand(0);
1708 SDValue N1 = N->getOperand(1);
1709 SDValue N2 = N->getOperand(2);
1710 SDValue N3 = N->getOperand(3);
1711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1713 EVT VT = N0.getValueType();
1714 // Canonicalize multiplicative constant to RHS. If both multiplicative
1715 // operands are constant canonicalize smallest to RHS.
1716 if ((N0C && !N1C) ||
1717 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1718 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1722 if (N1C && N1C->isNullValue()) {
1723 // If the high result is unused fold to add(a, b)
1724 if (N->hasNUsesOfValue(0, 0)) {
1725 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1726 SDValue Ops[] = { Lo, Lo };
1727 return DAG.getMergeValues(Ops, dl);
1729 // Otherwise fold to ladd(a, b, 0)
1731 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1732 SDValue Carry(Result.getNode(), 1);
1733 SDValue Ops[] = { Carry, Result };
1734 return DAG.getMergeValues(Ops, dl);
1739 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1740 // lmul(x, y, a, b). The high result of lmul will be ignored.
1741 // This is only profitable if the intermediate results are unused
1743 SDValue Mul0, Mul1, Addend0, Addend1;
1744 if (N->getValueType(0) == MVT::i32 &&
1745 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1746 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1747 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1748 Mul1, Addend0, Addend1);
1749 SDValue Result(Ignored.getNode(), 1);
1752 APInt HighMask = APInt::getHighBitsSet(64, 32);
1753 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1754 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1755 // before type legalization as it is messy to match the operands after
1757 if (N->getValueType(0) == MVT::i64 &&
1758 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1759 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1760 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1761 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1762 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1763 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1764 Mul0, DAG.getConstant(0, dl, MVT::i32));
1765 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1766 Mul1, DAG.getConstant(0, dl, MVT::i32));
1767 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1768 Addend0, DAG.getConstant(0, dl, MVT::i32));
1769 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1770 Addend1, DAG.getConstant(0, dl, MVT::i32));
1771 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1772 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1773 Addend0L, Addend1L);
1774 SDValue Lo(Hi.getNode(), 1);
1775 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1780 // Replace unaligned store of unaligned load with memmove.
1781 StoreSDNode *ST = cast<StoreSDNode>(N);
1782 if (!DCI.isBeforeLegalize() ||
1783 allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
1784 ST->getMemoryVT(), *ST->getMemOperand()) ||
1785 ST->isVolatile() || ST->isIndexed()) {
1788 SDValue Chain = ST->getChain();
1790 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1791 assert((StoreBits % 8) == 0 &&
1792 "Store size in bits must be a multiple of 8");
1793 unsigned Alignment = ST->getAlignment();
1795 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1796 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1797 LD->getAlignment() == Alignment &&
1798 !LD->isVolatile() && !LD->isIndexed() &&
1799 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1800 bool isTail = isInTailCallPosition(DAG, ST, Chain);
1801 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1803 DAG.getConstant(StoreBits/8, dl, MVT::i32),
1804 Alignment, false, isTail, ST->getPointerInfo(),
1805 LD->getPointerInfo());
1814 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1816 const APInt &DemandedElts,
1817 const SelectionDAG &DAG,
1818 unsigned Depth) const {
1820 switch (Op.getOpcode()) {
1822 case XCoreISD::LADD:
1823 case XCoreISD::LSUB:
1824 if (Op.getResNo() == 1) {
1825 // Top bits of carry / borrow are clear.
1826 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1827 Known.getBitWidth() - 1);
1830 case ISD::INTRINSIC_W_CHAIN:
1832 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1834 case Intrinsic::xcore_getts:
1835 // High bits are known to be zero.
1836 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1837 Known.getBitWidth() - 16);
1839 case Intrinsic::xcore_int:
1840 case Intrinsic::xcore_inct:
1841 // High bits are known to be zero.
1842 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1843 Known.getBitWidth() - 8);
1845 case Intrinsic::xcore_testct:
1846 // Result is either 0 or 1.
1847 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1848 Known.getBitWidth() - 1);
1850 case Intrinsic::xcore_testwct:
1851 // Result is in the range 0 - 4.
1852 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1853 Known.getBitWidth() - 3);
1861 //===----------------------------------------------------------------------===//
1862 // Addressing mode description hooks
1863 //===----------------------------------------------------------------------===//
1865 static inline bool isImmUs(int64_t val)
1867 return (val >= 0 && val <= 11);
1870 static inline bool isImmUs2(int64_t val)
1872 return (val%2 == 0 && isImmUs(val/2));
1875 static inline bool isImmUs4(int64_t val)
1877 return (val%4 == 0 && isImmUs(val/4));
1880 /// isLegalAddressingMode - Return true if the addressing mode represented
1881 /// by AM is legal for this target, for a load/store of the specified type.
1882 bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1883 const AddrMode &AM, Type *Ty,
1885 Instruction *I) const {
1886 if (Ty->getTypeID() == Type::VoidTyID)
1887 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1889 unsigned Size = DL.getTypeAllocSize(Ty);
1891 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1898 if (AM.Scale == 0) {
1899 return isImmUs(AM.BaseOffs);
1902 return AM.Scale == 1 && AM.BaseOffs == 0;
1906 if (AM.Scale == 0) {
1907 return isImmUs2(AM.BaseOffs);
1910 return AM.Scale == 2 && AM.BaseOffs == 0;
1913 if (AM.Scale == 0) {
1914 return isImmUs4(AM.BaseOffs);
1917 return AM.Scale == 4 && AM.BaseOffs == 0;
1921 //===----------------------------------------------------------------------===//
1922 // XCore Inline Assembly Support
1923 //===----------------------------------------------------------------------===//
1925 std::pair<unsigned, const TargetRegisterClass *>
1926 XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1927 StringRef Constraint,
1929 if (Constraint.size() == 1) {
1930 switch (Constraint[0]) {
1933 return std::make_pair(0U, &XCore::GRRegsRegClass);
1936 // Use the default implementation in TargetLowering to convert the register
1937 // constraint into a member of a register class.
1938 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);