1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file is part of the X86 Disassembler Emitter.
10 // It contains the interface of a single recognizable instruction.
11 // Documentation for the disassembler emitter in general can be found in
12 // X86DisassemblerEmitter.h.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
19 #include "CodeGenTarget.h"
20 #include "X86DisassemblerTables.h"
21 #include "llvm/Support/DataTypes.h"
22 #include "llvm/TableGen/Record.h"
26 #define X86_INSTR_MRM_MAPPING \
92 // A clone of X86 since we can't depend on something that is generated.
114 MRMXmCC = 30, MRMXm = 31,
115 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35,
116 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39,
122 MRMXrCC = 46, MRMXr = 47,
123 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51,
124 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55,
125 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59,
126 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63,
127 #define MAP(from, to) MRM_##from = to,
128 X86_INSTR_MRM_MAPPING
133 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7
137 PD = 1, XS = 2, XD = 3, PS = 4
141 VEX = 1, XOP = 2, EVEX = 3
145 OpSize16 = 1, OpSize32 = 2
149 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
153 namespace X86Disassembler {
155 /// RecognizableInstr - Encapsulates all information required to decode a single
156 /// instruction, as extracted from the LLVM instruction tables. Has methods
157 /// to interpret the information available in the LLVM tables, and to emit the
158 /// instruction into DisassemblerTables.
159 class RecognizableInstr {
161 /// The opcode of the instruction, as used in an MCInst
163 /// The record from the .td files corresponding to this instruction
165 /// The OpPrefix field from the record
167 /// The OpMap field from the record
169 /// The opcode field from the record; this is the opcode used in the Intel
170 /// encoding and therefore distinct from the UID
172 /// The form field from the record
174 // The encoding field from the record
176 /// The OpSize field from the record
178 /// The AdSize field from the record
180 /// The hasREX_WPrefix field from the record
182 /// The hasVEX_4V field from the record
184 /// The HasVEX_WPrefix field from the record
186 /// The IgnoresVEX_W field from the record
188 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
190 /// The ignoreVEX_L field from the record
192 /// The hasEVEX_L2Prefix field from the record
193 bool HasEVEX_L2Prefix;
194 /// The hasEVEX_K field from the record
196 /// The hasEVEX_KZ field from the record
198 /// The hasEVEX_B field from the record
200 /// Indicates that the instruction uses the L and L' fields for RC.
202 /// The isCodeGenOnly field from the record
204 /// The ForceDisassemble field from the record
205 bool ForceDisassemble;
206 // The CD8_Scale field from the record
208 // Whether the instruction has the predicate "In64BitMode"
210 // Whether the instruction has the predicate "In32BitMode"
213 /// The instruction name as listed in the tables
216 /// Indicates whether the instruction should be emitted into the decode
217 /// tables; regardless, it will be emitted into the instruction info table
218 bool ShouldBeEmitted;
220 /// The operands of the instruction, as listed in the CodeGenInstruction.
221 /// They are not one-to-one with operands listed in the MCInst; for example,
222 /// memory operands expand to 5 operands in the MCInst
223 const std::vector<CGIOperandList::OperandInfo>* Operands;
225 /// The description of the instruction that is emitted into the instruction
227 InstructionSpecifier* Spec;
229 /// insnContext - Returns the primary context in which the instruction is
232 /// @return - The context in which the instruction is valid.
233 InstructionContext insnContext() const;
235 /// typeFromString - Translates an operand type from the string provided in
236 /// the LLVM tables to an OperandType for use in the operand specifier.
238 /// @param s - The string, as extracted by calling Rec->getName()
239 /// on a CodeGenInstruction::OperandInfo.
240 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
241 /// prefix. If it does, 32-bit register operands stay
242 /// 32-bit regardless of the operand size.
243 /// @param OpSize Indicates the operand size of the instruction.
244 /// If register size does not match OpSize, then
245 /// register sizes keep their size.
246 /// @return - The operand's type.
247 static OperandType typeFromString(const std::string& s,
248 bool hasREX_WPrefix, uint8_t OpSize);
250 /// immediateEncodingFromString - Translates an immediate encoding from the
251 /// string provided in the LLVM tables to an OperandEncoding for use in
252 /// the operand specifier.
254 /// @param s - See typeFromString().
255 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
256 /// If it is not, then 16-bit immediate operands stay 16-bit.
257 /// @return - The operand's encoding.
258 static OperandEncoding immediateEncodingFromString(const std::string &s,
261 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
262 /// handles operands that are in the REG field of the ModR/M byte.
263 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
266 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
267 /// handles operands that are in the REG field of the ModR/M byte.
268 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
270 static OperandEncoding memoryEncodingFromString(const std::string &s,
272 static OperandEncoding relocationEncodingFromString(const std::string &s,
274 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
276 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
278 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
281 /// Adjust the encoding type for an operand based on the instruction.
282 void adjustOperandEncoding(OperandEncoding &encoding);
284 /// handleOperand - Converts a single operand from the LLVM table format to
285 /// the emitted table format, handling any duplicate operands it encounters
286 /// and then one non-duplicate.
288 /// @param optional - Determines whether to assert that the
290 /// @param operandIndex - The index into the generated operand table.
291 /// Incremented by this function one or more
292 /// times to reflect possible duplicate
294 /// @param physicalOperandIndex - The index of the current operand into the
295 /// set of non-duplicate ('physical') operands.
296 /// Incremented by this function once.
297 /// @param numPhysicalOperands - The number of non-duplicate operands in the
299 /// @param operandMapping - The operand mapping, which has an entry for
300 /// each operand that indicates whether it is a
301 /// duplicate, and of what.
302 void handleOperand(bool optional,
303 unsigned &operandIndex,
304 unsigned &physicalOperandIndex,
305 unsigned numPhysicalOperands,
306 const unsigned *operandMapping,
307 OperandEncoding (*encodingFromString)
311 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
312 /// filters out many instructions, at various points in decoding we
313 /// determine that the instruction should not actually be decodable. In
314 /// particular, MMX MOV instructions aren't emitted, but they're only
315 /// identified during operand parsing.
317 /// @return - true if at this point we believe the instruction should be
318 /// emitted; false if not. This will return false if filter() returns false
319 /// once emitInstructionSpecifier() has been called.
320 bool shouldBeEmitted() const {
321 return ShouldBeEmitted;
324 /// emitInstructionSpecifier - Loads the instruction specifier for the current
325 /// instruction into a DisassemblerTables.
327 void emitInstructionSpecifier();
329 /// emitDecodePath - Populates the proper fields in the decode tables
330 /// corresponding to the decode paths for this instruction.
332 /// \param tables The DisassemblerTables to populate with the decode
333 /// decode information for the current instruction.
334 void emitDecodePath(DisassemblerTables &tables) const;
336 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
337 /// from a CodeGenInstruction.
339 /// \param tables The DisassemblerTables that the specifier will be added to.
340 /// \param insn The CodeGenInstruction to extract information from.
341 /// \param uid The unique ID of the current instruction.
342 RecognizableInstr(DisassemblerTables &tables,
343 const CodeGenInstruction &insn,
346 /// processInstr - Accepts a CodeGenInstruction and loads decode information
347 /// for it into a DisassemblerTables if appropriate.
349 /// \param tables The DiassemblerTables to be populated with decode
351 /// \param insn The CodeGenInstruction to be used as a source for this
353 /// \param uid The unique ID of the instruction.
354 static void processInstr(DisassemblerTables &tables,
355 const CodeGenInstruction &insn,
359 } // namespace X86Disassembler