2 * Copyright (c) 2006-2016 Chelsio, Inc. All rights reserved.
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
42 struct c4iw_stats c4iw_stats;
45 static void copy_wr_to_sq(struct t4_wq *wq, union t4_wr *wqe, u8 len16)
52 dst = &wq->sq.queue->flits[wq->sq.wq_pidx *
53 (T4_EQ_ENTRY_SIZE / sizeof(__be64))];
54 if (t4_sq_onchip(wq)) {
55 len16 = align(len16, 4);
57 /* In onchip mode the copy below will be made to WC memory and
58 * could trigger DMA. In offchip mode the copy below only
59 * queues the WQE, DMA cannot start until t4_ring_sq_db
64 /* NOTE len16 cannot be large enough to write to the
65 same sq.queue memory twice in this loop */
67 end = (uintptr_t)&wq->sq.queue[wq->sq.size];
68 if (__predict_true((uintptr_t)dst + total <= end)) {
69 /* Won't wrap around. */
70 memcpy(dst, src, total);
72 len = end - (uintptr_t)dst;
73 memcpy(dst, src, len);
74 memcpy(wq->sq.queue, src + len, total - len);
81 static void copy_wr_to_rq(struct t4_wq *wq, union t4_recv_wr *wqe, u8 len16)
88 dst = &wq->rq.queue->flits[wq->rq.wq_pidx *
89 (T4_EQ_ENTRY_SIZE / sizeof(__be64))];
92 end = (uintptr_t)&wq->rq.queue[wq->rq.size];
93 if (__predict_true((uintptr_t)dst + total <= end)) {
94 /* Won't wrap around. */
95 memcpy(dst, src, total);
97 len = end - (uintptr_t)dst;
98 memcpy(dst, src, len);
99 memcpy(wq->rq.queue, src + len, total - len);
103 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
104 struct ibv_send_wr *wr, int max, u32 *plenp)
111 dstp = (u8 *)immdp->data;
112 for (i = 0; i < wr->num_sge; i++) {
113 if ((plen + wr->sg_list[i].length) > max)
115 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
116 plen += wr->sg_list[i].length;
117 len = wr->sg_list[i].length;
118 memcpy(dstp, srcp, len);
122 len = ROUND_UP(plen + 8, 16) - (plen + 8);
124 memset(dstp, 0, len);
125 immdp->op = FW_RI_DATA_IMMD;
128 immdp->immdlen = htobe32(plen);
133 static int build_isgl(struct fw_ri_isgl *isglp, struct ibv_sge *sg_list,
134 int num_sge, u32 *plenp)
138 __be64 *flitp = (__be64 *)isglp->sge;
140 for (i = 0; i < num_sge; i++) {
141 if ((plen + sg_list[i].length) < plen)
143 plen += sg_list[i].length;
144 *flitp++ = htobe64(((u64)sg_list[i].lkey << 32) |
146 *flitp++ = htobe64(sg_list[i].addr);
149 isglp->op = FW_RI_DATA_ISGL;
151 isglp->nsge = htobe16(num_sge);
158 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
159 struct ibv_send_wr *wr, u8 *len16)
165 if (wr->num_sge > T4_MAX_SEND_SGE)
167 if (wr->send_flags & IBV_SEND_SOLICITED)
168 wqe->send.sendop_pkd = htobe32(
169 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
171 wqe->send.sendop_pkd = htobe32(
172 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
173 wqe->send.stag_inv = 0;
179 if (wr->send_flags & IBV_SEND_INLINE) {
180 ret = build_immd(sq, wqe->send.u.immd_src, wr,
181 T4_MAX_SEND_INLINE, &plen);
184 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
187 ret = build_isgl(wqe->send.u.isgl_src,
188 wr->sg_list, wr->num_sge, &plen);
191 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
192 wr->num_sge * sizeof (struct fw_ri_sge);
195 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
196 wqe->send.u.immd_src[0].r1 = 0;
197 wqe->send.u.immd_src[0].r2 = 0;
198 wqe->send.u.immd_src[0].immdlen = 0;
199 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
202 *len16 = DIV_ROUND_UP(size, 16);
203 wqe->send.plen = htobe32(plen);
207 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
208 struct ibv_send_wr *wr, u8 *len16)
214 if (wr->num_sge > T4_MAX_SEND_SGE)
217 wqe->write.stag_sink = htobe32(wr->wr.rdma.rkey);
218 wqe->write.to_sink = htobe64(wr->wr.rdma.remote_addr);
220 if (wr->send_flags & IBV_SEND_INLINE) {
221 ret = build_immd(sq, wqe->write.u.immd_src, wr,
222 T4_MAX_WRITE_INLINE, &plen);
225 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
228 ret = build_isgl(wqe->write.u.isgl_src,
229 wr->sg_list, wr->num_sge, &plen);
232 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
233 wr->num_sge * sizeof (struct fw_ri_sge);
236 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
237 wqe->write.u.immd_src[0].r1 = 0;
238 wqe->write.u.immd_src[0].r2 = 0;
239 wqe->write.u.immd_src[0].immdlen = 0;
240 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
243 *len16 = DIV_ROUND_UP(size, 16);
244 wqe->write.plen = htobe32(plen);
248 static int build_rdma_read(union t4_wr *wqe, struct ibv_send_wr *wr, u8 *len16)
253 wqe->read.stag_src = htobe32(wr->wr.rdma.rkey);
254 wqe->read.to_src_hi = htobe32((u32)(wr->wr.rdma.remote_addr >>32));
255 wqe->read.to_src_lo = htobe32((u32)wr->wr.rdma.remote_addr);
256 wqe->read.stag_sink = htobe32(wr->sg_list[0].lkey);
257 wqe->read.plen = htobe32(wr->sg_list[0].length);
258 wqe->read.to_sink_hi = htobe32((u32)(wr->sg_list[0].addr >> 32));
259 wqe->read.to_sink_lo = htobe32((u32)(wr->sg_list[0].addr));
261 wqe->read.stag_src = htobe32(2);
262 wqe->read.to_src_hi = 0;
263 wqe->read.to_src_lo = 0;
264 wqe->read.stag_sink = htobe32(2);
266 wqe->read.to_sink_hi = 0;
267 wqe->read.to_sink_lo = 0;
271 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
275 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
276 struct ibv_recv_wr *wr, u8 *len16)
280 ret = build_isgl(&wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
283 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
284 wr->num_sge * sizeof(struct fw_ri_sge), 16);
288 static void ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 idx)
290 struct ibv_modify_qp cmd = {};
291 struct ibv_qp_attr attr;
293 int __attribute__((unused)) ret;
295 /* FIXME: Why do we need this barrier if the kernel is going to
297 udma_to_device_barrier();
298 if (qid == qhp->wq.sq.qid) {
300 mask = IBV_QP_SQ_PSN;
303 mask = IBV_QP_RQ_PSN;
305 ret = ibv_cmd_modify_qp(&qhp->ibv_qp, &attr, mask, &cmd, sizeof cmd);
309 int c4iw_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
310 struct ibv_send_wr **bad_wr)
314 enum fw_wr_opcodes fw_opcode;
315 enum fw_ri_wr_flags fw_flags;
317 union t4_wr *wqe, lwqe;
319 struct t4_swsqe *swsqe;
322 qhp = to_c4iw_qp(ibqp);
323 pthread_spin_lock(&qhp->lock);
324 if (t4_wq_in_error(&qhp->wq)) {
325 pthread_spin_unlock(&qhp->lock);
329 num_wrs = t4_sq_avail(&qhp->wq);
331 pthread_spin_unlock(&qhp->lock);
344 if (wr->send_flags & IBV_SEND_SOLICITED)
345 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
346 if (wr->send_flags & IBV_SEND_SIGNALED || qhp->sq_sig_all)
347 fw_flags |= FW_RI_COMPLETION_FLAG;
348 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
349 switch (wr->opcode) {
352 if (wr->send_flags & IBV_SEND_FENCE)
353 fw_flags |= FW_RI_READ_FENCE_FLAG;
354 fw_opcode = FW_RI_SEND_WR;
355 swsqe->opcode = FW_RI_SEND;
356 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
358 case IBV_WR_RDMA_WRITE:
360 fw_opcode = FW_RI_RDMA_WRITE_WR;
361 swsqe->opcode = FW_RI_RDMA_WRITE;
362 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
364 case IBV_WR_RDMA_READ:
366 fw_opcode = FW_RI_RDMA_READ_WR;
367 swsqe->opcode = FW_RI_READ_REQ;
369 err = build_rdma_read(wqe, wr, &len16);
372 swsqe->read_len = wr->sg_list ? wr->sg_list[0].length :
374 if (!qhp->wq.sq.oldest_read)
375 qhp->wq.sq.oldest_read = swsqe;
378 PDBG("%s post of type=%d TBD!\n", __func__,
386 swsqe->idx = qhp->wq.sq.pidx;
388 swsqe->signaled = (wr->send_flags & IBV_SEND_SIGNALED) ||
391 swsqe->wr_id = wr->wr_id;
393 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
394 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x\n",
395 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
399 copy_wr_to_sq(&qhp->wq, wqe, len16);
400 t4_sq_produce(&qhp->wq, len16);
401 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
403 if (t4_wq_db_enabled(&qhp->wq)) {
404 t4_ring_sq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
407 ring_kernel_db(qhp, qhp->wq.sq.qid, idx);
408 /* This write is only for debugging, the value does not matter for DMA
410 qhp->wq.sq.queue[qhp->wq.sq.size].status.host_wq_pidx = \
411 (qhp->wq.sq.wq_pidx);
413 pthread_spin_unlock(&qhp->lock);
417 int c4iw_post_receive(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
418 struct ibv_recv_wr **bad_wr)
422 union t4_recv_wr *wqe, lwqe;
427 qhp = to_c4iw_qp(ibqp);
428 pthread_spin_lock(&qhp->lock);
429 if (t4_wq_in_error(&qhp->wq)) {
430 pthread_spin_unlock(&qhp->lock);
435 num_wrs = t4_rq_avail(&qhp->wq);
437 pthread_spin_unlock(&qhp->lock);
442 if (wr->num_sge > T4_MAX_RECV_SGE) {
449 err = build_rdma_recv(qhp, wqe, wr, &len16);
457 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
459 wqe->recv.opcode = FW_RI_RECV_WR;
461 wqe->recv.wrid = qhp->wq.rq.pidx;
465 wqe->recv.len16 = len16;
466 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
467 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
468 copy_wr_to_rq(&qhp->wq, wqe, len16);
469 t4_rq_produce(&qhp->wq, len16);
470 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
474 if (t4_wq_db_enabled(&qhp->wq))
475 t4_ring_rq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
478 ring_kernel_db(qhp, qhp->wq.rq.qid, idx);
479 qhp->wq.rq.queue[qhp->wq.rq.size].status.host_wq_pidx = \
480 (qhp->wq.rq.wq_pidx);
481 pthread_spin_unlock(&qhp->lock);
485 static void update_qp_state(struct c4iw_qp *qhp)
487 struct ibv_query_qp cmd;
488 struct ibv_qp_attr attr;
489 struct ibv_qp_init_attr iattr;
492 ret = ibv_cmd_query_qp(&qhp->ibv_qp, &attr, IBV_QP_STATE, &iattr,
496 qhp->ibv_qp.state = attr.qp_state;
500 * Assumes qhp lock is held.
502 void c4iw_flush_qp(struct c4iw_qp *qhp)
504 struct c4iw_cq *rchp, *schp;
510 update_qp_state(qhp);
512 rchp = to_c4iw_cq(qhp->ibv_qp.recv_cq);
513 schp = to_c4iw_cq(qhp->ibv_qp.send_cq);
515 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
517 pthread_spin_unlock(&qhp->lock);
519 /* locking heirarchy: cq lock first, then qp lock. */
520 pthread_spin_lock(&rchp->lock);
521 pthread_spin_lock(&qhp->lock);
522 c4iw_flush_hw_cq(rchp);
523 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
524 c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
525 pthread_spin_unlock(&qhp->lock);
526 pthread_spin_unlock(&rchp->lock);
528 /* locking heirarchy: cq lock first, then qp lock. */
529 pthread_spin_lock(&schp->lock);
530 pthread_spin_lock(&qhp->lock);
532 c4iw_flush_hw_cq(schp);
534 pthread_spin_unlock(&qhp->lock);
535 pthread_spin_unlock(&schp->lock);
536 pthread_spin_lock(&qhp->lock);
539 void c4iw_flush_qps(struct c4iw_dev *dev)
543 pthread_spin_lock(&dev->lock);
544 for (i=0; i < dev->max_qp; i++) {
545 struct c4iw_qp *qhp = dev->qpid2ptr[i];
547 if (!qhp->wq.flushed && t4_wq_in_error(&qhp->wq)) {
548 pthread_spin_lock(&qhp->lock);
550 pthread_spin_unlock(&qhp->lock);
554 pthread_spin_unlock(&dev->lock);