2 * Copyright (c) 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies Ltd. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
42 #include <infiniband/opcode.h>
48 MLX4_CQ_DOORBELL = 0x20
57 #define MLX4_CQ_DB_REQ_NOT_SOL (1 << 24)
58 #define MLX4_CQ_DB_REQ_NOT (2 << 24)
61 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
62 MLX4_CQE_QPN_MASK = 0xffffff,
66 MLX4_CQE_OWNER_MASK = 0x80,
67 MLX4_CQE_IS_SEND_MASK = 0x40,
68 MLX4_CQE_OPCODE_MASK = 0x1f
72 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
73 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
74 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
75 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
76 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
77 MLX4_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
78 MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
79 MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
80 MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
81 MLX4_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
82 MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
83 MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
84 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
89 uint32_t reserved1[5];
94 uint8_t owner_sr_opcode;
97 static struct mlx4_cqe *get_cqe(struct mlx4_cq *cq, int entry)
99 return cq->buf.buf + entry * cq->cqe_size;
102 static void *get_sw_cqe(struct mlx4_cq *cq, int n)
104 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibv_cq.cqe);
105 struct mlx4_cqe *tcqe = cq->cqe_size == 64 ? cqe + 1 : cqe;
107 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
108 !!(n & (cq->ibv_cq.cqe + 1))) ? NULL : cqe;
111 static struct mlx4_cqe *next_cqe_sw(struct mlx4_cq *cq)
113 return get_sw_cqe(cq, cq->cons_index);
116 static enum ibv_wc_status mlx4_handle_error_cqe(struct mlx4_err_cqe *cqe)
118 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR)
119 printf(PFX "local QP operation err "
120 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
122 htobe32(cqe->vlan_my_qpn), htobe32(cqe->wqe_index),
124 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
126 switch (cqe->syndrome) {
127 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
128 return IBV_WC_LOC_LEN_ERR;
129 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
130 return IBV_WC_LOC_QP_OP_ERR;
131 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
132 return IBV_WC_LOC_PROT_ERR;
133 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
134 return IBV_WC_WR_FLUSH_ERR;
135 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
136 return IBV_WC_MW_BIND_ERR;
137 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
138 return IBV_WC_BAD_RESP_ERR;
139 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
140 return IBV_WC_LOC_ACCESS_ERR;
141 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
142 return IBV_WC_REM_INV_REQ_ERR;
143 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
144 return IBV_WC_REM_ACCESS_ERR;
145 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
146 return IBV_WC_REM_OP_ERR;
147 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
148 return IBV_WC_RETRY_EXC_ERR;
149 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
150 return IBV_WC_RNR_RETRY_EXC_ERR;
151 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
152 return IBV_WC_REM_ABORT_ERR;
154 return IBV_WC_GENERAL_ERR;
158 static inline void handle_good_req(struct ibv_wc *wc, struct mlx4_cqe *cqe)
161 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
162 case MLX4_OPCODE_RDMA_WRITE_IMM:
163 wc->wc_flags |= IBV_WC_WITH_IMM;
165 case MLX4_OPCODE_RDMA_WRITE:
166 wc->opcode = IBV_WC_RDMA_WRITE;
168 case MLX4_OPCODE_SEND_IMM:
169 wc->wc_flags |= IBV_WC_WITH_IMM;
171 case MLX4_OPCODE_SEND:
172 case MLX4_OPCODE_SEND_INVAL:
173 wc->opcode = IBV_WC_SEND;
175 case MLX4_OPCODE_RDMA_READ:
176 wc->opcode = IBV_WC_RDMA_READ;
177 wc->byte_len = be32toh(cqe->byte_cnt);
179 case MLX4_OPCODE_ATOMIC_CS:
180 wc->opcode = IBV_WC_COMP_SWAP;
183 case MLX4_OPCODE_ATOMIC_FA:
184 wc->opcode = IBV_WC_FETCH_ADD;
187 case MLX4_OPCODE_LOCAL_INVAL:
188 wc->opcode = IBV_WC_LOCAL_INV;
190 case MLX4_OPCODE_BIND_MW:
191 wc->opcode = IBV_WC_BIND_MW;
194 /* assume it's a send completion */
195 wc->opcode = IBV_WC_SEND;
200 static inline int mlx4_get_next_cqe(struct mlx4_cq *cq,
201 struct mlx4_cqe **pcqe)
203 static inline int mlx4_get_next_cqe(struct mlx4_cq *cq,
204 struct mlx4_cqe **pcqe)
206 struct mlx4_cqe *cqe;
208 cqe = next_cqe_sw(cq);
212 if (cq->cqe_size == 64)
217 VALGRIND_MAKE_MEM_DEFINED(cqe, sizeof *cqe);
220 * Make sure we read CQ entry contents after we've checked the
223 udma_from_device_barrier();
230 static inline int mlx4_parse_cqe(struct mlx4_cq *cq,
231 struct mlx4_cqe *cqe,
232 struct mlx4_qp **cur_qp,
233 struct ibv_wc *wc, int lazy)
235 static inline int mlx4_parse_cqe(struct mlx4_cq *cq,
236 struct mlx4_cqe *cqe,
237 struct mlx4_qp **cur_qp,
238 struct ibv_wc *wc, int lazy)
241 struct mlx4_srq *srq;
243 uint32_t g_mlpath_rqpn;
246 struct mlx4_err_cqe *ecqe;
247 struct mlx4_context *mctx;
250 enum ibv_wc_status *pstatus;
252 mctx = to_mctx(cq->ibv_cq.context);
253 qpn = be32toh(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK;
256 cq->flags &= (~MLX4_CQ_FLAGS_RX_CSUM_VALID);
260 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
261 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
262 MLX4_CQE_OPCODE_ERROR;
264 if ((qpn & MLX4_XRC_QPN_BIT) && !is_send) {
266 * We do not have to take the XSRQ table lock here,
267 * because CQs will be locked while SRQs are removed
270 srq = mlx4_find_xsrq(&mctx->xsrq_table,
271 be32toh(cqe->g_mlpath_rqpn) & MLX4_CQE_QPN_MASK);
275 if (!*cur_qp || (qpn != (*cur_qp)->verbs_qp.qp.qp_num)) {
277 * We do not have to take the QP table lock here,
278 * because CQs will be locked while QPs are removed
281 *cur_qp = mlx4_find_qp(mctx, qpn);
285 srq = ((*cur_qp)->verbs_qp.qp.srq) ? to_msrq((*cur_qp)->verbs_qp.qp.srq) : NULL;
288 pwr_id = lazy ? &cq->ibv_cq.wr_id : &wc->wr_id;
291 wqe_index = be16toh(cqe->wqe_index);
292 wq->tail += (uint16_t) (wqe_index - (uint16_t) wq->tail);
293 *pwr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
296 wqe_index = be16toh(cqe->wqe_index);
297 *pwr_id = srq->wrid[wqe_index];
298 mlx4_free_srq_wqe(srq, wqe_index);
301 *pwr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
305 pstatus = lazy ? &cq->ibv_cq.status : &wc->status;
307 ecqe = (struct mlx4_err_cqe *)cqe;
308 *pstatus = mlx4_handle_error_cqe(ecqe);
310 wc->vendor_err = ecqe->vendor_err;
314 *pstatus = IBV_WC_SUCCESS;
317 if ((*cur_qp) && ((*cur_qp)->qp_cap_cache & MLX4_RX_CSUM_VALID))
318 cq->flags |= MLX4_CQ_FLAGS_RX_CSUM_VALID;
319 } else if (is_send) {
320 handle_good_req(wc, cqe);
322 wc->byte_len = be32toh(cqe->byte_cnt);
324 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
325 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
326 wc->opcode = IBV_WC_RECV_RDMA_WITH_IMM;
327 wc->wc_flags = IBV_WC_WITH_IMM;
328 wc->imm_data = cqe->immed_rss_invalid;
330 case MLX4_RECV_OPCODE_SEND_INVAL:
331 wc->opcode = IBV_WC_RECV;
332 wc->wc_flags |= IBV_WC_WITH_INV;
333 wc->imm_data = be32toh(cqe->immed_rss_invalid);
335 case MLX4_RECV_OPCODE_SEND:
336 wc->opcode = IBV_WC_RECV;
339 case MLX4_RECV_OPCODE_SEND_IMM:
340 wc->opcode = IBV_WC_RECV;
341 wc->wc_flags = IBV_WC_WITH_IMM;
342 wc->imm_data = cqe->immed_rss_invalid;
346 wc->slid = be16toh(cqe->rlid);
347 g_mlpath_rqpn = be32toh(cqe->g_mlpath_rqpn);
348 wc->src_qp = g_mlpath_rqpn & 0xffffff;
349 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
350 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IBV_WC_GRH : 0;
351 wc->pkey_index = be32toh(cqe->immed_rss_invalid) & 0x7f;
352 /* When working with xrc srqs, don't have qp to check link layer.
353 * Using IB SL, should consider Roce. (TBD)
355 if ((*cur_qp) && (*cur_qp)->link_layer == IBV_LINK_LAYER_ETHERNET)
356 wc->sl = be16toh(cqe->sl_vid) >> 13;
358 wc->sl = be16toh(cqe->sl_vid) >> 12;
360 if ((*cur_qp) && ((*cur_qp)->qp_cap_cache & MLX4_RX_CSUM_VALID)) {
361 wc->wc_flags |= ((cqe->status & htobe32(MLX4_CQE_STATUS_IPV4_CSUM_OK)) ==
362 htobe32(MLX4_CQE_STATUS_IPV4_CSUM_OK)) <<
363 IBV_WC_IP_CSUM_OK_SHIFT;
370 static inline int mlx4_parse_lazy_cqe(struct mlx4_cq *cq,
371 struct mlx4_cqe *cqe)
373 static inline int mlx4_parse_lazy_cqe(struct mlx4_cq *cq,
374 struct mlx4_cqe *cqe)
376 return mlx4_parse_cqe(cq, cqe, &cq->cur_qp, NULL, 1);
379 static inline int mlx4_poll_one(struct mlx4_cq *cq,
380 struct mlx4_qp **cur_qp,
383 static inline int mlx4_poll_one(struct mlx4_cq *cq,
384 struct mlx4_qp **cur_qp,
387 struct mlx4_cqe *cqe;
390 err = mlx4_get_next_cqe(cq, &cqe);
394 return mlx4_parse_cqe(cq, cqe, cur_qp, wc, 0);
397 int mlx4_poll_cq(struct ibv_cq *ibcq, int ne, struct ibv_wc *wc)
399 struct mlx4_cq *cq = to_mcq(ibcq);
400 struct mlx4_qp *qp = NULL;
404 pthread_spin_lock(&cq->lock);
406 for (npolled = 0; npolled < ne; ++npolled) {
407 err = mlx4_poll_one(cq, &qp, wc + npolled);
412 if (npolled || err == CQ_POLL_ERR)
413 mlx4_update_cons_index(cq);
415 pthread_spin_unlock(&cq->lock);
417 return err == CQ_POLL_ERR ? err : npolled;
420 static inline void _mlx4_end_poll(struct ibv_cq_ex *ibcq, int lock)
422 static inline void _mlx4_end_poll(struct ibv_cq_ex *ibcq, int lock)
424 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
426 mlx4_update_cons_index(cq);
429 pthread_spin_unlock(&cq->lock);
432 static inline int _mlx4_start_poll(struct ibv_cq_ex *ibcq,
433 struct ibv_poll_cq_attr *attr,
436 static inline int _mlx4_start_poll(struct ibv_cq_ex *ibcq,
437 struct ibv_poll_cq_attr *attr,
440 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
441 struct mlx4_cqe *cqe;
444 if (unlikely(attr->comp_mask))
448 pthread_spin_lock(&cq->lock);
452 err = mlx4_get_next_cqe(cq, &cqe);
453 if (err == CQ_EMPTY) {
455 pthread_spin_unlock(&cq->lock);
459 err = mlx4_parse_lazy_cqe(cq, cqe);
461 pthread_spin_unlock(&cq->lock);
466 static int mlx4_next_poll(struct ibv_cq_ex *ibcq)
468 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
469 struct mlx4_cqe *cqe;
472 err = mlx4_get_next_cqe(cq, &cqe);
476 return mlx4_parse_lazy_cqe(cq, cqe);
479 static void mlx4_end_poll(struct ibv_cq_ex *ibcq)
481 _mlx4_end_poll(ibcq, 0);
484 static void mlx4_end_poll_lock(struct ibv_cq_ex *ibcq)
486 _mlx4_end_poll(ibcq, 1);
489 static int mlx4_start_poll(struct ibv_cq_ex *ibcq,
490 struct ibv_poll_cq_attr *attr)
492 return _mlx4_start_poll(ibcq, attr, 0);
495 static int mlx4_start_poll_lock(struct ibv_cq_ex *ibcq,
496 struct ibv_poll_cq_attr *attr)
498 return _mlx4_start_poll(ibcq, attr, 1);
501 static enum ibv_wc_opcode mlx4_cq_read_wc_opcode(struct ibv_cq_ex *ibcq)
503 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
505 if (cq->cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK) {
506 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
507 case MLX4_OPCODE_RDMA_WRITE_IMM:
508 case MLX4_OPCODE_RDMA_WRITE:
509 return IBV_WC_RDMA_WRITE;
510 case MLX4_OPCODE_SEND_INVAL:
511 case MLX4_OPCODE_SEND_IMM:
512 case MLX4_OPCODE_SEND:
514 case MLX4_OPCODE_RDMA_READ:
515 return IBV_WC_RDMA_READ;
516 case MLX4_OPCODE_ATOMIC_CS:
517 return IBV_WC_COMP_SWAP;
518 case MLX4_OPCODE_ATOMIC_FA:
519 return IBV_WC_FETCH_ADD;
520 case MLX4_OPCODE_LOCAL_INVAL:
521 return IBV_WC_LOCAL_INV;
522 case MLX4_OPCODE_BIND_MW:
523 return IBV_WC_BIND_MW;
526 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
527 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
528 return IBV_WC_RECV_RDMA_WITH_IMM;
529 case MLX4_RECV_OPCODE_SEND_INVAL:
530 case MLX4_RECV_OPCODE_SEND_IMM:
531 case MLX4_RECV_OPCODE_SEND:
539 static uint32_t mlx4_cq_read_wc_qp_num(struct ibv_cq_ex *ibcq)
541 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
543 return be32toh(cq->cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK;
546 static int mlx4_cq_read_wc_flags(struct ibv_cq_ex *ibcq)
548 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
549 int is_send = cq->cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
553 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
554 case MLX4_OPCODE_RDMA_WRITE_IMM:
555 case MLX4_OPCODE_SEND_IMM:
556 wc_flags |= IBV_WC_WITH_IMM;
560 if (cq->flags & MLX4_CQ_FLAGS_RX_CSUM_VALID)
561 wc_flags |= ((cq->cqe->status &
562 htobe32(MLX4_CQE_STATUS_IPV4_CSUM_OK)) ==
563 htobe32(MLX4_CQE_STATUS_IPV4_CSUM_OK)) <<
564 IBV_WC_IP_CSUM_OK_SHIFT;
566 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
567 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
568 case MLX4_RECV_OPCODE_SEND_IMM:
569 wc_flags |= IBV_WC_WITH_IMM;
571 case MLX4_RECV_OPCODE_SEND_INVAL:
572 wc_flags |= IBV_WC_WITH_INV;
575 wc_flags |= (be32toh(cq->cqe->g_mlpath_rqpn) & 0x80000000) ? IBV_WC_GRH : 0;
581 static uint32_t mlx4_cq_read_wc_byte_len(struct ibv_cq_ex *ibcq)
583 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
585 return be32toh(cq->cqe->byte_cnt);
588 static uint32_t mlx4_cq_read_wc_vendor_err(struct ibv_cq_ex *ibcq)
590 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
591 struct mlx4_err_cqe *ecqe = (struct mlx4_err_cqe *)cq->cqe;
593 return ecqe->vendor_err;
596 static uint32_t mlx4_cq_read_wc_imm_data(struct ibv_cq_ex *ibcq)
598 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
600 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
601 case MLX4_RECV_OPCODE_SEND_INVAL:
602 return be32toh(cq->cqe->immed_rss_invalid);
604 return cq->cqe->immed_rss_invalid;
608 static uint32_t mlx4_cq_read_wc_slid(struct ibv_cq_ex *ibcq)
610 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
612 return (uint32_t)be16toh(cq->cqe->rlid);
615 static uint8_t mlx4_cq_read_wc_sl(struct ibv_cq_ex *ibcq)
617 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
619 if ((cq->cur_qp) && (cq->cur_qp->link_layer == IBV_LINK_LAYER_ETHERNET))
620 return be16toh(cq->cqe->sl_vid) >> 13;
622 return be16toh(cq->cqe->sl_vid) >> 12;
625 static uint32_t mlx4_cq_read_wc_src_qp(struct ibv_cq_ex *ibcq)
627 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
629 return be32toh(cq->cqe->g_mlpath_rqpn) & 0xffffff;
632 static uint8_t mlx4_cq_read_wc_dlid_path_bits(struct ibv_cq_ex *ibcq)
634 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
636 return (be32toh(cq->cqe->g_mlpath_rqpn) >> 24) & 0x7f;
639 static uint64_t mlx4_cq_read_wc_completion_ts(struct ibv_cq_ex *ibcq)
641 struct mlx4_cq *cq = to_mcq(ibv_cq_ex_to_cq(ibcq));
643 return ((uint64_t)be32toh(cq->cqe->ts_47_16) << 16) |
644 (cq->cqe->ts_15_8 << 8) |
648 void mlx4_cq_fill_pfns(struct mlx4_cq *cq, const struct ibv_cq_init_attr_ex *cq_attr)
651 if (cq->flags & MLX4_CQ_FLAGS_SINGLE_THREADED) {
652 cq->ibv_cq.start_poll = mlx4_start_poll;
653 cq->ibv_cq.end_poll = mlx4_end_poll;
655 cq->ibv_cq.start_poll = mlx4_start_poll_lock;
656 cq->ibv_cq.end_poll = mlx4_end_poll_lock;
658 cq->ibv_cq.next_poll = mlx4_next_poll;
660 cq->ibv_cq.read_opcode = mlx4_cq_read_wc_opcode;
661 cq->ibv_cq.read_vendor_err = mlx4_cq_read_wc_vendor_err;
662 cq->ibv_cq.read_wc_flags = mlx4_cq_read_wc_flags;
663 if (cq_attr->wc_flags & IBV_WC_EX_WITH_BYTE_LEN)
664 cq->ibv_cq.read_byte_len = mlx4_cq_read_wc_byte_len;
665 if (cq_attr->wc_flags & IBV_WC_EX_WITH_IMM)
666 cq->ibv_cq.read_imm_data = mlx4_cq_read_wc_imm_data;
667 if (cq_attr->wc_flags & IBV_WC_EX_WITH_QP_NUM)
668 cq->ibv_cq.read_qp_num = mlx4_cq_read_wc_qp_num;
669 if (cq_attr->wc_flags & IBV_WC_EX_WITH_SRC_QP)
670 cq->ibv_cq.read_src_qp = mlx4_cq_read_wc_src_qp;
671 if (cq_attr->wc_flags & IBV_WC_EX_WITH_SLID)
672 cq->ibv_cq.read_slid = mlx4_cq_read_wc_slid;
673 if (cq_attr->wc_flags & IBV_WC_EX_WITH_SL)
674 cq->ibv_cq.read_sl = mlx4_cq_read_wc_sl;
675 if (cq_attr->wc_flags & IBV_WC_EX_WITH_DLID_PATH_BITS)
676 cq->ibv_cq.read_dlid_path_bits = mlx4_cq_read_wc_dlid_path_bits;
677 if (cq_attr->wc_flags & IBV_WC_EX_WITH_COMPLETION_TIMESTAMP)
678 cq->ibv_cq.read_completion_ts = mlx4_cq_read_wc_completion_ts;
681 int mlx4_arm_cq(struct ibv_cq *ibvcq, int solicited)
683 struct mlx4_cq *cq = to_mcq(ibvcq);
684 uint32_t doorbell[2];
690 ci = cq->cons_index & 0xffffff;
691 cmd = solicited ? MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT;
693 *cq->arm_db = htobe32(sn << 28 | cmd | ci);
696 * Make sure that the doorbell record in host memory is
697 * written before ringing the doorbell via PCI MMIO.
699 udma_to_device_barrier();
701 doorbell[0] = htobe32(sn << 28 | cmd | cq->cqn);
702 doorbell[1] = htobe32(ci);
704 mlx4_write64(doorbell, to_mctx(ibvcq->context), MLX4_CQ_DOORBELL);
709 void mlx4_cq_event(struct ibv_cq *cq)
711 to_mcq(cq)->arm_sn++;
714 void __mlx4_cq_clean(struct mlx4_cq *cq, uint32_t qpn, struct mlx4_srq *srq)
716 struct mlx4_cqe *cqe, *dest;
720 int cqe_inc = cq->cqe_size == 64 ? 1 : 0;
723 * First we need to find the current producer index, so we
724 * know where to start cleaning from. It doesn't matter if HW
725 * adds new entries after this loop -- the QP we're worried
726 * about is already in RESET, so the new entries won't come
727 * from our QP and therefore don't need to be checked.
729 for (prod_index = cq->cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
730 if (prod_index == cq->cons_index + cq->ibv_cq.cqe)
734 * Now sweep backwards through the CQ, removing CQ entries
735 * that match our QP by copying older entries on top of them.
737 while ((int) --prod_index - (int) cq->cons_index >= 0) {
738 cqe = get_cqe(cq, prod_index & cq->ibv_cq.cqe);
740 if (srq && srq->ext_srq &&
741 (be32toh(cqe->g_mlpath_rqpn) & MLX4_CQE_QPN_MASK) == srq->verbs_srq.srq_num &&
742 !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) {
743 mlx4_free_srq_wqe(srq, be16toh(cqe->wqe_index));
745 } else if ((be32toh(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
746 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
747 mlx4_free_srq_wqe(srq, be16toh(cqe->wqe_index));
750 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibv_cq.cqe);
752 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
753 memcpy(dest, cqe, sizeof *cqe);
754 dest->owner_sr_opcode = owner_bit |
755 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
760 cq->cons_index += nfreed;
762 * Make sure update of buffer contents is done before
763 * updating consumer index.
765 udma_to_device_barrier();
766 mlx4_update_cons_index(cq);
770 void mlx4_cq_clean(struct mlx4_cq *cq, uint32_t qpn, struct mlx4_srq *srq)
772 pthread_spin_lock(&cq->lock);
773 __mlx4_cq_clean(cq, qpn, srq);
774 pthread_spin_unlock(&cq->lock);
777 int mlx4_get_outstanding_cqes(struct mlx4_cq *cq)
781 for (i = cq->cons_index; get_sw_cqe(cq, i); ++i)
784 return i - cq->cons_index;
787 void mlx4_cq_resize_copy_cqes(struct mlx4_cq *cq, void *buf, int old_cqe)
789 struct mlx4_cqe *cqe;
791 int cqe_inc = cq->cqe_size == 64 ? 1 : 0;
794 cqe = get_cqe(cq, (i & old_cqe));
797 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
798 cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
799 (((i + 1) & (cq->ibv_cq.cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
800 memcpy(buf + ((i + 1) & cq->ibv_cq.cqe) * cq->cqe_size,
801 cqe - cqe_inc, cq->cqe_size);
803 cqe = get_cqe(cq, (i & old_cqe));
810 int mlx4_alloc_cq_buf(struct mlx4_device *dev, struct mlx4_buf *buf, int nent,
813 if (mlx4_alloc_buf(buf, align(nent * entry_size, dev->page_size),
816 memset(buf->buf, 0, nent * entry_size);