2 * Copyright (c) 2007 Cisco, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <infiniband/endian.h>
46 int mlx4_query_device(struct ibv_context *context, struct ibv_device_attr *attr)
48 struct ibv_query_device cmd;
50 unsigned major, minor, sub_minor;
53 ret = ibv_cmd_query_device(context, attr, &raw_fw_ver, &cmd, sizeof cmd);
57 major = (raw_fw_ver >> 32) & 0xffff;
58 minor = (raw_fw_ver >> 16) & 0xffff;
59 sub_minor = raw_fw_ver & 0xffff;
61 snprintf(attr->fw_ver, sizeof attr->fw_ver,
62 "%d.%d.%03d", major, minor, sub_minor);
67 int mlx4_query_device_ex(struct ibv_context *context,
68 const struct ibv_query_device_ex_input *input,
69 struct ibv_device_attr_ex *attr,
72 struct mlx4_context *mctx = to_mctx(context);
73 struct mlx4_query_device_ex_resp resp = {};
74 struct mlx4_query_device_ex cmd = {};
81 err = ibv_cmd_query_device_ex(context, input, attr, attr_size,
83 &cmd.ibv_cmd, sizeof(cmd.ibv_cmd), sizeof(cmd),
84 &resp.ibv_resp, sizeof(resp.ibv_resp),
89 if (resp.comp_mask & MLX4_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET) {
90 mctx->core_clock.offset = resp.hca_core_clock_offset;
91 mctx->core_clock.offset_valid = 1;
94 major = (raw_fw_ver >> 32) & 0xffff;
95 minor = (raw_fw_ver >> 16) & 0xffff;
96 sub_minor = raw_fw_ver & 0xffff;
98 snprintf(attr->orig_attr.fw_ver, sizeof attr->orig_attr.fw_ver,
99 "%d.%d.%03d", major, minor, sub_minor);
104 #define READL(ptr) (*((uint32_t *)(ptr)))
105 static int mlx4_read_clock(struct ibv_context *context, uint64_t *cycles)
107 unsigned int clockhi, clocklo, clockhi1;
109 struct mlx4_context *ctx = to_mctx(context);
111 if (!ctx->hca_core_clock)
114 /* Handle wraparound */
115 for (i = 0; i < 2; i++) {
116 clockhi = be32toh(READL(ctx->hca_core_clock));
117 clocklo = be32toh(READL(ctx->hca_core_clock + 4));
118 clockhi1 = be32toh(READL(ctx->hca_core_clock));
119 if (clockhi == clockhi1)
123 *cycles = (uint64_t)clockhi << 32 | (uint64_t)clocklo;
128 int mlx4_query_rt_values(struct ibv_context *context,
129 struct ibv_values_ex *values)
131 uint32_t comp_mask = 0;
134 if (values->comp_mask & IBV_VALUES_MASK_RAW_CLOCK) {
137 err = mlx4_read_clock(context, &cycles);
139 values->raw_clock.tv_sec = 0;
140 values->raw_clock.tv_nsec = cycles;
141 comp_mask |= IBV_VALUES_MASK_RAW_CLOCK;
145 values->comp_mask = comp_mask;
150 int mlx4_query_port(struct ibv_context *context, uint8_t port,
151 struct ibv_port_attr *attr)
153 struct ibv_query_port cmd;
156 err = ibv_cmd_query_port(context, port, attr, &cmd, sizeof(cmd));
157 if (!err && port <= MLX4_PORTS_NUM && port > 0) {
158 struct mlx4_context *mctx = to_mctx(context);
159 if (!mctx->port_query_cache[port - 1].valid) {
160 mctx->port_query_cache[port - 1].link_layer =
162 mctx->port_query_cache[port - 1].caps =
163 attr->port_cap_flags;
164 mctx->port_query_cache[port - 1].valid = 1;
171 /* Only the fields in the port cache will be valid */
172 static int query_port_cache(struct ibv_context *context, uint8_t port_num,
173 struct ibv_port_attr *port_attr)
175 struct mlx4_context *mctx = to_mctx(context);
176 if (port_num <= 0 || port_num > MLX4_PORTS_NUM)
178 if (mctx->port_query_cache[port_num - 1].valid) {
179 port_attr->link_layer =
181 port_query_cache[port_num - 1].
183 port_attr->port_cap_flags =
185 port_query_cache[port_num - 1].
189 return mlx4_query_port(context, port_num,
190 (struct ibv_port_attr *)port_attr);
194 struct ibv_pd *mlx4_alloc_pd(struct ibv_context *context)
196 struct ibv_alloc_pd cmd;
197 struct mlx4_alloc_pd_resp resp;
200 pd = malloc(sizeof *pd);
204 if (ibv_cmd_alloc_pd(context, &pd->ibv_pd, &cmd, sizeof cmd,
205 &resp.ibv_resp, sizeof resp)) {
215 int mlx4_free_pd(struct ibv_pd *pd)
219 ret = ibv_cmd_dealloc_pd(pd);
227 struct ibv_xrcd *mlx4_open_xrcd(struct ibv_context *context,
228 struct ibv_xrcd_init_attr *attr)
230 struct ibv_open_xrcd cmd;
231 struct ibv_open_xrcd_resp resp;
232 struct verbs_xrcd *xrcd;
235 xrcd = calloc(1, sizeof *xrcd);
239 ret = ibv_cmd_open_xrcd(context, xrcd, sizeof(*xrcd), attr,
240 &cmd, sizeof cmd, &resp, sizeof resp);
251 int mlx4_close_xrcd(struct ibv_xrcd *ib_xrcd)
253 struct verbs_xrcd *xrcd = container_of(ib_xrcd, struct verbs_xrcd, xrcd);
256 ret = ibv_cmd_close_xrcd(xrcd);
263 struct ibv_mr *mlx4_reg_mr(struct ibv_pd *pd, void *addr, size_t length,
267 struct ibv_reg_mr cmd;
268 struct ibv_reg_mr_resp resp;
271 mr = malloc(sizeof *mr);
275 ret = ibv_cmd_reg_mr(pd, addr, length, (uintptr_t) addr,
276 access, mr, &cmd, sizeof cmd,
286 int mlx4_rereg_mr(struct ibv_mr *mr,
288 struct ibv_pd *pd, void *addr,
289 size_t length, int access)
291 struct ibv_rereg_mr cmd;
292 struct ibv_rereg_mr_resp resp;
294 if (flags & IBV_REREG_MR_KEEP_VALID)
297 return ibv_cmd_rereg_mr(mr, flags, addr, length,
301 &resp, sizeof(resp));
304 int mlx4_dereg_mr(struct ibv_mr *mr)
308 ret = ibv_cmd_dereg_mr(mr);
316 struct ibv_mw *mlx4_alloc_mw(struct ibv_pd *pd, enum ibv_mw_type type)
319 struct ibv_alloc_mw cmd;
320 struct ibv_alloc_mw_resp resp;
323 mw = calloc(1, sizeof(*mw));
327 ret = ibv_cmd_alloc_mw(pd, type, mw, &cmd, sizeof(cmd),
328 &resp, sizeof(resp));
338 int mlx4_dealloc_mw(struct ibv_mw *mw)
341 struct ibv_dealloc_mw cmd;
343 ret = ibv_cmd_dealloc_mw(mw, &cmd, sizeof(cmd));
351 int mlx4_bind_mw(struct ibv_qp *qp, struct ibv_mw *mw,
352 struct ibv_mw_bind *mw_bind)
354 struct ibv_send_wr *bad_wr = NULL;
355 struct ibv_send_wr wr = { };
359 wr.opcode = IBV_WR_BIND_MW;
362 wr.wr_id = mw_bind->wr_id;
363 wr.send_flags = mw_bind->send_flags;
366 wr.bind_mw.rkey = ibv_inc_rkey(mw->rkey);
367 wr.bind_mw.bind_info = mw_bind->bind_info;
369 ret = mlx4_post_send(qp, &wr, &bad_wr);
374 /* updating the mw with the latest rkey. */
375 mw->rkey = wr.bind_mw.rkey;
380 int align_queue_size(int req)
384 for (nent = 1; nent < req; nent <<= 1)
391 CREATE_CQ_SUPPORTED_WC_FLAGS = IBV_WC_STANDARD_FLAGS |
392 IBV_WC_EX_WITH_COMPLETION_TIMESTAMP
396 CREATE_CQ_SUPPORTED_COMP_MASK = IBV_CQ_INIT_ATTR_MASK_FLAGS
400 CREATE_CQ_SUPPORTED_FLAGS = IBV_CREATE_CQ_ATTR_SINGLE_THREADED
404 static int mlx4_cmd_create_cq(struct ibv_context *context,
405 struct ibv_cq_init_attr_ex *cq_attr,
408 struct mlx4_create_cq cmd = {};
409 struct mlx4_create_cq_resp resp = {};
412 cmd.buf_addr = (uintptr_t) cq->buf.buf;
413 cmd.db_addr = (uintptr_t) cq->set_ci_db;
415 ret = ibv_cmd_create_cq(context, cq_attr->cqe, cq_attr->channel,
416 cq_attr->comp_vector,
417 ibv_cq_ex_to_cq(&cq->ibv_cq),
418 &cmd.ibv_cmd, sizeof(cmd),
419 &resp.ibv_resp, sizeof(resp));
427 static int mlx4_cmd_create_cq_ex(struct ibv_context *context,
428 struct ibv_cq_init_attr_ex *cq_attr,
431 struct mlx4_create_cq_ex cmd = {};
432 struct mlx4_create_cq_resp_ex resp = {};
435 cmd.buf_addr = (uintptr_t) cq->buf.buf;
436 cmd.db_addr = (uintptr_t) cq->set_ci_db;
438 ret = ibv_cmd_create_cq_ex(context, cq_attr,
439 &cq->ibv_cq, &cmd.ibv_cmd,
443 sizeof(resp.ibv_resp),
451 static struct ibv_cq_ex *create_cq(struct ibv_context *context,
452 struct ibv_cq_init_attr_ex *cq_attr,
457 struct mlx4_context *mctx = to_mctx(context);
459 /* Sanity check CQ size before proceeding */
460 if (cq_attr->cqe > 0x3fffff) {
465 if (cq_attr->comp_mask & ~CREATE_CQ_SUPPORTED_COMP_MASK) {
470 if (cq_attr->comp_mask & IBV_CQ_INIT_ATTR_MASK_FLAGS &&
471 cq_attr->flags & ~CREATE_CQ_SUPPORTED_FLAGS) {
476 if (cq_attr->wc_flags & ~CREATE_CQ_SUPPORTED_WC_FLAGS)
479 /* mlx4 devices don't support slid and sl in cqe when completion
480 * timestamp is enabled in the CQ
482 if ((cq_attr->wc_flags & (IBV_WC_EX_WITH_SLID | IBV_WC_EX_WITH_SL)) &&
483 (cq_attr->wc_flags & IBV_WC_EX_WITH_COMPLETION_TIMESTAMP)) {
488 cq = malloc(sizeof *cq);
494 if (pthread_spin_init(&cq->lock, PTHREAD_PROCESS_PRIVATE))
497 cq_attr->cqe = align_queue_size(cq_attr->cqe + 1);
499 if (mlx4_alloc_cq_buf(to_mdev(context->device), &cq->buf, cq_attr->cqe, mctx->cqe_size))
502 cq->cqe_size = mctx->cqe_size;
503 cq->set_ci_db = mlx4_alloc_db(to_mctx(context), MLX4_DB_TYPE_CQ);
507 cq->arm_db = cq->set_ci_db + 1;
511 cq->flags = cq_alloc_flags;
513 if (cq_attr->comp_mask & IBV_CQ_INIT_ATTR_MASK_FLAGS &&
514 cq_attr->flags & IBV_CREATE_CQ_ATTR_SINGLE_THREADED)
515 cq->flags |= MLX4_CQ_FLAGS_SINGLE_THREADED;
518 if (cq_alloc_flags & MLX4_CQ_FLAGS_EXTENDED)
519 ret = mlx4_cmd_create_cq_ex(context, cq_attr, cq);
521 ret = mlx4_cmd_create_cq(context, cq_attr, cq);
527 if (cq_alloc_flags & MLX4_CQ_FLAGS_EXTENDED)
528 mlx4_cq_fill_pfns(cq, cq_attr);
533 mlx4_free_db(to_mctx(context), MLX4_DB_TYPE_CQ, cq->set_ci_db);
536 mlx4_free_buf(&cq->buf);
544 struct ibv_cq *mlx4_create_cq(struct ibv_context *context, int cqe,
545 struct ibv_comp_channel *channel,
548 struct ibv_cq_ex *cq;
549 struct ibv_cq_init_attr_ex cq_attr = {.cqe = cqe, .channel = channel,
550 .comp_vector = comp_vector,
551 .wc_flags = IBV_WC_STANDARD_FLAGS};
553 cq = create_cq(context, &cq_attr, 0);
554 return cq ? ibv_cq_ex_to_cq(cq) : NULL;
557 struct ibv_cq_ex *mlx4_create_cq_ex(struct ibv_context *context,
558 struct ibv_cq_init_attr_ex *cq_attr)
561 * Make local copy since some attributes might be adjusted
564 struct ibv_cq_init_attr_ex cq_attr_c = {.cqe = cq_attr->cqe,
565 .channel = cq_attr->channel,
566 .comp_vector = cq_attr->comp_vector,
567 .wc_flags = cq_attr->wc_flags,
568 .comp_mask = cq_attr->comp_mask,
569 .flags = cq_attr->flags};
571 return create_cq(context, &cq_attr_c, MLX4_CQ_FLAGS_EXTENDED);
574 int mlx4_resize_cq(struct ibv_cq *ibcq, int cqe)
576 struct mlx4_cq *cq = to_mcq(ibcq);
577 struct mlx4_resize_cq cmd;
578 struct ibv_resize_cq_resp resp;
580 int old_cqe, outst_cqe, ret;
582 /* Sanity check CQ size before proceeding */
586 pthread_spin_lock(&cq->lock);
588 cqe = align_queue_size(cqe + 1);
589 if (cqe == ibcq->cqe + 1) {
594 /* Can't be smaller then the number of outstanding CQEs */
595 outst_cqe = mlx4_get_outstanding_cqes(cq);
596 if (cqe < outst_cqe + 1) {
601 ret = mlx4_alloc_cq_buf(to_mdev(ibcq->context->device), &buf, cqe, cq->cqe_size);
606 cmd.buf_addr = (uintptr_t) buf.buf;
608 ret = ibv_cmd_resize_cq(ibcq, cqe - 1, &cmd.ibv_cmd, sizeof cmd,
615 mlx4_cq_resize_copy_cqes(cq, buf.buf, old_cqe);
617 mlx4_free_buf(&cq->buf);
619 mlx4_update_cons_index(cq);
622 pthread_spin_unlock(&cq->lock);
626 int mlx4_destroy_cq(struct ibv_cq *cq)
630 ret = ibv_cmd_destroy_cq(cq);
634 mlx4_free_db(to_mctx(cq->context), MLX4_DB_TYPE_CQ, to_mcq(cq)->set_ci_db);
635 mlx4_free_buf(&to_mcq(cq)->buf);
641 struct ibv_srq *mlx4_create_srq(struct ibv_pd *pd,
642 struct ibv_srq_init_attr *attr)
644 struct mlx4_create_srq cmd;
645 struct mlx4_create_srq_resp resp;
646 struct mlx4_srq *srq;
649 /* Sanity check SRQ size before proceeding */
650 if (attr->attr.max_wr > 1 << 16 || attr->attr.max_sge > 64)
653 srq = malloc(sizeof *srq);
657 if (pthread_spin_init(&srq->lock, PTHREAD_PROCESS_PRIVATE))
660 srq->max = align_queue_size(attr->attr.max_wr + 1);
661 srq->max_gs = attr->attr.max_sge;
665 if (mlx4_alloc_srq_buf(pd, &attr->attr, srq))
668 srq->db = mlx4_alloc_db(to_mctx(pd->context), MLX4_DB_TYPE_RQ);
674 cmd.buf_addr = (uintptr_t) srq->buf.buf;
675 cmd.db_addr = (uintptr_t) srq->db;
677 ret = ibv_cmd_create_srq(pd, &srq->verbs_srq.srq, attr,
678 &cmd.ibv_cmd, sizeof cmd,
679 &resp.ibv_resp, sizeof resp);
683 return &srq->verbs_srq.srq;
686 mlx4_free_db(to_mctx(pd->context), MLX4_DB_TYPE_RQ, srq->db);
690 mlx4_free_buf(&srq->buf);
698 struct ibv_srq *mlx4_create_srq_ex(struct ibv_context *context,
699 struct ibv_srq_init_attr_ex *attr_ex)
701 if (!(attr_ex->comp_mask & IBV_SRQ_INIT_ATTR_TYPE) ||
702 (attr_ex->srq_type == IBV_SRQT_BASIC))
703 return mlx4_create_srq(attr_ex->pd, (struct ibv_srq_init_attr *) attr_ex);
704 else if (attr_ex->srq_type == IBV_SRQT_XRC)
705 return mlx4_create_xrc_srq(context, attr_ex);
710 int mlx4_modify_srq(struct ibv_srq *srq,
711 struct ibv_srq_attr *attr,
714 struct ibv_modify_srq cmd;
716 return ibv_cmd_modify_srq(srq, attr, attr_mask, &cmd, sizeof cmd);
719 int mlx4_query_srq(struct ibv_srq *srq,
720 struct ibv_srq_attr *attr)
722 struct ibv_query_srq cmd;
724 return ibv_cmd_query_srq(srq, attr, &cmd, sizeof cmd);
727 int mlx4_destroy_srq(struct ibv_srq *srq)
731 if (to_msrq(srq)->ext_srq)
732 return mlx4_destroy_xrc_srq(srq);
734 ret = ibv_cmd_destroy_srq(srq);
738 mlx4_free_db(to_mctx(srq->context), MLX4_DB_TYPE_RQ, to_msrq(srq)->db);
739 mlx4_free_buf(&to_msrq(srq)->buf);
740 free(to_msrq(srq)->wrid);
746 static int mlx4_cmd_create_qp_ex(struct ibv_context *context,
747 struct ibv_qp_init_attr_ex *attr,
748 struct mlx4_create_qp *cmd,
751 struct mlx4_create_qp_ex cmd_ex;
752 struct mlx4_create_qp_resp_ex resp;
755 memset(&cmd_ex, 0, sizeof(cmd_ex));
756 memcpy(&cmd_ex.ibv_cmd.base, &cmd->ibv_cmd.user_handle,
757 offsetof(typeof(cmd->ibv_cmd), is_srq) +
758 sizeof(cmd->ibv_cmd.is_srq) -
759 offsetof(typeof(cmd->ibv_cmd), user_handle));
761 memcpy(&cmd_ex.drv_ex, &cmd->buf_addr,
762 offsetof(typeof(*cmd), sq_no_prefetch) +
763 sizeof(cmd->sq_no_prefetch) - sizeof(cmd->ibv_cmd));
765 ret = ibv_cmd_create_qp_ex2(context, &qp->verbs_qp,
766 sizeof(qp->verbs_qp), attr,
767 &cmd_ex.ibv_cmd, sizeof(cmd_ex.ibv_cmd),
768 sizeof(cmd_ex), &resp.ibv_resp,
769 sizeof(resp.ibv_resp), sizeof(resp));
774 MLX4_CREATE_QP_SUP_COMP_MASK = (IBV_QP_INIT_ATTR_PD |
775 IBV_QP_INIT_ATTR_XRCD |
776 IBV_QP_INIT_ATTR_CREATE_FLAGS),
780 MLX4_CREATE_QP_EX2_COMP_MASK = (IBV_QP_INIT_ATTR_CREATE_FLAGS),
783 struct ibv_qp *mlx4_create_qp_ex(struct ibv_context *context,
784 struct ibv_qp_init_attr_ex *attr)
786 struct mlx4_context *ctx = to_mctx(context);
787 struct mlx4_create_qp cmd;
788 struct ibv_create_qp_resp resp;
792 /* Sanity check QP size before proceeding */
793 if (ctx->max_qp_wr) { /* mlx4_query_device succeeded */
794 if (attr->cap.max_send_wr > ctx->max_qp_wr ||
795 attr->cap.max_recv_wr > ctx->max_qp_wr ||
796 attr->cap.max_send_sge > ctx->max_sge ||
797 attr->cap.max_recv_sge > ctx->max_sge)
800 if (attr->cap.max_send_wr > 65536 ||
801 attr->cap.max_recv_wr > 65536 ||
802 attr->cap.max_send_sge > 64 ||
803 attr->cap.max_recv_sge > 64)
806 if (attr->cap.max_inline_data > 1024)
809 if (attr->comp_mask & ~MLX4_CREATE_QP_SUP_COMP_MASK)
812 qp = calloc(1, sizeof *qp);
816 if (attr->qp_type == IBV_QPT_XRC_RECV) {
817 attr->cap.max_send_wr = qp->sq.wqe_cnt = 0;
819 mlx4_calc_sq_wqe_size(&attr->cap, attr->qp_type, qp);
821 * We need to leave 2 KB + 1 WQE of headroom in the SQ to
822 * allow HW to prefetch.
824 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
825 qp->sq.wqe_cnt = align_queue_size(attr->cap.max_send_wr + qp->sq_spare_wqes);
828 if (attr->srq || attr->qp_type == IBV_QPT_XRC_SEND ||
829 attr->qp_type == IBV_QPT_XRC_RECV) {
830 attr->cap.max_recv_wr = qp->rq.wqe_cnt = attr->cap.max_recv_sge = 0;
832 qp->rq.wqe_cnt = align_queue_size(attr->cap.max_recv_wr);
833 if (attr->cap.max_recv_sge < 1)
834 attr->cap.max_recv_sge = 1;
835 if (attr->cap.max_recv_wr < 1)
836 attr->cap.max_recv_wr = 1;
839 if (mlx4_alloc_qp_buf(context, &attr->cap, attr->qp_type, qp))
842 mlx4_init_qp_indices(qp);
844 if (pthread_spin_init(&qp->sq.lock, PTHREAD_PROCESS_PRIVATE) ||
845 pthread_spin_init(&qp->rq.lock, PTHREAD_PROCESS_PRIVATE))
848 if (attr->cap.max_recv_sge) {
849 qp->db = mlx4_alloc_db(to_mctx(context), MLX4_DB_TYPE_RQ);
854 cmd.db_addr = (uintptr_t) qp->db;
859 cmd.buf_addr = (uintptr_t) qp->buf.buf;
860 cmd.log_sq_stride = qp->sq.wqe_shift;
861 for (cmd.log_sq_bb_count = 0;
862 qp->sq.wqe_cnt > 1 << cmd.log_sq_bb_count;
863 ++cmd.log_sq_bb_count)
865 cmd.sq_no_prefetch = 0; /* OK for ABI 2: just a reserved field */
866 memset(cmd.reserved, 0, sizeof cmd.reserved);
867 pthread_mutex_lock(&to_mctx(context)->qp_table_mutex);
869 if (attr->comp_mask & MLX4_CREATE_QP_EX2_COMP_MASK)
870 ret = mlx4_cmd_create_qp_ex(context, attr, &cmd, qp);
872 ret = ibv_cmd_create_qp_ex(context, &qp->verbs_qp,
873 sizeof(qp->verbs_qp), attr,
874 &cmd.ibv_cmd, sizeof(cmd), &resp,
879 if (qp->sq.wqe_cnt || qp->rq.wqe_cnt) {
880 ret = mlx4_store_qp(to_mctx(context), qp->verbs_qp.qp.qp_num, qp);
884 pthread_mutex_unlock(&to_mctx(context)->qp_table_mutex);
886 qp->rq.wqe_cnt = qp->rq.max_post = attr->cap.max_recv_wr;
887 qp->rq.max_gs = attr->cap.max_recv_sge;
888 if (attr->qp_type != IBV_QPT_XRC_RECV)
889 mlx4_set_sq_sizes(qp, &attr->cap, attr->qp_type);
891 qp->doorbell_qpn = htobe32(qp->verbs_qp.qp.qp_num << 8);
892 if (attr->sq_sig_all)
893 qp->sq_signal_bits = htobe32(MLX4_WQE_CTRL_CQ_UPDATE);
895 qp->sq_signal_bits = 0;
897 return &qp->verbs_qp.qp;
900 ibv_cmd_destroy_qp(&qp->verbs_qp.qp);
903 pthread_mutex_unlock(&to_mctx(context)->qp_table_mutex);
904 if (attr->cap.max_recv_sge)
905 mlx4_free_db(to_mctx(context), MLX4_DB_TYPE_RQ, qp->db);
911 mlx4_free_buf(&qp->buf);
919 struct ibv_qp *mlx4_create_qp(struct ibv_pd *pd, struct ibv_qp_init_attr *attr)
921 struct ibv_qp_init_attr_ex attr_ex;
924 memcpy(&attr_ex, attr, sizeof *attr);
925 attr_ex.comp_mask = IBV_QP_INIT_ATTR_PD;
927 qp = mlx4_create_qp_ex(pd->context, &attr_ex);
929 memcpy(attr, &attr_ex, sizeof *attr);
933 struct ibv_qp *mlx4_open_qp(struct ibv_context *context, struct ibv_qp_open_attr *attr)
935 struct ibv_open_qp cmd;
936 struct ibv_create_qp_resp resp;
940 qp = calloc(1, sizeof *qp);
944 ret = ibv_cmd_open_qp(context, &qp->verbs_qp, sizeof(qp->verbs_qp), attr,
945 &cmd, sizeof cmd, &resp, sizeof resp);
949 return &qp->verbs_qp.qp;
956 int mlx4_query_qp(struct ibv_qp *ibqp, struct ibv_qp_attr *attr,
958 struct ibv_qp_init_attr *init_attr)
960 struct ibv_query_qp cmd;
961 struct mlx4_qp *qp = to_mqp(ibqp);
964 ret = ibv_cmd_query_qp(ibqp, attr, attr_mask, init_attr, &cmd, sizeof cmd);
968 init_attr->cap.max_send_wr = qp->sq.max_post;
969 init_attr->cap.max_send_sge = qp->sq.max_gs;
970 init_attr->cap.max_inline_data = qp->max_inline_data;
972 attr->cap = init_attr->cap;
977 int mlx4_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr,
980 struct ibv_modify_qp cmd = {};
981 struct ibv_port_attr port_attr;
982 struct mlx4_qp *mqp = to_mqp(qp);
983 struct ibv_device_attr device_attr;
986 memset(&device_attr, 0, sizeof(device_attr));
987 if (attr_mask & IBV_QP_PORT) {
988 ret = ibv_query_port(qp->context, attr->port_num,
992 mqp->link_layer = port_attr.link_layer;
994 ret = ibv_query_device(qp->context, &device_attr);
998 switch(qp->qp_type) {
1000 if ((mqp->link_layer == IBV_LINK_LAYER_INFINIBAND) &&
1001 (device_attr.device_cap_flags & IBV_DEVICE_UD_IP_CSUM))
1002 mqp->qp_cap_cache |= MLX4_CSUM_SUPPORT_UD_OVER_IB |
1005 case IBV_QPT_RAW_PACKET:
1006 if ((mqp->link_layer == IBV_LINK_LAYER_ETHERNET) &&
1007 (device_attr.device_cap_flags & IBV_DEVICE_RAW_IP_CSUM))
1008 mqp->qp_cap_cache |= MLX4_CSUM_SUPPORT_RAW_OVER_ETH |
1017 if (qp->state == IBV_QPS_RESET &&
1018 attr_mask & IBV_QP_STATE &&
1019 attr->qp_state == IBV_QPS_INIT) {
1020 mlx4_qp_init_sq_ownership(to_mqp(qp));
1023 ret = ibv_cmd_modify_qp(qp, attr, attr_mask, &cmd, sizeof cmd);
1026 (attr_mask & IBV_QP_STATE) &&
1027 attr->qp_state == IBV_QPS_RESET) {
1029 mlx4_cq_clean(to_mcq(qp->recv_cq), qp->qp_num,
1030 qp->srq ? to_msrq(qp->srq) : NULL);
1031 if (qp->send_cq && qp->send_cq != qp->recv_cq)
1032 mlx4_cq_clean(to_mcq(qp->send_cq), qp->qp_num, NULL);
1034 mlx4_init_qp_indices(to_mqp(qp));
1035 if (to_mqp(qp)->rq.wqe_cnt)
1036 *to_mqp(qp)->db = 0;
1042 static void mlx4_lock_cqs(struct ibv_qp *qp)
1044 struct mlx4_cq *send_cq = to_mcq(qp->send_cq);
1045 struct mlx4_cq *recv_cq = to_mcq(qp->recv_cq);
1047 if (!qp->send_cq || !qp->recv_cq) {
1049 pthread_spin_lock(&send_cq->lock);
1050 else if (qp->recv_cq)
1051 pthread_spin_lock(&recv_cq->lock);
1052 } else if (send_cq == recv_cq) {
1053 pthread_spin_lock(&send_cq->lock);
1054 } else if (send_cq->cqn < recv_cq->cqn) {
1055 pthread_spin_lock(&send_cq->lock);
1056 pthread_spin_lock(&recv_cq->lock);
1058 pthread_spin_lock(&recv_cq->lock);
1059 pthread_spin_lock(&send_cq->lock);
1063 static void mlx4_unlock_cqs(struct ibv_qp *qp)
1065 struct mlx4_cq *send_cq = to_mcq(qp->send_cq);
1066 struct mlx4_cq *recv_cq = to_mcq(qp->recv_cq);
1069 if (!qp->send_cq || !qp->recv_cq) {
1071 pthread_spin_unlock(&send_cq->lock);
1072 else if (qp->recv_cq)
1073 pthread_spin_unlock(&recv_cq->lock);
1074 } else if (send_cq == recv_cq) {
1075 pthread_spin_unlock(&send_cq->lock);
1076 } else if (send_cq->cqn < recv_cq->cqn) {
1077 pthread_spin_unlock(&recv_cq->lock);
1078 pthread_spin_unlock(&send_cq->lock);
1080 pthread_spin_unlock(&send_cq->lock);
1081 pthread_spin_unlock(&recv_cq->lock);
1085 int mlx4_destroy_qp(struct ibv_qp *ibqp)
1087 struct mlx4_qp *qp = to_mqp(ibqp);
1090 pthread_mutex_lock(&to_mctx(ibqp->context)->qp_table_mutex);
1091 ret = ibv_cmd_destroy_qp(ibqp);
1093 pthread_mutex_unlock(&to_mctx(ibqp->context)->qp_table_mutex);
1097 mlx4_lock_cqs(ibqp);
1100 __mlx4_cq_clean(to_mcq(ibqp->recv_cq), ibqp->qp_num,
1101 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1102 if (ibqp->send_cq && ibqp->send_cq != ibqp->recv_cq)
1103 __mlx4_cq_clean(to_mcq(ibqp->send_cq), ibqp->qp_num, NULL);
1105 if (qp->sq.wqe_cnt || qp->rq.wqe_cnt)
1106 mlx4_clear_qp(to_mctx(ibqp->context), ibqp->qp_num);
1108 mlx4_unlock_cqs(ibqp);
1109 pthread_mutex_unlock(&to_mctx(ibqp->context)->qp_table_mutex);
1111 if (qp->rq.wqe_cnt) {
1112 mlx4_free_db(to_mctx(ibqp->context), MLX4_DB_TYPE_RQ, qp->db);
1117 mlx4_free_buf(&qp->buf);
1123 static int link_local_gid(const union ibv_gid *gid)
1125 uint32_t *tmp = (uint32_t *)gid->raw;
1126 uint32_t hi = tmp[0];
1127 uint32_t lo = tmp[1];
1129 if (hi == htobe32(0xfe800000) && lo == 0)
1135 static int is_multicast_gid(const union ibv_gid *gid)
1137 return gid->raw[0] == 0xff;
1140 static uint16_t get_vlan_id(union ibv_gid *gid)
1143 vid = gid->raw[11] << 8 | gid->raw[12];
1144 return vid < 0x1000 ? vid : 0xffff;
1147 static int mlx4_resolve_grh_to_l2(struct ibv_pd *pd, struct mlx4_ah *ah,
1148 struct ibv_ah_attr *attr)
1154 if (link_local_gid(&attr->grh.dgid)) {
1155 memcpy(ah->mac, &attr->grh.dgid.raw[8], 3);
1156 memcpy(ah->mac + 3, &attr->grh.dgid.raw[13], 3);
1159 vid = get_vlan_id(&attr->grh.dgid);
1160 } else if (is_multicast_gid(&attr->grh.dgid)) {
1163 for (i = 2; i < 6; ++i)
1164 ah->mac[i] = attr->grh.dgid.raw[i + 10];
1166 err = ibv_query_gid(pd->context, attr->port_num,
1167 attr->grh.sgid_index, &sgid);
1171 ah->av.dlid = htobe16(0xc000);
1172 ah->av.port_pd |= htobe32(1 << 31);
1174 vid = get_vlan_id(&sgid);
1178 if (vid != 0xffff) {
1179 ah->av.port_pd |= htobe32(1 << 29);
1180 ah->vlan = vid | ((attr->sl & 7) << 13);
1186 struct ibv_ah *mlx4_create_ah(struct ibv_pd *pd, struct ibv_ah_attr *attr)
1189 struct ibv_port_attr port_attr;
1191 if (query_port_cache(pd->context, attr->port_num, &port_attr))
1194 ah = malloc(sizeof *ah);
1198 memset(&ah->av, 0, sizeof ah->av);
1200 ah->av.port_pd = htobe32(to_mpd(pd)->pdn | (attr->port_num << 24));
1202 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1203 ah->av.g_slid = attr->src_path_bits;
1204 ah->av.dlid = htobe16(attr->dlid);
1205 ah->av.sl_tclass_flowlabel = htobe32(attr->sl << 28);
1207 ah->av.sl_tclass_flowlabel = htobe32(attr->sl << 29);
1209 if (attr->static_rate) {
1210 ah->av.stat_rate = attr->static_rate + MLX4_STAT_RATE_OFFSET;
1211 /* XXX check rate cap? */
1213 if (attr->is_global) {
1214 ah->av.g_slid |= 0x80;
1215 ah->av.gid_index = attr->grh.sgid_index;
1216 ah->av.hop_limit = attr->grh.hop_limit;
1217 ah->av.sl_tclass_flowlabel |=
1218 htobe32((attr->grh.traffic_class << 20) |
1219 attr->grh.flow_label);
1220 memcpy(ah->av.dgid, attr->grh.dgid.raw, 16);
1223 if (port_attr.link_layer == IBV_LINK_LAYER_ETHERNET) {
1224 if (port_attr.port_cap_flags & IBV_PORT_IP_BASED_GIDS) {
1227 if (ibv_resolve_eth_l2_from_gid(pd->context, attr,
1234 ah->av.port_pd |= htobe32(1 << 29);
1236 ((attr->sl & 7) << 13);
1240 if (mlx4_resolve_grh_to_l2(pd, ah, attr)) {
1250 int mlx4_destroy_ah(struct ibv_ah *ah)