contrib/ofed/libmlx5/mlx5-abi.h

   1 /*
   2  * Copyright (c) 2012 Mellanox Technologies, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_ABI_H
  34 #define MLX5_ABI_H
  35
  36 #include <infiniband/kern-abi.h>
  37 #include <infiniband/verbs.h>
  38 #include "mlx5dv.h"
  39
  40 #define MLX5_UVERBS_MIN_ABI_VERSION     1
  41 #define MLX5_UVERBS_MAX_ABI_VERSION     1
  42
  43 enum {
  44         MLX5_QP_FLAG_SIGNATURE          = 1 << 0,
  45         MLX5_QP_FLAG_SCATTER_CQE        = 1 << 1,
  46 };
  47
  48 enum {
  49         MLX5_RWQ_FLAG_SIGNATURE         = 1 << 0,
  50 };
  51
  52 enum {
  53         MLX5_NUM_NON_FP_BFREGS_PER_UAR  = 2,
  54         NUM_BFREGS_PER_UAR              = 4,
  55         MLX5_MAX_UARS                   = 1 << 8,
  56         MLX5_MAX_BFREGS                 = MLX5_MAX_UARS * MLX5_NUM_NON_FP_BFREGS_PER_UAR,
  57         MLX5_DEF_TOT_UUARS              = 8 * MLX5_NUM_NON_FP_BFREGS_PER_UAR,
  58         MLX5_MED_BFREGS_TSHOLD          = 12,
  59 };
  60
  61 enum mlx5_lib_caps {
  62         MLX5_LIB_CAP_4K_UAR             = 1 << 0,
  63 };
  64
  65 struct mlx5_alloc_ucontext {
  66         struct ibv_get_context          ibv_req;
  67         __u32                           total_num_uuars;
  68         __u32                           num_low_latency_uuars;
  69         __u32                           flags;
  70         __u32                           comp_mask;
  71         __u8                            cqe_version;
  72         __u8                            reserved0;
  73         __u16                           reserved1;
  74         __u32                           reserved2;
  75         __u64                           lib_caps;
  76 };
  77
  78 enum mlx5_ib_alloc_ucontext_resp_mask {
  79         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
  80 };
  81
  82 struct mlx5_alloc_ucontext_resp {
  83         struct ibv_get_context_resp     ibv_resp;
  84         __u32                           qp_tab_size;
  85         __u32                           bf_reg_size;
  86         __u32                           tot_uuars;
  87         __u32                           cache_line_size;
  88         __u16                           max_sq_desc_sz;
  89         __u16                           max_rq_desc_sz;
  90         __u32                           max_send_wqebb;
  91         __u32                           max_recv_wr;
  92         __u32                           max_srq_recv_wr;
  93         __u16                           num_ports;
  94         __u16                           reserved1;
  95         __u32                           comp_mask;
  96         __u32                           response_length;
  97         __u8                            cqe_version;
  98         __u8                            cmds_supp_uhw;
  99         __u16                           reserved2;
 100         __u64                           hca_core_clock_offset;
 101         __u32                           log_uar_size;
 102         __u32                           num_uars_per_page;
 103 };
 104
 105 struct mlx5_create_ah_resp {
 106         struct ibv_create_ah_resp       ibv_resp;
 107         __u32                           response_length;
 108         __u8                            dmac[ETHERNET_LL_SIZE];
 109         __u8                            reserved[6];
 110 };
 111
 112 struct mlx5_alloc_pd_resp {
 113         struct ibv_alloc_pd_resp        ibv_resp;
 114         __u32                           pdn;
 115 };
 116
 117 struct mlx5_create_cq {
 118         struct ibv_create_cq            ibv_cmd;
 119         __u64                           buf_addr;
 120         __u64                           db_addr;
 121         __u32                           cqe_size;
 122         __u8                            cqe_comp_en;
 123         __u8                            cqe_comp_res_format;
 124         __u16                           reserved;
 125 };
 126
 127 struct mlx5_create_cq_resp {
 128         struct ibv_create_cq_resp       ibv_resp;
 129         __u32                           cqn;
 130 };
 131
 132 struct mlx5_create_srq {
 133         struct ibv_create_srq           ibv_cmd;
 134         __u64                           buf_addr;
 135         __u64                           db_addr;
 136         __u32                           flags;
 137 };
 138
 139 struct mlx5_create_srq_resp {
 140         struct ibv_create_srq_resp      ibv_resp;
 141         __u32                           srqn;
 142         __u32                           reserved;
 143 };
 144
 145 struct mlx5_create_srq_ex {
 146         struct ibv_create_xsrq          ibv_cmd;
 147         __u64                           buf_addr;
 148         __u64                           db_addr;
 149         __u32                           flags;
 150         __u32                           reserved;
 151         __u32                           uidx;
 152         __u32                           reserved1;
 153 };
 154
 155 struct mlx5_create_qp_drv_ex {
 156         __u64                   buf_addr;
 157         __u64                   db_addr;
 158         __u32                   sq_wqe_count;
 159         __u32                   rq_wqe_count;
 160         __u32                   rq_wqe_shift;
 161         __u32                   flags;
 162         __u32                   uidx;
 163         __u32                   reserved;
 164         /* SQ buffer address - used for Raw Packet QP */
 165         __u64                   sq_buf_addr;
 166 };
 167
 168 struct mlx5_create_qp_ex {
 169         struct ibv_create_qp_ex ibv_cmd;
 170         struct mlx5_create_qp_drv_ex drv_ex;
 171 };
 172
 173 struct mlx5_create_qp_ex_rss {
 174         struct ibv_create_qp_ex ibv_cmd;
 175         __u64 rx_hash_fields_mask; /* enum ibv_rx_hash_fields */
 176         __u8 rx_hash_function; /* enum ibv_rx_hash_function_flags */
 177         __u8 rx_key_len;
 178         __u8 reserved[6];
 179         __u8 rx_hash_key[128];
 180         __u32   comp_mask;
 181         __u32   reserved1;
 182 };
 183
 184 struct mlx5_create_qp_resp_ex {
 185         struct ibv_create_qp_resp_ex    ibv_resp;
 186         __u32                           uuar_index;
 187         __u32                           reserved;
 188 };
 189
 190 struct mlx5_create_qp {
 191         struct ibv_create_qp            ibv_cmd;
 192         __u64                           buf_addr;
 193         __u64                           db_addr;
 194         __u32                           sq_wqe_count;
 195         __u32                           rq_wqe_count;
 196         __u32                           rq_wqe_shift;
 197         __u32                           flags;
 198         __u32                           uidx;
 199         __u32                           reserved;
 200         /* SQ buffer address - used for Raw Packet QP */
 201         __u64                           sq_buf_addr;
 202 };
 203
 204 struct mlx5_create_qp_resp {
 205         struct ibv_create_qp_resp       ibv_resp;
 206         __u32                           uuar_index;
 207 };
 208
 209 struct mlx5_drv_create_wq {
 210         __u64           buf_addr;
 211         __u64           db_addr;
 212         __u32           rq_wqe_count;
 213         __u32           rq_wqe_shift;
 214         __u32           user_index;
 215         __u32           flags;
 216         __u32           comp_mask;
 217         __u32           reserved;
 218 };
 219
 220 struct mlx5_create_wq {
 221         struct ibv_create_wq    ibv_cmd;
 222         struct mlx5_drv_create_wq       drv;
 223 };
 224
 225 struct mlx5_create_wq_resp {
 226         struct ibv_create_wq_resp       ibv_resp;
 227         __u32                   response_length;
 228         __u32                   reserved;
 229 };
 230
 231 struct mlx5_modify_wq {
 232         struct ibv_modify_wq    ibv_cmd;
 233         __u32                   comp_mask;
 234         __u32                   reserved;
 235 };
 236
 237 struct mlx5_create_rwq_ind_table_resp {
 238         struct ibv_create_rwq_ind_table_resp ibv_resp;
 239 };
 240
 241 struct mlx5_destroy_rwq_ind_table {
 242         struct ibv_destroy_rwq_ind_table ibv_cmd;
 243 };
 244
 245 struct mlx5_resize_cq {
 246         struct ibv_resize_cq            ibv_cmd;
 247         __u64                           buf_addr;
 248         __u16                           cqe_size;
 249         __u16                           reserved0;
 250         __u32                           reserved1;
 251 };
 252
 253 struct mlx5_resize_cq_resp {
 254         struct ibv_resize_cq_resp       ibv_resp;
 255 };
 256
 257 struct mlx5_query_device_ex {
 258         struct ibv_query_device_ex      ibv_cmd;
 259 };
 260
 261 struct mlx5_reserved_tso_caps {
 262         __u64 reserved;
 263 };
 264
 265 struct mlx5_rss_caps {
 266         __u64 rx_hash_fields_mask; /* enum ibv_rx_hash_fields */
 267         __u8 rx_hash_function; /* enum ibv_rx_hash_function_flags */
 268         __u8 reserved[7];
 269 };
 270
 271 struct mlx5_packet_pacing_caps {
 272         struct ibv_packet_pacing_caps caps;
 273         __u32  reserved;
 274 };
 275
 276 struct mlx5_query_device_ex_resp {
 277         struct ibv_query_device_resp_ex ibv_resp;
 278         __u32                           comp_mask;
 279         __u32                           response_length;
 280         struct ibv_tso_caps             tso_caps;
 281         struct mlx5_rss_caps            rss_caps; /* vendor data channel */
 282         struct mlx5dv_cqe_comp_caps     cqe_comp_caps;
 283         struct mlx5_packet_pacing_caps  packet_pacing_caps;
 284         __u32                           support_multi_pkt_send_wqe;
 285         __u32                           reserved;
 286 };
 287
 288 #endif /* MLX5_ABI_H */