2 * Copyright (c) 2012 Mellanox Technologies, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 struct mlx5_sg_copy_ptr {
43 struct mlx5_eqe_comp {
48 struct mlx5_eqe_qp_srq {
53 struct mlx5_wqe_xrc_seg {
58 struct mlx5_wqe_masked_atomic_seg {
61 uint64_t swap_add_mask;
62 uint64_t compare_mask;
66 MLX5_ETH_L2_INLINE_HEADER_SIZE = 18,
67 MLX5_ETH_L2_MIN_HEADER_SIZE = 14,
71 MLX5_WQE_UMR_CTRL_FLAG_INLINE = 1 << 7,
72 MLX5_WQE_UMR_CTRL_FLAG_CHECK_FREE = 1 << 5,
73 MLX5_WQE_UMR_CTRL_FLAG_TRNSLATION_OFFSET = 1 << 4,
74 MLX5_WQE_UMR_CTRL_FLAG_CHECK_QPN = 1 << 3,
78 MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN = 1 << 0,
79 MLX5_WQE_UMR_CTRL_MKEY_MASK_START_ADDR = 1 << 6,
80 MLX5_WQE_UMR_CTRL_MKEY_MASK_MKEY = 1 << 13,
81 MLX5_WQE_UMR_CTRL_MKEY_MASK_QPN = 1 << 14,
82 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_LOCAL_WRITE = 1 << 18,
83 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_REMOTE_READ = 1 << 19,
84 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_REMOTE_WRITE = 1 << 20,
85 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_ATOMIC = 1 << 21,
86 MLX5_WQE_UMR_CTRL_MKEY_MASK_FREE = 1 << 29,
89 struct mlx5_wqe_umr_ctrl_seg {
92 uint16_t klm_octowords;
93 uint16_t translation_offset;
98 struct mlx5_wqe_umr_klm_seg {
105 union mlx5_wqe_umr_inline_seg {
106 struct mlx5_wqe_umr_klm_seg klm;
110 MLX5_WQE_MKEY_CONTEXT_FREE = 1 << 6
114 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_ATOMIC = 1 << 6,
115 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_REMOTE_WRITE = 1 << 5,
116 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_REMOTE_READ = 1 << 4,
117 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_LOCAL_WRITE = 1 << 3,
118 MLX5_WQE_MKEY_CONTEXT_ACCESS_FLAGS_LOCAL_READ = 1 << 2
121 struct mlx5_wqe_mkey_context_seg {
124 uint8_t access_flags;
131 uint32_t bsf_octword_size;
132 uint32_t reserved3[4];
133 uint32_t translations_octword_size;
134 uint8_t reserved4[3];
135 uint8_t log_page_size;
137 union mlx5_wqe_umr_inline_seg inseg[0];
140 struct mlx5_seg_set_psv {
144 uint16_t block_guard;
151 struct mlx5_seg_get_psv {
156 uint32_t psv_index[4];
159 struct mlx5_seg_check_psv {
161 uint16_t err_coalescing_op;
163 uint16_t xport_err_op;
165 uint16_t xport_err_mask;
170 uint32_t psv_index[4];
173 struct mlx5_rwqe_sig {
179 struct mlx5_wqe_signature_seg {
185 struct mlx5_wqe_inline_seg {