2 * \file trc_cmp_cfg_etmv4.h
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
10 * Redistribution and use in source and binary forms, with or without modification,
11 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
20 * 3. Neither the name of the copyright holder nor the names of its contributors
21 * may be used to endorse or promote products derived from this software without
22 * specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #ifndef ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
37 #define ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
39 #include "trc_pkt_types_etmv4.h"
40 #include "common/trc_cs_config.h"
43 /** @addtogroup ocsd_protocol_cfg
46 /** @name ETMv4 configuration
51 * @brief Interpreter class for etm v4 config structure.
53 * Provides quick value interpretation methods for the ETMv4 config register values.
54 * Primarily inlined for efficient code.
56 class EtmV4Config : public CSConfig // public ocsd_etmv4_cfg
59 EtmV4Config(); /**< Default constructor */
60 EtmV4Config(const ocsd_etmv4_cfg *cfg_regs);
61 ~EtmV4Config() {}; /**< Default destructor */
63 // operations to convert to and from C-API structure
65 //! copy assignment operator for base structure into class.
66 EtmV4Config & operator=(const ocsd_etmv4_cfg *p_cfg);
68 //! cast operator returning struct const reference
69 operator const ocsd_etmv4_cfg &() const { return m_cfg; };
70 //! cast operator returning struct const pointer
71 operator const ocsd_etmv4_cfg *() const { return &m_cfg; };
73 const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; };
74 const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
77 const bool LSasInstP0() const;
78 const bool hasDataTrace() const;
79 const bool hasBranchBroadcast() const;
80 const bool hasCondTrace() const;
81 const bool hasCycleCountI() const;
82 const bool hasRetStack() const;
83 const uint8_t numEvents() const;
85 typedef enum _condType {
90 const condType hasCondType() const;
92 typedef enum _QSuppType {
99 const QSuppType getQSuppType();
100 const bool hasQElem();
101 const bool hasQFilter();
103 const bool hasTrcExcpData() const;
104 const uint32_t TimeStampSize() const;
106 const bool commitOpt1() const;
109 const uint8_t MajVersion() const;
110 const uint8_t MinVersion() const;
111 const uint8_t FullVersion() const;
114 const uint32_t iaSizeMax() const;
115 const uint32_t cidSize() const;
116 const uint32_t vmidSize();
117 const uint32_t daSize() const;
118 const uint32_t dvSize() const;
119 const uint32_t ccSize() const;
120 const bool vmidOpt() const;
121 const bool wfiwfeBranch() const;
124 const uint32_t MaxSpecDepth() const;
125 const uint32_t P0_Key_Max() const;
126 const uint32_t P1_Key_Max() const;
127 const uint32_t P1_Spcl_Key_Max() const;
128 const uint32_t CondKeyMax() const;
129 const uint32_t CondSpecKeyMax() const;
130 const uint32_t CondKeyMaxIncr() const;
133 virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device.
136 const bool enabledDVTrace() const;
137 const bool enabledDATrace() const;
138 const bool enabledDataTrace() const;
147 const bool enabledLSP0Trace() const;
148 const LSP0_t LSP0Type() const;
150 const bool enabledBrBroad() const;
151 const bool enabledCCI() const;
152 const bool enabledCID() const;
153 const bool enabledVMID() const;
163 const CondITrace_t enabledCondITrace();
165 const bool enabledTS() const;
166 const bool enabledRetStack() const;
168 const bool enabledQE() const;
177 QSuppType m_QSuppType;
182 bool m_condTraceCalc;
183 CondITrace_t m_CondTrace;
186 ocsd_etmv4_cfg m_cfg;
193 inline const bool EtmV4Config::LSasInstP0() const
195 return (bool)((m_cfg.reg_idr0 & 0x6) == 0x6);
198 inline const bool EtmV4Config::hasDataTrace() const
200 return (bool)((m_cfg.reg_idr0 & 0x18) == 0x18);
203 inline const bool EtmV4Config::hasBranchBroadcast() const
205 return (bool)((m_cfg.reg_idr0 & 0x20) == 0x20);
208 inline const bool EtmV4Config::hasCondTrace() const
210 return (bool)((m_cfg.reg_idr0 & 0x40) == 0x40);
213 inline const bool EtmV4Config::hasCycleCountI() const
215 return (bool)((m_cfg.reg_idr0 & 0x80) == 0x80);
218 inline const bool EtmV4Config::hasRetStack() const
220 return (bool)((m_cfg.reg_idr0 & 0x200) == 0x200);
223 inline const uint8_t EtmV4Config::numEvents() const
225 return ((m_cfg.reg_idr0 >> 10) & 0x3) + 1;
228 inline const EtmV4Config::condType EtmV4Config::hasCondType() const
230 return ((m_cfg.reg_idr0 & 0x3000) == 0x1000) ? EtmV4Config::COND_HAS_ASPR : EtmV4Config::COND_PASS_FAIL;
233 inline const EtmV4Config::QSuppType EtmV4Config::getQSuppType()
235 if(!m_QSuppCalc) CalcQSupp();
239 inline const bool EtmV4Config::hasQElem()
241 if(!m_QSuppCalc) CalcQSupp();
242 return (bool)(m_QSuppType != Q_NONE);
245 inline const bool EtmV4Config::hasQFilter()
247 if(!m_QSuppCalc) CalcQSupp();
248 return m_QSuppFilter;
251 inline const bool EtmV4Config::hasTrcExcpData() const
253 return (bool)((m_cfg.reg_idr0 & 0x20000) == 0x20000);
256 inline const uint32_t EtmV4Config::TimeStampSize() const
258 uint32_t tsSizeF = (m_cfg.reg_idr0 >> 24) & 0x1F;
266 inline const bool EtmV4Config::commitOpt1() const
268 return (bool)((m_cfg.reg_idr0 & 0x20000000) == 0x20000000) && hasCycleCountI();
272 inline const uint8_t EtmV4Config::MajVersion() const
277 inline const uint8_t EtmV4Config::MinVersion() const
282 inline const uint8_t EtmV4Config::FullVersion() const
284 return (m_MajVer << 4) | m_MinVer;
288 inline const uint32_t EtmV4Config::iaSizeMax() const
290 return ((m_cfg.reg_idr2 & 0x1F) == 0x8) ? 64 : 32;
293 inline const uint32_t EtmV4Config::cidSize() const
295 return (((m_cfg.reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0;
298 inline const uint32_t EtmV4Config::vmidSize()
307 inline const uint32_t EtmV4Config::daSize() const
309 uint32_t daSizeF = ((m_cfg.reg_idr2 >> 15) & 0x1F);
311 return (((m_cfg.reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32;
315 inline const uint32_t EtmV4Config::dvSize() const
317 uint32_t dvSizeF = ((m_cfg.reg_idr2 >> 20) & 0x1F);
319 return (((m_cfg.reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32;
323 inline const uint32_t EtmV4Config::ccSize() const
325 return ((m_cfg.reg_idr2 >> 25) & 0xF) + 12;
328 inline const bool EtmV4Config::vmidOpt() const
330 return (bool)((m_cfg.reg_idr2 & 0x20000000) == 0x20000000) && (MinVersion() > 0);
333 inline const bool EtmV4Config::wfiwfeBranch() const
335 return (bool)((m_cfg.reg_idr2 & 0x80000000) && (FullVersion() >= 0x43));
341 inline const uint32_t EtmV4Config::MaxSpecDepth() const
343 return m_cfg.reg_idr8;
346 inline const uint32_t EtmV4Config::P0_Key_Max() const
348 return (m_cfg.reg_idr9 == 0) ? 1 : m_cfg.reg_idr9;
351 inline const uint32_t EtmV4Config::P1_Key_Max() const
353 return m_cfg.reg_idr10;
356 inline const uint32_t EtmV4Config::P1_Spcl_Key_Max() const
358 return m_cfg.reg_idr11;
361 inline const uint32_t EtmV4Config::CondKeyMax() const
363 return m_cfg.reg_idr12;
366 inline const uint32_t EtmV4Config::CondSpecKeyMax() const
368 return m_cfg.reg_idr13;
371 inline const uint32_t EtmV4Config::CondKeyMaxIncr() const
373 return m_cfg.reg_idr12 - m_cfg.reg_idr13;
376 inline const uint8_t EtmV4Config::getTraceID() const
378 return (uint8_t)(m_cfg.reg_traceidr & 0x7F);
382 inline const bool EtmV4Config::enabledDVTrace() const
384 return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 17)) != 0);
387 inline const bool EtmV4Config::enabledDATrace() const
389 return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 16)) != 0);
392 inline const bool EtmV4Config::enabledDataTrace() const
394 return enabledDATrace() || enabledDVTrace();
397 inline const bool EtmV4Config::enabledLSP0Trace() const
399 return ((m_cfg.reg_configr & 0x6) != 0);
402 inline const EtmV4Config::LSP0_t EtmV4Config::LSP0Type() const
404 return (LSP0_t)((m_cfg.reg_configr & 0x6) >> 1);
407 inline const bool EtmV4Config::enabledBrBroad() const
409 return ((m_cfg.reg_configr & (0x1 << 3)) != 0);
412 inline const bool EtmV4Config::enabledCCI() const
414 return ((m_cfg.reg_configr & (0x1 << 4)) != 0);
417 inline const bool EtmV4Config::enabledCID() const
419 return ((m_cfg.reg_configr & (0x1 << 6)) != 0);
422 inline const bool EtmV4Config::enabledVMID() const
424 return ((m_cfg.reg_configr & (0x1 << 7)) != 0);
427 inline const EtmV4Config::CondITrace_t EtmV4Config::enabledCondITrace()
431 switch((m_cfg.reg_configr >> 8) & 0x7)
434 case 0: m_CondTrace = COND_TR_DIS; break;
435 case 1: m_CondTrace = COND_TR_LD; break;
436 case 2: m_CondTrace = COND_TR_ST; break;
437 case 3: m_CondTrace = COND_TR_LDST; break;
438 case 7: m_CondTrace = COND_TR_ALL; break;
440 m_condTraceCalc = true;
445 inline const bool EtmV4Config::enabledTS() const
447 return ((m_cfg.reg_configr & (0x1 << 11)) != 0);
450 inline const bool EtmV4Config::enabledRetStack() const
452 return ((m_cfg.reg_configr & (0x1 << 12)) != 0);
455 inline const bool EtmV4Config::enabledQE() const
457 return ((m_cfg.reg_configr & (0x3 << 13)) != 0);
463 #endif // ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
465 /* End of File trc_cmp_cfg_etmv4.h */