2 * \file trc_pkt_decode_etmv4i.h
3 * \brief OpenCSD : ETMv4 instruction decoder
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
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35 #ifndef ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED
36 #define ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED
38 #include "common/trc_pkt_decode_base.h"
39 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
40 #include "opencsd/etmv4/trc_cmp_cfg_etmv4.h"
41 #include "common/trc_gen_elem.h"
42 #include "common/trc_ret_stack.h"
43 #include "opencsd/etmv4/trc_etmv4_stack_elem.h"
46 class TrcStackElemParam;
47 class TrcStackElemCtxt;
49 class TrcPktDecodeEtmV4I : public TrcPktDecodeBase<EtmV4ITrcPacket, EtmV4Config>
53 TrcPktDecodeEtmV4I(int instIDNum);
54 virtual ~TrcPktDecodeEtmV4I();
57 /* implementation packet decoding interface */
58 virtual ocsd_datapath_resp_t processPacket();
59 virtual ocsd_datapath_resp_t onEOT();
60 virtual ocsd_datapath_resp_t onReset();
61 virtual ocsd_datapath_resp_t onFlush();
62 virtual ocsd_err_t onProtocolConfig();
63 virtual const uint8_t getCoreSightTraceID() { return m_CSID; };
65 /* local decode methods */
66 void initDecoder(); // initial state on creation (zeros all config)
67 void resetDecoder(); // reset state to start of decode. (moves state, retains config)
69 ocsd_datapath_resp_t decodePacket(bool &Complete); // return true to indicate decode complete - can change FSM to commit state - return is false.
70 ocsd_datapath_resp_t commitElements(bool &Complete); // commit elements - may get wait response, or flag completion.
71 ocsd_datapath_resp_t flushEOT();
73 void doTraceInfoPacket();
74 void updateContext(TrcStackElemCtxt *pCtxtElem);
76 // process atom will output instruction trace, or no memory access trace elements.
77 ocsd_datapath_resp_t processAtom(const ocsd_atm_val, bool &bCont);
79 // process an exception element - output instruction trace + exception generic type.
80 ocsd_datapath_resp_t processException();
82 // process a bad packet
83 ocsd_datapath_resp_t handleBadPacket(const char *reason);
85 ocsd_datapath_resp_t outputCC(TrcStackElemParam *pParamElem);
86 ocsd_datapath_resp_t outputTS(TrcStackElemParam *pParamElem, bool withCC);
87 ocsd_datapath_resp_t outputEvent(TrcStackElemParam *pParamElem);
90 void SetInstrInfoInAddrISA(const ocsd_vaddr_t addr_val, const uint8_t isa);
92 ocsd_err_t traceInstrToWP(bool &bWPFound, const bool traceToAddrNext = false, const ocsd_vaddr_t nextAddrMatch = 0); //!< follow instructions from the current address to a WP. true if good, false if memory cannot be accessed.
94 ocsd_datapath_resp_t returnStackPop(); // pop return stack and update instruction address.
96 //** intra packet state (see ETMv4 spec 6.2.1);
99 uint64_t m_timestamp; // last broadcast global Timestamp.
102 uint32_t m_context_id; // most recent context ID
103 uint32_t m_vmid_id; // most recent VMID
104 bool m_is_secure; // true if Secure
105 bool m_is_64bit; // true if 64 bit
110 // speculative trace (unsupported at present in the decoder).
111 int m_curr_spec_depth;
112 int m_max_spec_depth;
114 // data trace associative elements (unsupported at present in the decoder).
118 // conditional non-branch trace - when data trace active (unsupported at present in the decoder)
121 int m_cond_key_max_incr;
123 uint8_t m_CSID; //!< Coresight trace ID for this decoder.
125 bool m_IASize64; //!< True if 64 bit instruction addresses supported.
127 //** Other processor state;
131 NO_SYNC, //!< pre start trace - init state or after reset or overflow, loss of sync.
132 WAIT_SYNC, //!< waiting for sync packet.
133 WAIT_TINFO, //!< waiting for trace info packet.
134 DECODE_PKTS, //!< processing packets - creating decode elements on stack
135 COMMIT_ELEM, //!< commit elements for execution - create generic trace elements and pass on.
138 processor_state_t m_curr_state;
140 //** P0 element stack
141 EtmV4P0Stack m_P0_stack; //!< P0 decode element stack
143 int m_P0_commit; //!< number of elements to commit
145 // packet decode state
146 bool m_need_ctxt; //!< need context to continue
147 bool m_need_addr; //!< need an address to continue
148 bool m_except_pending_addr; //!< next address packet is part of exception.
150 // exception packet processing state (may need excep elem only, range+excep, range+
152 EXCEP_POP, // start of processing read exception packets off the stack and analyze
153 EXCEP_RANGE, // output a range element
154 EXCEP_NACC, // output a nacc element
155 EXCEP_EXCEP, // output an ecxeption element.
156 } excep_proc_state_t;
158 excep_proc_state_t m_excep_proc; //!< state of exception processing
159 etmv4_addr_val_t m_excep_addr; //!< excepiton return address.
160 ocsd_trc_index_t m_excep_index; //!< trace index for exception element
162 ocsd_instr_info m_instr_info; //!< instruction info for code follower - in address is the next to be decoded.
164 bool m_mem_nacc_pending; //!< need to output a memory access failure packet
165 ocsd_vaddr_t m_nacc_addr; //!< record unaccessible address
167 ocsd_pe_context m_pe_context; //!< current context information
168 etmv4_trace_info_t m_trace_info; //!< trace info for this trace run.
170 bool m_prev_overflow;
172 bool m_flush_EOT; //!< true if doing an end of trace flush - cleans up lingering events / TS / CC
174 TrcAddrReturnStack m_return_stack;
177 OcsdTraceElement m_output_elem;
181 #endif // ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED
183 /* End of File trc_pkt_decode_etmv4i.h */