2 * \file trc_pkt_elem_etmv4i.cpp
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
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37 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
39 EtmV4ITrcPacket::EtmV4ITrcPacket()
43 EtmV4ITrcPacket::~EtmV4ITrcPacket()
47 void EtmV4ITrcPacket::initStartState()
49 // clear packet state to start of trace (first sync or post discontinuity)
51 // clear all valid bits
56 v_addr.valid_bits = 0;
67 void EtmV4ITrcPacket::initNextPacket()
69 // clear valid bits for elements that are only valid over a single packet.
70 pkt_valid.bits.cc_valid = 0;
71 pkt_valid.bits.commit_elem_valid = 0;
74 context.updated_v = 0;
75 context.updated_c = 0;
76 err_type = ETM4_PKT_I_NO_ERR_TYPE;
80 void EtmV4ITrcPacket::toString(std::string &str) const
84 std::string valStr, ctxtStr = "";
86 name = packetTypeName(type, &desc);
87 str = name + (std::string)" : " + desc;
89 // extended descriptions
92 case ETM4_PKT_I_BAD_SEQUENCE:
93 case ETM4_PKT_I_INCOMPLETE_EOT:
94 name = packetTypeName(err_type, 0);
95 str += "[" + (std::string)name + "]";
98 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
99 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
101 case ETM4_PKT_I_ADDR_L_32IS0:
102 case ETM4_PKT_I_ADDR_L_32IS1:
103 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 32) ? v_addr.pkt_bits : 0);
104 str += "; Addr=" + valStr + "; " + ctxtStr;
107 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
108 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
110 case ETM4_PKT_I_ADDR_L_64IS0:
111 case ETM4_PKT_I_ADDR_L_64IS1:
112 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
113 str += "; Addr=" + valStr + "; " + ctxtStr;
116 case ETM4_PKT_I_CTXT:
118 str += "; " + ctxtStr;
121 case ETM4_PKT_I_ADDR_S_IS0:
122 case ETM4_PKT_I_ADDR_S_IS1:
123 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, v_addr.pkt_bits);
124 str += "; Addr=" + valStr;
127 case ETM4_PKT_I_ADDR_MATCH:
128 addrMatchIdx(valStr);
129 str += ", " + valStr;
130 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true);
131 str += "; Addr=" + valStr + "; " + ctxtStr;
134 case ETM4_PKT_I_ATOM_F1:
135 case ETM4_PKT_I_ATOM_F2:
136 case ETM4_PKT_I_ATOM_F3:
137 case ETM4_PKT_I_ATOM_F4:
138 case ETM4_PKT_I_ATOM_F5:
139 case ETM4_PKT_I_ATOM_F6:
141 str += "; " + valStr;
144 case ETM4_PKT_I_EXCEPT:
145 exceptionInfo(valStr);
146 str += "; " + valStr;
149 case ETM4_PKT_I_TIMESTAMP:
151 std::ostringstream oss;
152 oss << "; Updated val = " << std::hex << "0x" << ts.timestamp;
153 if (pkt_valid.bits.cc_valid)
154 oss << "; CC=" << std::hex << "0x" << cycle_count;
159 case ETM4_PKT_I_TRACE_INFO:
161 std::ostringstream oss;
162 oss << "; INFO=" << std::hex << "0x" << trace_info.val;
163 if (trace_info.bits.cc_enabled)
164 oss << "; CC_THRESHOLD=" << std::hex << "0x" << cc_threshold;
169 case ETM4_PKT_I_CCNT_F1:
170 case ETM4_PKT_I_CCNT_F2:
171 case ETM4_PKT_I_CCNT_F3:
173 std::ostringstream oss;
174 oss << "; Count=" << std::hex << "0x" << cycle_count;
181 void EtmV4ITrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
183 toString(str); // TBD add in formatted response.
186 const char *EtmV4ITrcPacket::packetTypeName(const ocsd_etmv4_i_pkt_type type, const char **ppDesc) const
188 const char *pName = "I_RESERVED";
189 const char *pDesc = "Reserved Packet Header";
193 case ETM4_PKT_I_RESERVED: break; // default;
195 case ETM4_PKT_I_NOTSYNC:
196 pName = "I_NOT_SYNC";
197 pDesc = "I Stream not synchronised";
200 case ETM4_PKT_I_BAD_SEQUENCE:
201 pName = "I_BAD_SEQUENCE";
202 pDesc = "Invalid Sequence in packet.";
205 case ETM4_PKT_I_BAD_TRACEMODE:
206 pName = "I_BAD_TRACEMODE";
207 pDesc = "Invalid Packet for trace mode.";
210 case ETM4_PKT_I_INCOMPLETE_EOT:
211 pName = "I_INCOMPLETE_EOT";
212 pDesc = "Incomplete packet at end of trace.";
215 case ETM4_PKT_I_NO_ERR_TYPE:
216 pName = "I_NO_ERR_TYPE";
217 pDesc = "No Error Type.";
220 case ETM4_PKT_I_EXTENSION:
221 pName = "I_EXTENSION";
222 pDesc = "Extention packet header.";
225 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
226 pName = "I_ADDR_CTXT_L_32IS0";
227 pDesc = "Address & Context, Long, 32 bit, IS0.";
230 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
231 pName = "I_ADDR_CTXT_L_32IS1";
232 pDesc = "Address & Context, Long, 32 bit, IS0.";
235 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
236 pName = "I_ADDR_CTXT_L_64IS0";
237 pDesc = "Address & Context, Long, 64 bit, IS0.";
240 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
241 pName = "I_ADDR_CTXT_L_64IS1";
242 pDesc = "Address & Context, Long, 64 bit, IS1.";
245 case ETM4_PKT_I_CTXT:
247 pDesc = "Context Packet.";
250 case ETM4_PKT_I_ADDR_MATCH:
251 pName = "I_ADDR_MATCH";
252 pDesc = "Exact Address Match.";
255 case ETM4_PKT_I_ADDR_L_32IS0:
256 pName = "I_ADDR_L_32IS0";
257 pDesc = "Address, Long, 32 bit, IS0.";
260 case ETM4_PKT_I_ADDR_L_32IS1:
261 pName = "I_ADDR_L_32IS1";
262 pDesc = "Address, Long, 32 bit, IS1.";
265 case ETM4_PKT_I_ADDR_L_64IS0:
266 pName = "I_ADDR_L_64IS0";
267 pDesc = "Address, Long, 64 bit, IS0.";
270 case ETM4_PKT_I_ADDR_L_64IS1:
271 pName = "I_ADDR_L_64IS1";
272 pDesc = "Address, Long, 64 bit, IS1.";
275 case ETM4_PKT_I_ADDR_S_IS0:
276 pName = "I_ADDR_S_IS0";
277 pDesc = "Address, Short, IS0.";
280 case ETM4_PKT_I_ADDR_S_IS1:
281 pName = "I_ADDR_S_IS1";
282 pDesc = "Address, Short, IS1.";
290 case ETM4_PKT_I_ATOM_F1:
292 pDesc = "Atom format 1.";
295 case ETM4_PKT_I_ATOM_F2:
297 pDesc = "Atom format 2.";
300 case ETM4_PKT_I_ATOM_F3:
302 pDesc = "Atom format 3.";
305 case ETM4_PKT_I_ATOM_F4:
307 pDesc = "Atom format 4.";
310 case ETM4_PKT_I_ATOM_F5:
312 pDesc = "Atom format 5.";
315 case ETM4_PKT_I_ATOM_F6:
317 pDesc = "Atom format 6.";
320 case ETM4_PKT_I_COND_FLUSH:
321 pName = "I_COND_FLUSH";
322 pDesc = "Conditional Flush.";
325 case ETM4_PKT_I_COND_I_F1:
326 pName = "I_COND_I_F1";
327 pDesc = "Conditional Instruction, format 1.";
330 case ETM4_PKT_I_COND_I_F2:
331 pName = "I_COND_I_F2";
332 pDesc = "Conditional Instruction, format 2.";
335 case ETM4_PKT_I_COND_I_F3:
336 pName = "I_COND_I_F3";
337 pDesc = "Conditional Instruction, format 3.";
340 case ETM4_PKT_I_COND_RES_F1:
341 pName = "I_COND_RES_F1";
342 pDesc = "Conditional Result, format 1.";
345 case ETM4_PKT_I_COND_RES_F2:
346 pName = "I_COND_RES_F2";
347 pDesc = "Conditional Result, format 2.";
350 case ETM4_PKT_I_COND_RES_F3:
351 pName = "I_COND_RES_F3";
352 pDesc = "Conditional Result, format 3.";
355 case ETM4_PKT_I_COND_RES_F4:
356 pName = "I_COND_RES_F4";
357 pDesc = "Conditional Result, format 4.";
360 case ETM4_PKT_I_CCNT_F1:
362 pDesc = "Cycle Count format 1.";
365 case ETM4_PKT_I_CCNT_F2:
367 pDesc = "Cycle Count format 2.";
370 case ETM4_PKT_I_CCNT_F3:
372 pDesc = "Cycle Count format 3.";
375 case ETM4_PKT_I_NUM_DS_MKR:
376 pName = "I_NUM_DS_MKR";
377 pDesc = "Data Synchronisation Marker - Numbered.";
380 case ETM4_PKT_I_UNNUM_DS_MKR:
381 pName = "I_UNNUM_DS_MKR";
382 pDesc = "Data Synchronisation Marker - Unnumbered.";
385 case ETM4_PKT_I_EVENT:
387 pDesc = "Trace Event.";
390 case ETM4_PKT_I_EXCEPT:
392 pDesc = "Exception.";
395 case ETM4_PKT_I_EXCEPT_RTN:
396 pName = "I_EXCEPT_RTN";
397 pDesc = "Exception Return.";
400 case ETM4_PKT_I_TIMESTAMP:
401 pName = "I_TIMESTAMP";
402 pDesc = "Timestamp.";
405 case ETM4_PKT_I_CANCEL_F1:
406 pName = "I_CANCEL_F1";
407 pDesc = "Cancel Format 1.";
409 case ETM4_PKT_I_CANCEL_F2:
410 pName = "I_CANCEL_F2";
411 pDesc = "Cancel Format 2.";
414 case ETM4_PKT_I_CANCEL_F3:
415 pName = "I_CANCEL_F3";
416 pDesc = "Cancel Format 3.";
419 case ETM4_PKT_I_COMMIT:
424 case ETM4_PKT_I_MISPREDICT:
425 pName = "I_MISPREDICT";
426 pDesc = "Mispredict.";
429 case ETM4_PKT_I_TRACE_INFO:
430 pName = "I_TRACE_INFO";
431 pDesc = "Trace Info.";
434 case ETM4_PKT_I_TRACE_ON:
435 pName = "I_TRACE_ON";
439 case ETM4_PKT_I_ASYNC:
441 pDesc = "Alignment Synchronisation.";
444 case ETM4_PKT_I_DISCARD:
449 case ETM4_PKT_I_OVERFLOW:
450 pName = "I_OVERFLOW";
455 if(ppDesc) *ppDesc = pDesc;
459 void EtmV4ITrcPacket::contextStr(std::string &ctxtStr) const
462 if(pkt_valid.bits.context_valid)
464 std::ostringstream oss;
467 oss << "Ctxt: " << (context.SF ? "AArch64," : "AArch32, ") << "EL" << context.EL << ", " << (context.NS ? "NS; " : "S; ");
468 if(context.updated_c)
470 oss << "CID=0x" << std::hex << std::setfill('0') << std::setw(8) << context.ctxtID << "; ";
472 if(context.updated_v)
474 oss << "VMID=0x" << std::hex << std::setfill('0') << std::setw(4) << context.VMID << "; ";
485 void EtmV4ITrcPacket::atomSeq(std::string &valStr) const
487 std::ostringstream oss;
488 uint32_t bitpattern = atom.En_bits;
489 for(int i = 0; i < atom.num; i++)
491 oss << ((bitpattern & 0x1) ? "E" : "N");
497 void EtmV4ITrcPacket::addrMatchIdx(std::string &valStr) const
499 std::ostringstream oss;
500 oss << "[" << (uint16_t)addr_exact_match_idx << "]";
504 void EtmV4ITrcPacket::exceptionInfo(std::string &valStr) const
506 std::ostringstream oss;
508 static const char *ARv8Excep[] = {
509 "PE Reset", "Debug Halt", "Call", "Trap",
510 "System Error", "Reserved", "Inst Debug", "Data Debug",
511 "Reserved", "Reserved", "Alignment", "Inst Fault",
512 "Data Fault", "Reserved", "IRQ", "FIQ"
515 static const char *MExcep[] = {
516 "Reserved", "PE Reset", "NMI", "HardFault",
517 "MemManage", "BusFault", "UsageFault", "Reserved",
518 "Reserved","Reserved","Reserved","SVC",
519 "DebugMonitor", "Reserved","PendSV","SysTick",
520 "IRQ0","IRQ1","IRQ2","IRQ3",
521 "IRQ4","IRQ5","IRQ6","IRQ7",
522 "DebugHalt", "LazyFP Push", "Lockup", "Reserved",
523 "Reserved","Reserved","Reserved","Reserved"
526 if(exception_info.m_type == 0)
528 if(exception_info.exceptionType < 0x10)
529 oss << " " << ARv8Excep[exception_info.exceptionType] << ";";
536 if(exception_info.exceptionType < 0x20)
537 oss << " " << MExcep[exception_info.exceptionType] << ";";
538 else if((exception_info.exceptionType >= 0x208) && (exception_info.exceptionType <= 0x3EF))
539 oss << " IRQ" << (int)(exception_info.exceptionType - 0x200) << ";";
542 if(exception_info.m_fault_pending)
543 oss << " Fault Pending;";
546 if(exception_info.addr_interp == 0x1)
547 oss << " Ret Addr Follows;";
548 else if(exception_info.addr_interp == 0x2)
549 oss << " Ret Addr Follows, Match Prev;";
554 EtmV4ITrcPacket &EtmV4ITrcPacket::operator =(const ocsd_etmv4_i_pkt* p_pkt)
556 *dynamic_cast<ocsd_etmv4_i_pkt *>(this) = *p_pkt;
560 /* End of File trc_pkt_elem_etmv4i.cpp */