2 * \file trc_i_decode.cpp
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
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35 #include "opencsd/ocsd_if_types.h"
36 #include "i_dec/trc_i_decode.h"
37 #include "i_dec/trc_idec_arminst.h"
39 ocsd_err_t TrcIDecode::DecodeInstruction(ocsd_instr_info *instr_info)
41 ocsd_err_t err = OCSD_OK;
42 clear_instr_subtype();
43 switch(instr_info->isa)
46 err = DecodeA32(instr_info);
50 err = DecodeT32(instr_info);
53 case ocsd_isa_aarch64:
54 err = DecodeA64(instr_info);
58 case ocsd_isa_jazelle:
61 err = OCSD_ERR_UNSUPPORTED_ISA;
64 instr_info->sub_type = get_instr_subtype();
68 ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info)
70 uint32_t branchAddr = 0;
71 arm_barrier_t barrier;
73 instr_info->instr_size = 4; // instruction size A32
74 instr_info->type = OCSD_INSTR_OTHER; // default type
75 instr_info->next_isa = instr_info->isa; // assume same ISA
76 instr_info->is_link = 0;
78 if(inst_ARM_is_indirect_branch(instr_info->opcode))
80 instr_info->type = OCSD_INSTR_BR_INDIRECT;
81 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode);
83 else if(inst_ARM_is_direct_branch(instr_info->opcode))
85 inst_ARM_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr);
86 instr_info->type = OCSD_INSTR_BR;
89 instr_info->next_isa = ocsd_isa_thumb2;
92 instr_info->branch_addr = (ocsd_vaddr_t)branchAddr;
93 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode);
95 else if((barrier = inst_ARM_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
100 instr_info->type = OCSD_INSTR_ISB;
103 case ARM_BARRIER_DSB:
104 case ARM_BARRIER_DMB:
105 if(instr_info->dsb_dmb_waypoints)
106 instr_info->type = OCSD_INSTR_DSB_DMB;
111 instr_info->is_conditional = inst_ARM_is_conditional(instr_info->opcode);
116 ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info)
118 uint64_t branchAddr = 0;
119 arm_barrier_t barrier;
121 instr_info->instr_size = 4; // default address update
122 instr_info->type = OCSD_INSTR_OTHER; // default type
123 instr_info->next_isa = instr_info->isa; // assume same ISA
124 instr_info->is_link = 0;
126 if(inst_A64_is_indirect_branch(instr_info->opcode))
128 instr_info->type = OCSD_INSTR_BR_INDIRECT;
129 instr_info->is_link = inst_A64_is_branch_and_link(instr_info->opcode);
131 else if(inst_A64_is_direct_branch(instr_info->opcode))
133 inst_A64_branch_destination(instr_info->instr_addr,instr_info->opcode,&branchAddr);
134 instr_info->type = OCSD_INSTR_BR;
135 instr_info->branch_addr = (ocsd_vaddr_t)branchAddr;
136 instr_info->is_link = inst_A64_is_branch_and_link(instr_info->opcode);
138 else if((barrier = inst_A64_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
142 case ARM_BARRIER_ISB:
143 instr_info->type = OCSD_INSTR_ISB;
146 case ARM_BARRIER_DSB:
147 case ARM_BARRIER_DMB:
148 if(instr_info->dsb_dmb_waypoints)
149 instr_info->type = OCSD_INSTR_DSB_DMB;
154 instr_info->is_conditional = inst_A64_is_conditional(instr_info->opcode);
159 ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info)
161 uint32_t branchAddr = 0;
162 arm_barrier_t barrier;
164 // need to align the 32 bit opcode as 2 16 bit, with LS 16 as in top 16 bit of
165 // 32 bit word - T2 routines assume 16 bit in top 16 bit of 32 bit opcode.
166 uint32_t op_temp = (instr_info->opcode >> 16) & 0xFFFF;
167 op_temp |= ((instr_info->opcode & 0xFFFF) << 16);
168 instr_info->opcode = op_temp;
171 instr_info->instr_size = is_wide_thumb((uint16_t)(instr_info->opcode >> 16)) ? 4 : 2;
172 instr_info->type = OCSD_INSTR_OTHER; // default type
173 instr_info->next_isa = instr_info->isa; // assume same ISA
174 instr_info->is_link = 0;
176 if(inst_Thumb_is_indirect_branch(instr_info->opcode))
178 instr_info->type = OCSD_INSTR_BR_INDIRECT;
179 instr_info->is_link = inst_Thumb_is_branch_and_link(instr_info->opcode);
181 else if(inst_Thumb_is_direct_branch(instr_info->opcode))
183 inst_Thumb_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr);
184 instr_info->type = OCSD_INSTR_BR;
185 instr_info->branch_addr = (ocsd_vaddr_t)(branchAddr & ~0x1);
186 if((branchAddr & 0x1) == 0)
187 instr_info->next_isa = ocsd_isa_arm;
188 instr_info->is_link = inst_Thumb_is_branch_and_link(instr_info->opcode);
190 else if((barrier = inst_Thumb_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
194 case ARM_BARRIER_ISB:
195 instr_info->type = OCSD_INSTR_ISB;
198 case ARM_BARRIER_DSB:
199 case ARM_BARRIER_DMB:
200 if(instr_info->dsb_dmb_waypoints)
201 instr_info->type = OCSD_INSTR_DSB_DMB;
206 instr_info->is_conditional = inst_Thumb_is_conditional(instr_info->opcode);
207 instr_info->thumb_it_conditions = inst_Thumb_is_IT(instr_info->opcode);
213 /* End of File trc_i_decode.cpp */