10 __attribute__ ((visibility("hidden")))
11 unsigned int OPENSSL_armcap_P = 0;
13 #if __ARM_MAX_ARCH__<7
14 void OPENSSL_cpuid_setup(void)
18 unsigned long OPENSSL_rdtsc(void)
23 static sigset_t all_masked;
25 static sigjmp_buf ill_jmp;
26 static void ill_handler(int sig)
28 siglongjmp(ill_jmp, sig);
32 * Following subroutines could have been inlined, but it's not all
33 * ARM compilers support inline assembler...
35 void _armv7_neon_probe(void);
36 void _armv8_aes_probe(void);
37 void _armv8_sha1_probe(void);
38 void _armv8_sha256_probe(void);
39 void _armv8_pmull_probe(void);
40 unsigned long _armv7_tick(void);
42 unsigned long OPENSSL_rdtsc(void)
44 if (OPENSSL_armcap_P & ARMV7_TICK)
51 * Use a weak reference to getauxval() so we can use it if it is available but
52 * don't break the build if it is not.
54 # if defined(__GNUC__) && __GNUC__>=2
55 void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
56 extern unsigned long getauxval(unsigned long type) __attribute__ ((weak));
58 static unsigned long (*getauxval) (unsigned long) = NULL;
62 * ARM puts the the feature bits for Crypto Extensions in AT_HWCAP2, whereas
63 * AArch64 used AT_HWCAP.
65 # if defined(__arm__) || defined (__arm)
68 # define HWCAP_NEON (1 << 12)
72 # define HWCAP_CE_AES (1 << 0)
73 # define HWCAP_CE_PMULL (1 << 1)
74 # define HWCAP_CE_SHA1 (1 << 2)
75 # define HWCAP_CE_SHA256 (1 << 3)
76 # elif defined(__aarch64__)
79 # define HWCAP_NEON (1 << 1)
81 # define HWCAP_CE HWCAP
82 # define HWCAP_CE_AES (1 << 3)
83 # define HWCAP_CE_PMULL (1 << 4)
84 # define HWCAP_CE_SHA1 (1 << 5)
85 # define HWCAP_CE_SHA256 (1 << 6)
88 void OPENSSL_cpuid_setup(void)
91 struct sigaction ill_oact, ill_act;
93 static int trigger = 0;
99 if ((e = getenv("OPENSSL_armcap"))) {
100 OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
104 sigfillset(&all_masked);
105 sigdelset(&all_masked, SIGILL);
106 sigdelset(&all_masked, SIGTRAP);
107 sigdelset(&all_masked, SIGFPE);
108 sigdelset(&all_masked, SIGBUS);
109 sigdelset(&all_masked, SIGSEGV);
111 OPENSSL_armcap_P = 0;
113 memset(&ill_act, 0, sizeof(ill_act));
114 ill_act.sa_handler = ill_handler;
115 ill_act.sa_mask = all_masked;
117 sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
118 sigaction(SIGILL, &ill_act, &ill_oact);
120 if (getauxval != NULL) {
121 if (getauxval(HWCAP) & HWCAP_NEON) {
122 unsigned long hwcap = getauxval(HWCAP_CE);
124 OPENSSL_armcap_P |= ARMV7_NEON;
126 if (hwcap & HWCAP_CE_AES)
127 OPENSSL_armcap_P |= ARMV8_AES;
129 if (hwcap & HWCAP_CE_PMULL)
130 OPENSSL_armcap_P |= ARMV8_PMULL;
132 if (hwcap & HWCAP_CE_SHA1)
133 OPENSSL_armcap_P |= ARMV8_SHA1;
135 if (hwcap & HWCAP_CE_SHA256)
136 OPENSSL_armcap_P |= ARMV8_SHA256;
138 } else if (sigsetjmp(ill_jmp, 1) == 0) {
140 OPENSSL_armcap_P |= ARMV7_NEON;
141 if (sigsetjmp(ill_jmp, 1) == 0) {
142 _armv8_pmull_probe();
143 OPENSSL_armcap_P |= ARMV8_PMULL | ARMV8_AES;
144 } else if (sigsetjmp(ill_jmp, 1) == 0) {
146 OPENSSL_armcap_P |= ARMV8_AES;
148 if (sigsetjmp(ill_jmp, 1) == 0) {
150 OPENSSL_armcap_P |= ARMV8_SHA1;
152 if (sigsetjmp(ill_jmp, 1) == 0) {
153 _armv8_sha256_probe();
154 OPENSSL_armcap_P |= ARMV8_SHA256;
157 if (sigsetjmp(ill_jmp, 1) == 0) {
159 OPENSSL_armcap_P |= ARMV7_TICK;
162 sigaction(SIGILL, &ill_oact, NULL);
163 sigprocmask(SIG_SETMASK, &oset, NULL);