2 * Copyright 2009-2021 The OpenSSL Project Authors. All Rights Reserved.
4 * Licensed under the OpenSSL license (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
16 #if defined(__linux) || defined(_AIX)
17 # include <sys/utsname.h>
19 #if defined(_AIX53) /* defined even on post-5.3 */
20 # include <sys/systemcfg.h>
21 # if !defined(__power_set)
22 # define __power_set(a) (_system_configuration.implementation & (a))
25 #if defined(__APPLE__) && defined(__MACH__)
26 # include <sys/types.h>
27 # include <sys/sysctl.h>
29 #include <openssl/crypto.h>
30 #include <openssl/bn.h>
31 #include <internal/cryptlib.h>
32 #include <crypto/chacha.h>
33 #include "bn/bn_local.h"
37 unsigned int OPENSSL_ppccap_P = 0;
39 static sigset_t all_masked;
41 #ifdef OPENSSL_BN_ASM_MONT
42 int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp,
43 const BN_ULONG *np, const BN_ULONG *n0, int num)
45 int bn_mul_mont_int(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp,
46 const BN_ULONG *np, const BN_ULONG *n0, int num);
47 int bn_mul4x_mont_int(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp,
48 const BN_ULONG *np, const BN_ULONG *n0, int num);
54 return bn_mul4x_mont_int(rp, ap, bp, np, n0, num);
57 * There used to be [optional] call to bn_mul_mont_fpu64 here,
58 * but above subroutine is faster on contemporary processors.
59 * Formulation means that there might be old processors where
60 * FPU code path would be faster, POWER6 perhaps, but there was
61 * no opportunity to figure it out...
64 return bn_mul_mont_int(rp, ap, bp, np, n0, num);
68 void sha256_block_p8(void *ctx, const void *inp, size_t len);
69 void sha256_block_ppc(void *ctx, const void *inp, size_t len);
70 void sha256_block_data_order(void *ctx, const void *inp, size_t len);
71 void sha256_block_data_order(void *ctx, const void *inp, size_t len)
73 OPENSSL_ppccap_P & PPC_CRYPTO207 ? sha256_block_p8(ctx, inp, len) :
74 sha256_block_ppc(ctx, inp, len);
77 void sha512_block_p8(void *ctx, const void *inp, size_t len);
78 void sha512_block_ppc(void *ctx, const void *inp, size_t len);
79 void sha512_block_data_order(void *ctx, const void *inp, size_t len);
80 void sha512_block_data_order(void *ctx, const void *inp, size_t len)
82 OPENSSL_ppccap_P & PPC_CRYPTO207 ? sha512_block_p8(ctx, inp, len) :
83 sha512_block_ppc(ctx, inp, len);
86 #ifndef OPENSSL_NO_CHACHA
87 void ChaCha20_ctr32_int(unsigned char *out, const unsigned char *inp,
88 size_t len, const unsigned int key[8],
89 const unsigned int counter[4]);
90 void ChaCha20_ctr32_vmx(unsigned char *out, const unsigned char *inp,
91 size_t len, const unsigned int key[8],
92 const unsigned int counter[4]);
93 void ChaCha20_ctr32_vsx(unsigned char *out, const unsigned char *inp,
94 size_t len, const unsigned int key[8],
95 const unsigned int counter[4]);
96 void ChaCha20_ctr32(unsigned char *out, const unsigned char *inp,
97 size_t len, const unsigned int key[8],
98 const unsigned int counter[4])
100 OPENSSL_ppccap_P & PPC_CRYPTO207
101 ? ChaCha20_ctr32_vsx(out, inp, len, key, counter)
102 : OPENSSL_ppccap_P & PPC_ALTIVEC
103 ? ChaCha20_ctr32_vmx(out, inp, len, key, counter)
104 : ChaCha20_ctr32_int(out, inp, len, key, counter);
108 #ifndef OPENSSL_NO_POLY1305
109 void poly1305_init_int(void *ctx, const unsigned char key[16]);
110 void poly1305_blocks(void *ctx, const unsigned char *inp, size_t len,
111 unsigned int padbit);
112 void poly1305_emit(void *ctx, unsigned char mac[16],
113 const unsigned int nonce[4]);
114 void poly1305_init_fpu(void *ctx, const unsigned char key[16]);
115 void poly1305_blocks_fpu(void *ctx, const unsigned char *inp, size_t len,
116 unsigned int padbit);
117 void poly1305_emit_fpu(void *ctx, unsigned char mac[16],
118 const unsigned int nonce[4]);
119 int poly1305_init(void *ctx, const unsigned char key[16], void *func[2]);
120 int poly1305_init(void *ctx, const unsigned char key[16], void *func[2])
122 if (sizeof(size_t) == 4 && (OPENSSL_ppccap_P & PPC_FPU)) {
123 poly1305_init_fpu(ctx, key);
124 func[0] = (void*)(uintptr_t)poly1305_blocks_fpu;
125 func[1] = (void*)(uintptr_t)poly1305_emit_fpu;
127 poly1305_init_int(ctx, key);
128 func[0] = (void*)(uintptr_t)poly1305_blocks;
129 func[1] = (void*)(uintptr_t)poly1305_emit;
135 #ifdef ECP_NISTZ256_ASM
136 void ecp_nistz256_mul_mont(unsigned long res[4], const unsigned long a[4],
137 const unsigned long b[4]);
139 void ecp_nistz256_to_mont(unsigned long res[4], const unsigned long in[4]);
140 void ecp_nistz256_to_mont(unsigned long res[4], const unsigned long in[4])
142 static const unsigned long RR[] = { 0x0000000000000003U,
145 0x00000004fffffffdU };
147 ecp_nistz256_mul_mont(res, in, RR);
150 void ecp_nistz256_from_mont(unsigned long res[4], const unsigned long in[4]);
151 void ecp_nistz256_from_mont(unsigned long res[4], const unsigned long in[4])
153 static const unsigned long one[] = { 1, 0, 0, 0 };
155 ecp_nistz256_mul_mont(res, in, one);
159 static sigjmp_buf ill_jmp;
160 static void ill_handler(int sig)
162 siglongjmp(ill_jmp, sig);
165 void OPENSSL_fpu_probe(void);
166 void OPENSSL_ppc64_probe(void);
167 void OPENSSL_altivec_probe(void);
168 void OPENSSL_crypto207_probe(void);
169 void OPENSSL_madd300_probe(void);
171 long OPENSSL_rdtsc_mftb(void);
172 long OPENSSL_rdtsc_mfspr268(void);
174 uint32_t OPENSSL_rdtsc(void)
176 if (OPENSSL_ppccap_P & PPC_MFTB)
177 return OPENSSL_rdtsc_mftb();
178 else if (OPENSSL_ppccap_P & PPC_MFSPR268)
179 return OPENSSL_rdtsc_mfspr268();
184 size_t OPENSSL_instrument_bus_mftb(unsigned int *, size_t);
185 size_t OPENSSL_instrument_bus_mfspr268(unsigned int *, size_t);
187 size_t OPENSSL_instrument_bus(unsigned int *out, size_t cnt)
189 if (OPENSSL_ppccap_P & PPC_MFTB)
190 return OPENSSL_instrument_bus_mftb(out, cnt);
191 else if (OPENSSL_ppccap_P & PPC_MFSPR268)
192 return OPENSSL_instrument_bus_mfspr268(out, cnt);
197 size_t OPENSSL_instrument_bus2_mftb(unsigned int *, size_t, size_t);
198 size_t OPENSSL_instrument_bus2_mfspr268(unsigned int *, size_t, size_t);
200 size_t OPENSSL_instrument_bus2(unsigned int *out, size_t cnt, size_t max)
202 if (OPENSSL_ppccap_P & PPC_MFTB)
203 return OPENSSL_instrument_bus2_mftb(out, cnt, max);
204 else if (OPENSSL_ppccap_P & PPC_MFSPR268)
205 return OPENSSL_instrument_bus2_mfspr268(out, cnt, max);
210 #if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
211 # if __GLIBC_PREREQ(2, 16)
212 # include <sys/auxv.h>
213 # define OSSL_IMPLEMENT_GETAUXVAL
214 # elif defined(__ANDROID_API__)
215 /* see https://developer.android.google.cn/ndk/guides/cpu-features */
216 # if __ANDROID_API__ >= 18
217 # include <sys/auxv.h>
218 # define OSSL_IMPLEMENT_GETAUXVAL
223 #if defined(__FreeBSD__)
224 # include <sys/param.h>
225 # if __FreeBSD_version >= 1200000
226 # include <sys/auxv.h>
227 # define OSSL_IMPLEMENT_GETAUXVAL
229 static unsigned long getauxval(unsigned long key)
231 unsigned long val = 0ul;
233 if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
241 /* I wish <sys/auxv.h> was universally available */
243 # define AT_HWCAP 16 /* AT_HWCAP */
245 #define HWCAP_PPC64 (1U << 30)
246 #define HWCAP_ALTIVEC (1U << 28)
247 #define HWCAP_FPU (1U << 27)
248 #define HWCAP_POWER6_EXT (1U << 9)
249 #define HWCAP_VSX (1U << 7)
252 # define AT_HWCAP2 26 /* AT_HWCAP2 */
254 #define HWCAP_VEC_CRYPTO (1U << 25)
255 #define HWCAP_ARCH_3_00 (1U << 23)
257 # if defined(__GNUC__) && __GNUC__>=2
258 __attribute__ ((constructor))
260 void OPENSSL_cpuid_setup(void)
263 struct sigaction ill_oact, ill_act;
265 static int trigger = 0;
271 if ((e = getenv("OPENSSL_ppccap"))) {
272 OPENSSL_ppccap_P = strtoul(e, NULL, 0);
276 OPENSSL_ppccap_P = 0;
279 OPENSSL_ppccap_P |= PPC_FPU;
281 if (sizeof(size_t) == 4) {
283 # if defined(_SC_AIX_KERNEL_BITMODE)
284 if (sysconf(_SC_AIX_KERNEL_BITMODE) != 64)
287 if (uname(&uts) != 0 || atoi(uts.version) < 6)
291 # if defined(__power_set)
293 * Value used in __power_set is a single-bit 1<<n one denoting
294 * specific processor class. Incidentally 0xffffffff<<n can be
295 * used to denote specific processor and its successors.
297 if (sizeof(size_t) == 4) {
298 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
299 if (__power_set(0xffffffffU<<13)) /* POWER5 and later */
300 OPENSSL_ppccap_P |= PPC_FPU64;
302 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
303 if (__power_set(0x1U<<14)) /* POWER6 */
304 OPENSSL_ppccap_P |= PPC_FPU64;
307 if (__power_set(0xffffffffU<<14)) /* POWER6 and later */
308 OPENSSL_ppccap_P |= PPC_ALTIVEC;
310 if (__power_set(0xffffffffU<<16)) /* POWER8 and later */
311 OPENSSL_ppccap_P |= PPC_CRYPTO207;
313 if (__power_set(0xffffffffU<<17)) /* POWER9 and later */
314 OPENSSL_ppccap_P |= PPC_MADD300;
320 #if defined(__APPLE__) && defined(__MACH__)
321 OPENSSL_ppccap_P |= PPC_FPU;
325 size_t len = sizeof(val);
327 if (sysctlbyname("hw.optional.64bitops", &val, &len, NULL, 0) == 0) {
329 OPENSSL_ppccap_P |= PPC_FPU64;
333 if (sysctlbyname("hw.optional.altivec", &val, &len, NULL, 0) == 0) {
335 OPENSSL_ppccap_P |= PPC_ALTIVEC;
342 #ifdef OSSL_IMPLEMENT_GETAUXVAL
344 unsigned long hwcap = getauxval(AT_HWCAP);
345 unsigned long hwcap2 = getauxval(AT_HWCAP2);
347 if (hwcap & HWCAP_FPU) {
348 OPENSSL_ppccap_P |= PPC_FPU;
350 if (sizeof(size_t) == 4) {
351 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
352 if (hwcap & HWCAP_PPC64)
353 OPENSSL_ppccap_P |= PPC_FPU64;
355 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
356 if (hwcap & HWCAP_POWER6_EXT)
357 OPENSSL_ppccap_P |= PPC_FPU64;
361 if (hwcap & HWCAP_ALTIVEC) {
362 OPENSSL_ppccap_P |= PPC_ALTIVEC;
364 if ((hwcap & HWCAP_VSX) && (hwcap2 & HWCAP_VEC_CRYPTO))
365 OPENSSL_ppccap_P |= PPC_CRYPTO207;
368 if (hwcap2 & HWCAP_ARCH_3_00) {
369 OPENSSL_ppccap_P |= PPC_MADD300;
374 sigfillset(&all_masked);
375 sigdelset(&all_masked, SIGILL);
376 sigdelset(&all_masked, SIGTRAP);
378 sigdelset(&all_masked, SIGEMT);
380 sigdelset(&all_masked, SIGFPE);
381 sigdelset(&all_masked, SIGBUS);
382 sigdelset(&all_masked, SIGSEGV);
384 memset(&ill_act, 0, sizeof(ill_act));
385 ill_act.sa_handler = ill_handler;
386 ill_act.sa_mask = all_masked;
388 sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
389 sigaction(SIGILL, &ill_act, &ill_oact);
391 #ifndef OSSL_IMPLEMENT_GETAUXVAL
392 if (sigsetjmp(ill_jmp,1) == 0) {
394 OPENSSL_ppccap_P |= PPC_FPU;
396 if (sizeof(size_t) == 4) {
399 if (uname(&uts) == 0 && strcmp(uts.machine, "ppc64") == 0)
401 if (sigsetjmp(ill_jmp, 1) == 0) {
402 OPENSSL_ppc64_probe();
403 OPENSSL_ppccap_P |= PPC_FPU64;
407 * Wanted code detecting POWER6 CPU and setting PPC_FPU64
412 if (sigsetjmp(ill_jmp, 1) == 0) {
413 OPENSSL_altivec_probe();
414 OPENSSL_ppccap_P |= PPC_ALTIVEC;
415 if (sigsetjmp(ill_jmp, 1) == 0) {
416 OPENSSL_crypto207_probe();
417 OPENSSL_ppccap_P |= PPC_CRYPTO207;
421 if (sigsetjmp(ill_jmp, 1) == 0) {
422 OPENSSL_madd300_probe();
423 OPENSSL_ppccap_P |= PPC_MADD300;
427 if (sigsetjmp(ill_jmp, 1) == 0) {
428 OPENSSL_rdtsc_mftb();
429 OPENSSL_ppccap_P |= PPC_MFTB;
430 } else if (sigsetjmp(ill_jmp, 1) == 0) {
431 OPENSSL_rdtsc_mfspr268();
432 OPENSSL_ppccap_P |= PPC_MFSPR268;
435 sigaction(SIGILL, &ill_oact, NULL);
436 sigprocmask(SIG_SETMASK, &oset, NULL);