1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
27 #include "safe-ctype.h"
30 #include "opcode/sparc.h"
31 #include "dw2gencfi.h"
34 #include "elf/sparc.h"
35 #include "dwarf2dbg.h"
38 /* Some ancient Sun C compilers would not take such hex constants as
39 unsigned, and would end up sign-extending them to form an offsetT,
40 so use these constants instead. */
41 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
42 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
44 static struct sparc_arch *lookup_arch PARAMS ((char *));
45 static void init_default_arch PARAMS ((void));
46 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
47 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
48 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
49 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
50 static int sparc_ffs PARAMS ((unsigned int));
51 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
52 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
53 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
54 static bfd_vma BSR PARAMS ((bfd_vma, int));
55 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
56 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
57 static int parse_const_expr_arg PARAMS ((char **, int *));
58 static int get_expression PARAMS ((char *str));
60 /* Default architecture. */
61 /* ??? The default value should be V8, but sparclite support was added
62 by making it the default. GCC now passes -Asparclite, so maybe sometime in
63 the future we can set this to V8. */
65 #define DEFAULT_ARCH "sparclite"
67 static char *default_arch = DEFAULT_ARCH;
69 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
71 static int default_init_p;
73 /* Current architecture. We don't bump up unless necessary. */
74 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
76 /* The maximum architecture level we can bump up to.
77 In a 32 bit environment, don't allow bumping up to v9 by default.
78 The native assembler works this way. The user is required to pass
79 an explicit argument before we'll create v9 object files. However, if
80 we don't see any v9 insns, a v8plus object file is not created. */
81 static enum sparc_opcode_arch_val max_architecture;
83 /* Either 32 or 64, selects file format. */
84 static int sparc_arch_size;
85 /* Initial (default) value, recorded separately in case a user option
86 changes the value before md_show_usage is called. */
87 static int default_arch_size;
90 /* The currently selected v9 memory model. Currently only used for
92 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
95 static int architecture_requested;
96 static int warn_on_bump;
98 /* If warn_on_bump and the needed architecture is higher than this
99 architecture, issue a warning. */
100 static enum sparc_opcode_arch_val warn_after_architecture;
102 /* Non-zero if as should generate error if an undeclared g[23] register
103 has been used in -64. */
104 static int no_undeclared_regs;
106 /* Non-zero if we should try to relax jumps and calls. */
107 static int sparc_relax;
109 /* Non-zero if we are generating PIC code. */
112 /* Non-zero if we should give an error when misaligned data is seen. */
113 static int enforce_aligned_data;
115 extern int target_big_endian;
117 static int target_little_endian_data;
119 /* Symbols for global registers on v9. */
120 static symbolS *globals[8];
122 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
123 int sparc_cie_data_alignment;
125 /* V9 and 86x have big and little endian data, but instructions are always big
126 endian. The sparclet has bi-endian support but both data and insns have
127 the same endianness. Global `target_big_endian' is used for data.
128 The following macro is used for instructions. */
129 #ifndef INSN_BIG_ENDIAN
130 #define INSN_BIG_ENDIAN (target_big_endian \
131 || default_arch_type == sparc86x \
132 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
135 /* Handle of the OPCODE hash table. */
136 static struct hash_control *op_hash;
138 static int mylog2 PARAMS ((int));
139 static void s_data1 PARAMS ((void));
140 static void s_seg PARAMS ((int));
141 static void s_proc PARAMS ((int));
142 static void s_reserve PARAMS ((int));
143 static void s_common PARAMS ((int));
144 static void s_empty PARAMS ((int));
145 static void s_uacons PARAMS ((int));
146 static void s_ncons PARAMS ((int));
148 static void s_register PARAMS ((int));
151 const pseudo_typeS md_pseudo_table[] =
153 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
154 {"common", s_common, 0},
155 {"empty", s_empty, 0},
156 {"global", s_globl, 0},
158 {"nword", s_ncons, 0},
159 {"optim", s_ignore, 0},
161 {"reserve", s_reserve, 0},
163 {"skip", s_space, 0},
166 {"uahalf", s_uacons, 2},
167 {"uaword", s_uacons, 4},
168 {"uaxword", s_uacons, 8},
170 /* These are specific to sparc/svr4. */
171 {"2byte", s_uacons, 2},
172 {"4byte", s_uacons, 4},
173 {"8byte", s_uacons, 8},
174 {"register", s_register, 0},
179 /* This array holds the chars that always start a comment. If the
180 pre-processor is disabled, these aren't very useful. */
181 const char comment_chars[] = "!"; /* JF removed '|' from
184 /* This array holds the chars that only start a comment at the beginning of
185 a line. If the line seems to have the form '# 123 filename'
186 .line and .file directives will appear in the pre-processed output. */
187 /* Note that input_file.c hand checks for '#' at the beginning of the
188 first line of the input file. This is because the compiler outputs
189 #NO_APP at the beginning of its output. */
190 /* Also note that comments started like this one will always
191 work if '/' isn't otherwise defined. */
192 const char line_comment_chars[] = "#";
194 const char line_separator_chars[] = ";";
196 /* Chars that can be used to separate mant from exp in floating point
198 const char EXP_CHARS[] = "eE";
200 /* Chars that mean this number is a floating point constant.
203 const char FLT_CHARS[] = "rRsSfFdDxXpP";
205 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
206 changed in read.c. Ideally it shouldn't have to know about it at all,
207 but nothing is ideal around here. */
209 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
214 unsigned long opcode;
215 struct nlist *nlistp;
219 bfd_reloc_code_real_type reloc;
222 struct sparc_it the_insn, set_insn;
224 static void output_insn
225 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
227 /* Table of arguments to -A.
228 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
229 for this use. That table is for opcodes only. This table is for opcodes
232 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
233 v8plusa, v9, v9a, v9b, v9_64};
235 static struct sparc_arch {
238 enum sparc_arch_types arch_type;
239 /* Default word size, as specified during configuration.
240 A value of zero means can't be used to specify default architecture. */
241 int default_arch_size;
242 /* Allowable arg to -A? */
244 } sparc_arch_table[] = {
245 { "v6", "v6", v6, 0, 1 },
246 { "v7", "v7", v7, 0, 1 },
247 { "v8", "v8", v8, 32, 1 },
248 { "sparclet", "sparclet", sparclet, 32, 1 },
249 { "sparclite", "sparclite", sparclite, 32, 1 },
250 { "sparc86x", "sparclite", sparc86x, 32, 1 },
251 { "v8plus", "v9", v9, 0, 1 },
252 { "v8plusa", "v9a", v9, 0, 1 },
253 { "v8plusb", "v9b", v9, 0, 1 },
254 { "v9", "v9", v9, 0, 1 },
255 { "v9a", "v9a", v9, 0, 1 },
256 { "v9b", "v9b", v9, 0, 1 },
257 /* This exists to allow configure.in/Makefile.in to pass one
258 value to specify both the default machine and default word size. */
259 { "v9-64", "v9", v9, 64, 0 },
260 { NULL, NULL, v8, 0, 0 }
263 /* Variant of default_arch */
264 static enum sparc_arch_types default_arch_type;
266 static struct sparc_arch *
270 struct sparc_arch *sa;
272 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
273 if (strcmp (sa->name, name) == 0)
275 if (sa->name == NULL)
280 /* Initialize the default opcode arch and word size from the default
281 architecture name. */
286 struct sparc_arch *sa = lookup_arch (default_arch);
289 || sa->default_arch_size == 0)
290 as_fatal (_("Invalid default architecture, broken assembler."));
292 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
293 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
294 as_fatal (_("Bad opcode table, broken assembler."));
295 default_arch_size = sparc_arch_size = sa->default_arch_size;
297 default_arch_type = sa->arch_type;
300 /* Called by TARGET_FORMAT. */
303 sparc_target_format ()
305 /* We don't get a chance to initialize anything before we're called,
306 so handle that now. */
307 if (! default_init_p)
308 init_default_arch ();
312 return "a.out-sparc-netbsd";
315 if (target_big_endian)
316 return "a.out-sunos-big";
317 else if (default_arch_type == sparc86x && target_little_endian_data)
318 return "a.out-sunos-big";
320 return "a.out-sparc-little";
322 return "a.out-sunos-big";
333 return "coff-sparc-lynx";
340 return "elf32-sparc-vxworks";
344 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
351 * Invocation line includes a switch not recognized by the base assembler.
352 * See if it's a processor-specific option. These are:
355 * Warn on architecture bumps. See also -A.
357 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
358 * Standard 32 bit architectures.
360 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
361 * This used to only mean 64 bits, but properly specifying it
362 * complicated gcc's ASM_SPECs, so now opcode selection is
363 * specified orthogonally to word size (except when specifying
364 * the default, but that is an internal implementation detail).
365 * -Av8plus, -Av8plusa, -Av8plusb
366 * Same as -Av9{,a,b}.
367 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
368 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
370 * -xarch=v9, -xarch=v9a, -xarch=v9b
371 * Same as -Av9{,a,b} -64, for compatibility with Sun's
374 * Select the architecture and possibly the file format.
375 * Instructions or features not supported by the selected
376 * architecture cause fatal errors.
378 * The default is to start at v6, and bump the architecture up
379 * whenever an instruction is seen at a higher level. In 32 bit
380 * environments, v9 is not bumped up to, the user must pass
383 * If -bump is specified, a warning is printing when bumping to
386 * If an architecture is specified, all instructions must match
387 * that architecture. Any higher level instructions are flagged
388 * as errors. Note that in the 32 bit environment specifying
389 * -Av8plus does not automatically create a v8plus object file, a
390 * v9 insn must be seen.
392 * If both an architecture and -bump are specified, the
393 * architecture starts at the specified level, but bumps are
394 * warnings. Note that we can't set `current_architecture' to
395 * the requested level in this case: in the 32 bit environment,
396 * we still must avoid creating v8plus object files unless v9
400 * Bumping between incompatible architectures is always an
401 * error. For example, from sparclite to v9.
405 const char *md_shortopts = "A:K:VQ:sq";
408 const char *md_shortopts = "A:k";
410 const char *md_shortopts = "A:";
413 struct option md_longopts[] = {
414 #define OPTION_BUMP (OPTION_MD_BASE)
415 {"bump", no_argument, NULL, OPTION_BUMP},
416 #define OPTION_SPARC (OPTION_MD_BASE + 1)
417 {"sparc", no_argument, NULL, OPTION_SPARC},
418 #define OPTION_XARCH (OPTION_MD_BASE + 2)
419 {"xarch", required_argument, NULL, OPTION_XARCH},
421 #define OPTION_32 (OPTION_MD_BASE + 3)
422 {"32", no_argument, NULL, OPTION_32},
423 #define OPTION_64 (OPTION_MD_BASE + 4)
424 {"64", no_argument, NULL, OPTION_64},
425 #define OPTION_TSO (OPTION_MD_BASE + 5)
426 {"TSO", no_argument, NULL, OPTION_TSO},
427 #define OPTION_PSO (OPTION_MD_BASE + 6)
428 {"PSO", no_argument, NULL, OPTION_PSO},
429 #define OPTION_RMO (OPTION_MD_BASE + 7)
430 {"RMO", no_argument, NULL, OPTION_RMO},
432 #ifdef SPARC_BIENDIAN
433 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
434 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
435 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
436 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
438 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
439 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
440 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
441 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
443 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
444 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
445 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
446 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
448 #define OPTION_RELAX (OPTION_MD_BASE + 14)
449 {"relax", no_argument, NULL, OPTION_RELAX},
450 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
451 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
452 {NULL, no_argument, NULL, 0}
455 size_t md_longopts_size = sizeof (md_longopts);
458 md_parse_option (c, arg)
462 /* We don't get a chance to initialize anything before we're called,
463 so handle that now. */
464 if (! default_init_p)
465 init_default_arch ();
471 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
476 if (strncmp (arg, "v9", 2) != 0)
477 md_parse_option (OPTION_32, NULL);
479 md_parse_option (OPTION_64, NULL);
485 struct sparc_arch *sa;
486 enum sparc_opcode_arch_val opcode_arch;
488 sa = lookup_arch (arg);
490 || ! sa->user_option_p)
492 if (c == OPTION_XARCH)
493 as_bad (_("invalid architecture -xarch=%s"), arg);
495 as_bad (_("invalid architecture -A%s"), arg);
499 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
500 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
501 as_fatal (_("Bad opcode table, broken assembler."));
503 max_architecture = opcode_arch;
504 architecture_requested = 1;
509 /* Ignore -sparc, used by SunOS make default .s.o rule. */
512 case OPTION_ENFORCE_ALIGNED_DATA:
513 enforce_aligned_data = 1;
516 #ifdef SPARC_BIENDIAN
517 case OPTION_LITTLE_ENDIAN:
518 target_big_endian = 0;
519 if (default_arch_type != sparclet)
520 as_fatal ("This target does not support -EL");
522 case OPTION_LITTLE_ENDIAN_DATA:
523 target_little_endian_data = 1;
524 target_big_endian = 0;
525 if (default_arch_type != sparc86x
526 && default_arch_type != v9)
527 as_fatal ("This target does not support --little-endian-data");
529 case OPTION_BIG_ENDIAN:
530 target_big_endian = 1;
544 const char **list, **l;
546 sparc_arch_size = c == OPTION_32 ? 32 : 64;
547 list = bfd_target_list ();
548 for (l = list; *l != NULL; l++)
550 if (sparc_arch_size == 32)
552 if (strcmp (*l, "elf32-sparc") == 0)
557 if (strcmp (*l, "elf64-sparc") == 0)
562 as_fatal (_("No compiled in support for %d bit object file format"),
569 sparc_memory_model = MM_TSO;
573 sparc_memory_model = MM_PSO;
577 sparc_memory_model = MM_RMO;
585 /* Qy - do emit .comment
586 Qn - do not emit .comment. */
590 /* Use .stab instead of .stab.excl. */
594 /* quick -- Native assembler does fewer checks. */
598 if (strcmp (arg, "PIC") != 0)
599 as_warn (_("Unrecognized option following -K"));
604 case OPTION_NO_UNDECLARED_REGS:
605 no_undeclared_regs = 1;
608 case OPTION_UNDECLARED_REGS:
609 no_undeclared_regs = 0;
617 case OPTION_NO_RELAX:
629 md_show_usage (stream)
632 const struct sparc_arch *arch;
635 /* We don't get a chance to initialize anything before we're called,
636 so handle that now. */
637 if (! default_init_p)
638 init_default_arch ();
640 fprintf (stream, _("SPARC options:\n"));
642 for (arch = &sparc_arch_table[0]; arch->name; arch++)
644 if (!arch->user_option_p)
646 if (arch != &sparc_arch_table[0])
647 fprintf (stream, " | ");
648 if (column + strlen (arch->name) > 70)
651 fputc ('\n', stream);
653 column += 5 + 2 + strlen (arch->name);
654 fprintf (stream, "-A%s", arch->name);
656 for (arch = &sparc_arch_table[0]; arch->name; arch++)
658 if (!arch->user_option_p)
660 fprintf (stream, " | ");
661 if (column + strlen (arch->name) > 65)
664 fputc ('\n', stream);
666 column += 5 + 7 + strlen (arch->name);
667 fprintf (stream, "-xarch=%s", arch->name);
669 fprintf (stream, _("\n\
670 specify variant of SPARC architecture\n\
671 -bump warn when assembler switches architectures\n\
673 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
674 -relax relax jumps and branches (default)\n\
675 -no-relax avoid changing any jumps and branches\n"));
677 fprintf (stream, _("\
678 -k generate PIC\n"));
681 fprintf (stream, _("\
682 -32 create 32 bit object file\n\
683 -64 create 64 bit object file\n"));
684 fprintf (stream, _("\
685 [default is %d]\n"), default_arch_size);
686 fprintf (stream, _("\
687 -TSO use Total Store Ordering\n\
688 -PSO use Partial Store Ordering\n\
689 -RMO use Relaxed Memory Ordering\n"));
690 fprintf (stream, _("\
691 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
692 fprintf (stream, _("\
693 -KPIC generate PIC\n\
694 -V print assembler version number\n\
695 -undeclared-regs ignore application global register usage without\n\
696 appropriate .register directive (default)\n\
697 -no-undeclared-regs force error on application global register usage\n\
698 without appropriate .register directive\n\
703 #ifdef SPARC_BIENDIAN
704 fprintf (stream, _("\
705 -EL generate code for a little endian machine\n\
706 -EB generate code for a big endian machine\n\
707 --little-endian-data generate code for a machine having big endian\n\
708 instructions and little endian data.\n"));
712 /* Native operand size opcode translation. */
718 } native_op_table[] =
720 {"ldn", "ld", "ldx"},
721 {"ldna", "lda", "ldxa"},
722 {"stn", "st", "stx"},
723 {"stna", "sta", "stxa"},
724 {"slln", "sll", "sllx"},
725 {"srln", "srl", "srlx"},
726 {"sran", "sra", "srax"},
727 {"casn", "cas", "casx"},
728 {"casna", "casa", "casxa"},
729 {"clrn", "clr", "clrx"},
733 /* sparc64 privileged and hyperprivileged registers. */
735 struct priv_reg_entry
741 struct priv_reg_entry priv_reg_table[] =
761 {"", -1}, /* End marker. */
764 struct priv_reg_entry hpriv_reg_table[] =
772 {"", -1}, /* End marker. */
775 /* v9a specific asrs. */
777 struct priv_reg_entry v9a_asr_table[] =
780 {"sys_tick_cmpr", 25},
788 {"clear_softint", 21},
789 {"", -1}, /* End marker. */
793 cmp_reg_entry (parg, qarg)
797 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
798 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
800 return strcmp (q->name, p->name);
803 /* This function is called once, at assembler startup time. It should
804 set up all the tables, etc. that the MD part of the assembler will
810 register const char *retval = NULL;
812 register unsigned int i = 0;
814 /* We don't get a chance to initialize anything before md_parse_option
815 is called, and it may not be called, so handle default initialization
816 now if not already done. */
817 if (! default_init_p)
818 init_default_arch ();
820 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
821 op_hash = hash_new ();
823 while (i < (unsigned int) sparc_num_opcodes)
825 const char *name = sparc_opcodes[i].name;
826 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
829 as_bad (_("Internal error: can't hash `%s': %s\n"),
830 sparc_opcodes[i].name, retval);
835 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
837 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
838 sparc_opcodes[i].name, sparc_opcodes[i].args);
843 while (i < (unsigned int) sparc_num_opcodes
844 && !strcmp (sparc_opcodes[i].name, name));
847 for (i = 0; native_op_table[i].name; i++)
849 const struct sparc_opcode *insn;
850 char *name = ((sparc_arch_size == 32)
851 ? native_op_table[i].name32
852 : native_op_table[i].name64);
853 insn = (struct sparc_opcode *) hash_find (op_hash, name);
856 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
857 name, native_op_table[i].name);
862 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
865 as_bad (_("Internal error: can't hash `%s': %s\n"),
866 sparc_opcodes[i].name, retval);
873 as_fatal (_("Broken assembler. No assembly attempted."));
875 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
876 sizeof (priv_reg_table[0]), cmp_reg_entry);
878 /* If -bump, record the architecture level at which we start issuing
879 warnings. The behaviour is different depending upon whether an
880 architecture was explicitly specified. If it wasn't, we issue warnings
881 for all upwards bumps. If it was, we don't start issuing warnings until
882 we need to bump beyond the requested architecture or when we bump between
883 conflicting architectures. */
886 && architecture_requested)
888 /* `max_architecture' records the requested architecture.
889 Issue warnings if we go above it. */
890 warn_after_architecture = max_architecture;
892 /* Find the highest architecture level that doesn't conflict with
893 the requested one. */
894 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
895 max_architecture > warn_after_architecture;
897 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
898 warn_after_architecture))
903 /* Called after all assembly has been done. */
908 unsigned long mach = bfd_mach_sparc;
910 if (sparc_arch_size == 64)
911 switch (current_architecture)
913 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
914 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
915 default: mach = bfd_mach_sparc_v9; break;
918 switch (current_architecture)
920 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
921 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
922 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
923 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
924 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
925 be but for now it is (since that's the way it's always been
929 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
932 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
935 in_signed_range (val, max)
936 bfd_signed_vma val, max;
940 /* Sign-extend the value from the architecture word size, so that
941 0xffffffff is always considered -1 on sparc32. */
942 if (sparc_arch_size == 32)
944 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
945 val = ((val & U0xffffffff) ^ sign) - sign;
954 /* Return non-zero if VAL is in the range 0 to MAX. */
957 in_unsigned_range (val, max)
965 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
966 (e.g. -15 to +31). */
969 in_bitfield_range (val, max)
970 bfd_signed_vma val, max;
976 if (val < ~(max >> 1))
990 for (i = 0; (mask & 1) == 0; ++i)
995 /* Implement big shift right. */
1001 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1002 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1003 return val >> amount;
1006 /* For communication between sparc_ip and get_expression. */
1007 static char *expr_end;
1009 /* Values for `special_case'.
1010 Instructions that require wierd handling because they're longer than
1012 #define SPECIAL_CASE_NONE 0
1013 #define SPECIAL_CASE_SET 1
1014 #define SPECIAL_CASE_SETSW 2
1015 #define SPECIAL_CASE_SETX 3
1016 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1017 #define SPECIAL_CASE_FDIV 4
1019 /* Bit masks of various insns. */
1020 #define NOP_INSN 0x01000000
1021 #define OR_INSN 0x80100000
1022 #define XOR_INSN 0x80180000
1023 #define FMOVS_INSN 0x81A00020
1024 #define SETHI_INSN 0x01000000
1025 #define SLLX_INSN 0x81281000
1026 #define SRA_INSN 0x81380000
1028 /* The last instruction to be assembled. */
1029 static const struct sparc_opcode *last_insn;
1030 /* The assembled opcode of `last_insn'. */
1031 static unsigned long last_opcode;
1033 /* Handle the set and setuw synthetic instructions. */
1036 synthetize_setuw (insn)
1037 const struct sparc_opcode *insn;
1039 int need_hi22_p = 0;
1040 int rd = (the_insn.opcode & RD (~0)) >> 25;
1042 if (the_insn.exp.X_op == O_constant)
1044 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1046 if (sizeof (offsetT) > 4
1047 && (the_insn.exp.X_add_number < 0
1048 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1049 as_warn (_("set: number not in 0..4294967295 range"));
1053 if (sizeof (offsetT) > 4
1054 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1055 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1056 as_warn (_("set: number not in -2147483648..4294967295 range"));
1057 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1061 /* See if operand is absolute and small; skip sethi if so. */
1062 if (the_insn.exp.X_op != O_constant
1063 || the_insn.exp.X_add_number >= (1 << 12)
1064 || the_insn.exp.X_add_number < -(1 << 12))
1066 the_insn.opcode = (SETHI_INSN | RD (rd)
1067 | ((the_insn.exp.X_add_number >> 10)
1068 & (the_insn.exp.X_op == O_constant
1070 the_insn.reloc = (the_insn.exp.X_op != O_constant
1071 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1072 output_insn (insn, &the_insn);
1076 /* See if operand has no low-order bits; skip OR if so. */
1077 if (the_insn.exp.X_op != O_constant
1078 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1081 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1083 | (the_insn.exp.X_add_number
1084 & (the_insn.exp.X_op != O_constant
1085 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1086 the_insn.reloc = (the_insn.exp.X_op != O_constant
1087 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1088 output_insn (insn, &the_insn);
1092 /* Handle the setsw synthetic instruction. */
1095 synthetize_setsw (insn)
1096 const struct sparc_opcode *insn;
1100 rd = (the_insn.opcode & RD (~0)) >> 25;
1102 if (the_insn.exp.X_op != O_constant)
1104 synthetize_setuw (insn);
1106 /* Need to sign extend it. */
1107 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1108 the_insn.reloc = BFD_RELOC_NONE;
1109 output_insn (insn, &the_insn);
1113 if (sizeof (offsetT) > 4
1114 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1115 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1116 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1118 low32 = the_insn.exp.X_add_number;
1122 synthetize_setuw (insn);
1128 the_insn.reloc = BFD_RELOC_NONE;
1129 /* See if operand is absolute and small; skip sethi if so. */
1130 if (low32 < -(1 << 12))
1132 the_insn.opcode = (SETHI_INSN | RD (rd)
1133 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1134 output_insn (insn, &the_insn);
1135 low32 = 0x1c00 | (low32 & 0x3ff);
1136 opc = RS1 (rd) | XOR_INSN;
1139 the_insn.opcode = (opc | RD (rd) | IMMED
1140 | (low32 & 0x1fff));
1141 output_insn (insn, &the_insn);
1144 /* Handle the setsw synthetic instruction. */
1147 synthetize_setx (insn)
1148 const struct sparc_opcode *insn;
1150 int upper32, lower32;
1151 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1152 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1154 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1155 int need_xor10_p = 0;
1157 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1158 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1159 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1162 upper_dstreg = tmpreg;
1163 /* The tmp reg should not be the dst reg. */
1164 if (tmpreg == dstreg)
1165 as_warn (_("setx: temporary register same as destination register"));
1167 /* ??? Obviously there are other optimizations we can do
1168 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1169 doing some of these. Later. If you do change things, try to
1170 change all of this to be table driven as well. */
1171 /* What to output depends on the number if it's constant.
1172 Compute that first, then output what we've decided upon. */
1173 if (the_insn.exp.X_op != O_constant)
1175 if (sparc_arch_size == 32)
1177 /* When arch size is 32, we want setx to be equivalent
1178 to setuw for anything but constants. */
1179 the_insn.exp.X_add_number &= 0xffffffff;
1180 synthetize_setuw (insn);
1183 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1189 /* Reset X_add_number, we've extracted it as upper32/lower32.
1190 Otherwise fixup_segment will complain about not being able to
1191 write an 8 byte number in a 4 byte field. */
1192 the_insn.exp.X_add_number = 0;
1194 /* Only need hh22 if `or' insn can't handle constant. */
1195 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1198 /* Does bottom part (after sethi) have bits? */
1199 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1200 /* No hh22, but does upper32 still have bits we can't set
1202 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1205 /* If the lower half is all zero, we build the upper half directly
1206 into the dst reg. */
1208 /* Need lower half if number is zero or 0xffffffff00000000. */
1209 || (! need_hh22_p && ! need_hm10_p))
1211 /* No need for sethi if `or' insn can handle constant. */
1212 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1213 /* Note that we can't use a negative constant in the `or'
1214 insn unless the upper 32 bits are all ones. */
1215 || (lower32 < 0 && upper32 != -1)
1216 || (lower32 >= 0 && upper32 == -1))
1219 if (need_hi22_p && upper32 == -1)
1222 /* Does bottom part (after sethi) have bits? */
1223 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1225 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1226 /* Need `or' if we didn't set anything else. */
1227 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1231 /* Output directly to dst reg if lower 32 bits are all zero. */
1232 upper_dstreg = dstreg;
1235 if (!upper_dstreg && dstreg)
1236 as_warn (_("setx: illegal temporary register g0"));
1240 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1241 | ((upper32 >> 10) & 0x3fffff));
1242 the_insn.reloc = (the_insn.exp.X_op != O_constant
1243 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1244 output_insn (insn, &the_insn);
1249 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1250 | (((need_xor10_p ? ~lower32 : lower32)
1251 >> 10) & 0x3fffff));
1252 the_insn.reloc = (the_insn.exp.X_op != O_constant
1253 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1254 output_insn (insn, &the_insn);
1259 the_insn.opcode = (OR_INSN
1260 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1263 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1264 the_insn.reloc = (the_insn.exp.X_op != O_constant
1265 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1266 output_insn (insn, &the_insn);
1271 /* FIXME: One nice optimization to do here is to OR the low part
1272 with the highpart if hi22 isn't needed and the low part is
1274 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1277 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1278 the_insn.reloc = (the_insn.exp.X_op != O_constant
1279 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1280 output_insn (insn, &the_insn);
1283 /* If we needed to build the upper part, shift it into place. */
1284 if (need_hh22_p || need_hm10_p)
1286 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1288 the_insn.reloc = BFD_RELOC_NONE;
1289 output_insn (insn, &the_insn);
1292 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1295 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1296 | 0x1c00 | (lower32 & 0x3ff));
1297 the_insn.reloc = BFD_RELOC_NONE;
1298 output_insn (insn, &the_insn);
1301 /* If we needed to build both upper and lower parts, OR them together. */
1302 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1304 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1306 the_insn.reloc = BFD_RELOC_NONE;
1307 output_insn (insn, &the_insn);
1311 /* Main entry point to assemble one instruction. */
1317 const struct sparc_opcode *insn;
1321 special_case = sparc_ip (str, &insn);
1325 /* We warn about attempts to put a floating point branch in a delay slot,
1326 unless the delay slot has been annulled. */
1327 if (last_insn != NULL
1328 && (insn->flags & F_FBR) != 0
1329 && (last_insn->flags & F_DELAYED) != 0
1330 /* ??? This test isn't completely accurate. We assume anything with
1331 F_{UNBR,CONDBR,FBR} set is annullable. */
1332 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1333 || (last_opcode & ANNUL) == 0))
1334 as_warn (_("FP branch in delay slot"));
1336 /* SPARC before v9 requires a nop instruction between a floating
1337 point instruction and a floating point branch. We insert one
1338 automatically, with a warning. */
1339 if (max_architecture < SPARC_OPCODE_ARCH_V9
1340 && last_insn != NULL
1341 && (insn->flags & F_FBR) != 0
1342 && (last_insn->flags & F_FLOAT) != 0)
1344 struct sparc_it nop_insn;
1346 nop_insn.opcode = NOP_INSN;
1347 nop_insn.reloc = BFD_RELOC_NONE;
1348 output_insn (insn, &nop_insn);
1349 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1352 switch (special_case)
1354 case SPECIAL_CASE_NONE:
1356 output_insn (insn, &the_insn);
1359 case SPECIAL_CASE_SETSW:
1360 synthetize_setsw (insn);
1363 case SPECIAL_CASE_SET:
1364 synthetize_setuw (insn);
1367 case SPECIAL_CASE_SETX:
1368 synthetize_setx (insn);
1371 case SPECIAL_CASE_FDIV:
1373 int rd = (the_insn.opcode >> 25) & 0x1f;
1375 output_insn (insn, &the_insn);
1377 /* According to information leaked from Sun, the "fdiv" instructions
1378 on early SPARC machines would produce incorrect results sometimes.
1379 The workaround is to add an fmovs of the destination register to
1380 itself just after the instruction. This was true on machines
1381 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1382 assert (the_insn.reloc == BFD_RELOC_NONE);
1383 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1384 output_insn (insn, &the_insn);
1389 as_fatal (_("failed special case insn sanity check"));
1393 /* Subroutine of md_assemble to do the actual parsing. */
1396 sparc_ip (str, pinsn)
1398 const struct sparc_opcode **pinsn;
1400 char *error_message = "";
1404 const struct sparc_opcode *insn;
1406 unsigned long opcode;
1407 unsigned int mask = 0;
1411 int special_case = SPECIAL_CASE_NONE;
1418 while (ISLOWER (*s) || ISDIGIT (*s));
1435 as_bad (_("Unknown opcode: `%s'"), str);
1437 return special_case;
1439 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1443 as_bad (_("Unknown opcode: `%s'"), str);
1444 return special_case;
1454 opcode = insn->match;
1455 memset (&the_insn, '\0', sizeof (the_insn));
1456 the_insn.reloc = BFD_RELOC_NONE;
1459 /* Build the opcode, checking as we go to make sure that the
1461 for (args = insn->args;; ++args)
1469 /* Parse a series of masks. */
1476 if (! parse_keyword_arg (sparc_encode_membar, &s,
1479 error_message = _(": invalid membar mask name");
1485 if (*s == '|' || *s == '+')
1493 if (! parse_const_expr_arg (&s, &kmask))
1495 error_message = _(": invalid membar mask expression");
1498 if (kmask < 0 || kmask > 127)
1500 error_message = _(": invalid membar mask number");
1505 opcode |= MEMBAR (kmask);
1513 if (! parse_const_expr_arg (&s, &smask))
1515 error_message = _(": invalid siam mode expression");
1518 if (smask < 0 || smask > 7)
1520 error_message = _(": invalid siam mode number");
1531 /* Parse a prefetch function. */
1534 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1536 error_message = _(": invalid prefetch function name");
1542 if (! parse_const_expr_arg (&s, &fcn))
1544 error_message = _(": invalid prefetch function expression");
1547 if (fcn < 0 || fcn > 31)
1549 error_message = _(": invalid prefetch function number");
1559 /* Parse a sparc64 privileged register. */
1562 struct priv_reg_entry *p = priv_reg_table;
1563 unsigned int len = 9999999; /* Init to make gcc happy. */
1566 while (p->name[0] > s[0])
1568 while (p->name[0] == s[0])
1570 len = strlen (p->name);
1571 if (strncmp (p->name, s, len) == 0)
1575 if (p->name[0] != s[0])
1577 error_message = _(": unrecognizable privileged register");
1581 opcode |= (p->regnum << 14);
1583 opcode |= (p->regnum << 25);
1589 error_message = _(": unrecognizable privileged register");
1595 /* Parse a sparc64 hyperprivileged register. */
1598 struct priv_reg_entry *p = hpriv_reg_table;
1599 unsigned int len = 9999999; /* Init to make gcc happy. */
1602 while (p->name[0] > s[0])
1604 while (p->name[0] == s[0])
1606 len = strlen (p->name);
1607 if (strncmp (p->name, s, len) == 0)
1611 if (p->name[0] != s[0])
1613 error_message = _(": unrecognizable hyperprivileged register");
1617 opcode |= (p->regnum << 14);
1619 opcode |= (p->regnum << 25);
1625 error_message = _(": unrecognizable hyperprivileged register");
1631 /* Parse a v9a/v9b ancillary state register. */
1634 struct priv_reg_entry *p = v9a_asr_table;
1635 unsigned int len = 9999999; /* Init to make gcc happy. */
1638 while (p->name[0] > s[0])
1640 while (p->name[0] == s[0])
1642 len = strlen (p->name);
1643 if (strncmp (p->name, s, len) == 0)
1647 if (p->name[0] != s[0])
1649 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1652 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1654 error_message = _(": rd on write only ancillary state register");
1658 && (insn->architecture
1659 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1661 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1662 error_message = _(": unrecognizable v9a ancillary state register");
1666 opcode |= (p->regnum << 14);
1668 opcode |= (p->regnum << 25);
1674 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1680 if (strncmp (s, "%asr", 4) == 0)
1688 while (ISDIGIT (*s))
1690 num = num * 10 + *s - '0';
1694 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1696 if (num < 16 || 31 < num)
1698 error_message = _(": asr number must be between 16 and 31");
1704 if (num < 0 || 31 < num)
1706 error_message = _(": asr number must be between 0 and 31");
1711 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1716 error_message = _(": expecting %asrN");
1723 the_insn.reloc = BFD_RELOC_SPARC_11;
1727 the_insn.reloc = BFD_RELOC_SPARC_10;
1731 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1732 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1733 the_insn.reloc = BFD_RELOC_SPARC_5;
1735 the_insn.reloc = BFD_RELOC_SPARC13;
1736 /* These fields are unsigned, but for upward compatibility,
1737 allow negative values as well. */
1741 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1742 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1743 the_insn.reloc = BFD_RELOC_SPARC_6;
1745 the_insn.reloc = BFD_RELOC_SPARC13;
1746 /* These fields are unsigned, but for upward compatibility,
1747 allow negative values as well. */
1751 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1756 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1761 if (*s == 'p' && s[1] == 'n')
1769 if (*s == 'p' && s[1] == 't')
1781 if (strncmp (s, "%icc", 4) == 0)
1793 if (strncmp (s, "%xcc", 4) == 0)
1805 if (strncmp (s, "%fcc0", 5) == 0)
1817 if (strncmp (s, "%fcc1", 5) == 0)
1829 if (strncmp (s, "%fcc2", 5) == 0)
1841 if (strncmp (s, "%fcc3", 5) == 0)
1849 if (strncmp (s, "%pc", 3) == 0)
1857 if (strncmp (s, "%tick", 5) == 0)
1864 case '\0': /* End of args. */
1865 if (s[0] == ',' && s[1] == '%')
1867 static const struct tls_ops {
1868 /* The name as it appears in assembler. */
1870 /* strlen (name), precomputed for speed */
1872 /* The reloc this pseudo-op translates to. */
1877 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1878 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1879 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1880 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1881 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1882 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1883 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1884 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
1886 const struct tls_ops *o;
1890 for (o = tls_ops; o->name; o++)
1891 if (strncmp (s + 2, o->name, o->len) == 0)
1893 if (o->name == NULL)
1896 if (s[o->len + 2] != '(')
1898 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1899 return special_case;
1902 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
1904 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1906 return special_case;
1910 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1911 || the_insn.exp.X_add_number != 0
1912 || the_insn.exp.X_add_symbol
1913 != symbol_find_or_make ("__tls_get_addr")))
1915 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1917 return special_case;
1920 the_insn.reloc = o->reloc;
1921 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1924 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1927 else if (*s1 == ')')
1936 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1937 return special_case;
1941 (void) get_expression (s);
1961 case '[': /* These must match exactly. */
1969 case '#': /* Must be at least one digit. */
1972 while (ISDIGIT (*s))
1980 case 'C': /* Coprocessor state register. */
1981 if (strncmp (s, "%csr", 4) == 0)
1988 case 'b': /* Next operand is a coprocessor register. */
1991 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1996 mask = 10 * (mask - '0') + (*s++ - '0');
2010 opcode |= mask << 14;
2018 opcode |= mask << 25;
2024 case 'r': /* next operand must be a register */
2034 case 'f': /* frame pointer */
2042 case 'g': /* global register */
2051 case 'i': /* in register */
2055 mask = c - '0' + 24;
2060 case 'l': /* local register */
2064 mask = (c - '0' + 16);
2069 case 'o': /* out register */
2073 mask = (c - '0' + 8);
2078 case 's': /* stack pointer */
2086 case 'r': /* any register */
2087 if (!ISDIGIT ((c = *s++)))
2104 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2120 if ((mask & ~1) == 2 && sparc_arch_size == 64
2121 && no_undeclared_regs && ! globals[mask])
2122 as_bad (_("detected global register use not covered by .register pseudo-op"));
2124 /* Got the register, now figure out where
2125 it goes in the opcode. */
2129 opcode |= mask << 14;
2137 opcode |= mask << 25;
2141 opcode |= (mask << 25) | (mask << 14);
2145 opcode |= (mask << 25) | (mask << 0);
2151 case 'e': /* next operand is a floating point register */
2166 && ((format = *s) == 'f')
2169 for (mask = 0; ISDIGIT (*s); ++s)
2171 mask = 10 * mask + (*s - '0');
2172 } /* read the number */
2180 } /* register must be even numbered */
2188 } /* register must be multiple of 4 */
2192 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2193 error_message = _(": There are only 64 f registers; [0-63]");
2195 error_message = _(": There are only 32 f registers; [0-31]");
2198 else if (mask >= 32)
2200 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2202 if (*args == 'e' || *args == 'f' || *args == 'g')
2205 = _(": There are only 32 single precision f registers; [0-31]");
2209 mask -= 31; /* wrap high bit */
2213 error_message = _(": There are only 32 f registers; [0-31]");
2221 } /* if not an 'f' register. */
2228 opcode |= RS1 (mask);
2234 opcode |= RS2 (mask);
2240 opcode |= RD (mask);
2249 if (strncmp (s, "%fsr", 4) == 0)
2256 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2257 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2260 case 'l': /* 22 bit PC relative immediate */
2261 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2265 case 'L': /* 30 bit immediate */
2266 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2271 case 'n': /* 22 bit immediate */
2272 the_insn.reloc = BFD_RELOC_SPARC22;
2275 case 'i': /* 13 bit immediate */
2276 the_insn.reloc = BFD_RELOC_SPARC13;
2286 char *op_arg = NULL;
2287 static expressionS op_exp;
2288 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2290 /* Check for %hi, etc. */
2293 static const struct ops {
2294 /* The name as it appears in assembler. */
2296 /* strlen (name), precomputed for speed */
2298 /* The reloc this pseudo-op translates to. */
2300 /* Non-zero if for v9 only. */
2302 /* Non-zero if can be used in pc-relative contexts. */
2303 int pcrel_p;/*FIXME:wip*/
2305 /* hix/lox must appear before hi/lo so %hix won't be
2306 mistaken for %hi. */
2307 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2308 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2309 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2310 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2311 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2312 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2313 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2314 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2315 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2316 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2317 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2318 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2331 { NULL, 0, 0, 0, 0 }
2333 const struct ops *o;
2335 for (o = ops; o->name; o++)
2336 if (strncmp (s + 1, o->name, o->len) == 0)
2338 if (o->name == NULL)
2341 if (s[o->len + 1] != '(')
2343 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2344 return special_case;
2348 the_insn.reloc = o->reloc;
2353 /* Note that if the get_expression() fails, we will still
2354 have created U entries in the symbol table for the
2355 'symbols' in the input string. Try not to create U
2356 symbols for registers, etc. */
2358 /* This stuff checks to see if the expression ends in
2359 +%reg. If it does, it removes the register from
2360 the expression, and re-sets 's' to point to the
2367 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2370 else if (*s1 == ')')
2379 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2380 return special_case;
2384 (void) get_expression (s);
2387 if (*s == ',' || *s == ']' || !*s)
2389 if (*s != '+' && *s != '-')
2391 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2392 return special_case;
2396 op_exp = the_insn.exp;
2397 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2400 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2403 if (s1 != s && ISDIGIT (s1[-1]))
2405 if (s1[-2] == '%' && s1[-3] == '+')
2407 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2414 if (op_arg && s1 == s + 1)
2415 the_insn.exp.X_op = O_absent;
2417 (void) get_expression (s);
2429 (void) get_expression (s);
2437 the_insn.exp2 = the_insn.exp;
2438 the_insn.exp = op_exp;
2439 if (the_insn.exp2.X_op == O_absent)
2440 the_insn.exp2.X_op = O_illegal;
2441 else if (the_insn.exp.X_op == O_absent)
2443 the_insn.exp = the_insn.exp2;
2444 the_insn.exp2.X_op = O_illegal;
2446 else if (the_insn.exp.X_op == O_constant)
2448 valueT val = the_insn.exp.X_add_number;
2449 switch (the_insn.reloc)
2454 case BFD_RELOC_SPARC_HH22:
2455 val = BSR (val, 32);
2458 case BFD_RELOC_SPARC_LM22:
2459 case BFD_RELOC_HI22:
2460 val = (val >> 10) & 0x3fffff;
2463 case BFD_RELOC_SPARC_HM10:
2464 val = BSR (val, 32);
2467 case BFD_RELOC_LO10:
2471 case BFD_RELOC_SPARC_H44:
2476 case BFD_RELOC_SPARC_M44:
2481 case BFD_RELOC_SPARC_L44:
2485 case BFD_RELOC_SPARC_HIX22:
2487 val = (val >> 10) & 0x3fffff;
2490 case BFD_RELOC_SPARC_LOX10:
2491 val = (val & 0x3ff) | 0x1c00;
2494 the_insn.exp = the_insn.exp2;
2495 the_insn.exp.X_add_number += val;
2496 the_insn.exp2.X_op = O_illegal;
2497 the_insn.reloc = old_reloc;
2499 else if (the_insn.exp2.X_op != O_constant)
2501 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2502 return special_case;
2506 if (old_reloc != BFD_RELOC_SPARC13
2507 || the_insn.reloc != BFD_RELOC_LO10
2508 || sparc_arch_size != 64
2511 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2512 return special_case;
2514 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2518 /* Check for constants that don't require emitting a reloc. */
2519 if (the_insn.exp.X_op == O_constant
2520 && the_insn.exp.X_add_symbol == 0
2521 && the_insn.exp.X_op_symbol == 0)
2523 /* For pc-relative call instructions, we reject
2524 constants to get better code. */
2526 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2527 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2529 error_message = _(": PC-relative operand can't be a constant");
2533 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2534 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2536 error_message = _(": TLS operand can't be a constant");
2540 /* Constants that won't fit are checked in md_apply_fix
2541 and bfd_install_relocation.
2542 ??? It would be preferable to install the constants
2543 into the insn here and save having to create a fixS
2544 for each one. There already exists code to handle
2545 all the various cases (e.g. in md_apply_fix and
2546 bfd_install_relocation) so duplicating all that code
2547 here isn't right. */
2567 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2569 error_message = _(": invalid ASI name");
2575 if (! parse_const_expr_arg (&s, &asi))
2577 error_message = _(": invalid ASI expression");
2580 if (asi < 0 || asi > 255)
2582 error_message = _(": invalid ASI number");
2586 opcode |= ASI (asi);
2588 } /* Alternate space. */
2591 if (strncmp (s, "%psr", 4) == 0)
2598 case 'q': /* Floating point queue. */
2599 if (strncmp (s, "%fq", 3) == 0)
2606 case 'Q': /* Coprocessor queue. */
2607 if (strncmp (s, "%cq", 3) == 0)
2615 if (strcmp (str, "set") == 0
2616 || strcmp (str, "setuw") == 0)
2618 special_case = SPECIAL_CASE_SET;
2621 else if (strcmp (str, "setsw") == 0)
2623 special_case = SPECIAL_CASE_SETSW;
2626 else if (strcmp (str, "setx") == 0)
2628 special_case = SPECIAL_CASE_SETX;
2631 else if (strncmp (str, "fdiv", 4) == 0)
2633 special_case = SPECIAL_CASE_FDIV;
2639 if (strncmp (s, "%asi", 4) != 0)
2645 if (strncmp (s, "%fprs", 5) != 0)
2651 if (strncmp (s, "%ccr", 4) != 0)
2657 if (strncmp (s, "%tbr", 4) != 0)
2663 if (strncmp (s, "%wim", 4) != 0)
2670 char *push = input_line_pointer;
2673 input_line_pointer = s;
2675 if (e.X_op == O_constant)
2677 int n = e.X_add_number;
2678 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2679 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2681 opcode |= e.X_add_number << 5;
2684 as_bad (_("non-immediate OPF operand, ignored"));
2685 s = input_line_pointer;
2686 input_line_pointer = push;
2691 if (strncmp (s, "%y", 2) != 0)
2699 /* Parse a sparclet cpreg. */
2701 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2703 error_message = _(": invalid cpreg name");
2706 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2711 as_fatal (_("failed sanity check."));
2712 } /* switch on arg code. */
2714 /* Break out of for() loop. */
2716 } /* For each arg that we expect. */
2721 /* Args don't match. */
2722 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2723 && (insn->name == insn[1].name
2724 || !strcmp (insn->name, insn[1].name)))
2732 as_bad (_("Illegal operands%s"), error_message);
2733 return special_case;
2738 /* We have a match. Now see if the architecture is OK. */
2739 int needed_arch_mask = insn->architecture;
2744 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2745 if (! needed_arch_mask)
2747 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2750 if (needed_arch_mask
2751 & SPARC_OPCODE_SUPPORTED (current_architecture))
2754 /* Can we bump up the architecture? */
2755 else if (needed_arch_mask
2756 & SPARC_OPCODE_SUPPORTED (max_architecture))
2758 enum sparc_opcode_arch_val needed_architecture =
2759 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2760 & needed_arch_mask);
2762 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2764 && needed_architecture > warn_after_architecture)
2766 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2767 sparc_opcode_archs[current_architecture].name,
2768 sparc_opcode_archs[needed_architecture].name,
2770 warn_after_architecture = needed_architecture;
2772 current_architecture = needed_architecture;
2775 /* ??? This seems to be a bit fragile. What if the next entry in
2776 the opcode table is the one we want and it is supported?
2777 It is possible to arrange the table today so that this can't
2778 happen but what about tomorrow? */
2781 int arch, printed_one_p = 0;
2783 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2785 /* Create a list of the architectures that support the insn. */
2786 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2788 arch = sparc_ffs (needed_arch_mask);
2789 while ((1 << arch) <= needed_arch_mask)
2791 if ((1 << arch) & needed_arch_mask)
2795 strcpy (p, sparc_opcode_archs[arch].name);
2802 as_bad (_("Architecture mismatch on \"%s\"."), str);
2803 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2805 sparc_opcode_archs[max_architecture].name);
2806 return special_case;
2808 } /* If no match. */
2811 } /* Forever looking for a match. */
2813 the_insn.opcode = opcode;
2814 return special_case;
2817 /* Parse an argument that can be expressed as a keyword.
2818 (eg: #StoreStore or %ccfr).
2819 The result is a boolean indicating success.
2820 If successful, INPUT_POINTER is updated. */
2823 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2824 int (*lookup_fn) PARAMS ((const char *));
2825 char **input_pointerP;
2831 p = *input_pointerP;
2832 for (q = p + (*p == '#' || *p == '%');
2833 ISALNUM (*q) || *q == '_';
2838 value = (*lookup_fn) (p);
2843 *input_pointerP = q;
2847 /* Parse an argument that is a constant expression.
2848 The result is a boolean indicating success. */
2851 parse_const_expr_arg (input_pointerP, valueP)
2852 char **input_pointerP;
2855 char *save = input_line_pointer;
2858 input_line_pointer = *input_pointerP;
2859 /* The next expression may be something other than a constant
2860 (say if we're not processing the right variant of the insn).
2861 Don't call expression unless we're sure it will succeed as it will
2862 signal an error (which we want to defer until later). */
2863 /* FIXME: It might be better to define md_operand and have it recognize
2864 things like %asi, etc. but continuing that route through to the end
2865 is a lot of work. */
2866 if (*input_line_pointer == '%')
2868 input_line_pointer = save;
2872 *input_pointerP = input_line_pointer;
2873 input_line_pointer = save;
2874 if (exp.X_op != O_constant)
2876 *valueP = exp.X_add_number;
2880 /* Subroutine of sparc_ip to parse an expression. */
2883 get_expression (str)
2889 save_in = input_line_pointer;
2890 input_line_pointer = str;
2891 seg = expression (&the_insn.exp);
2892 if (seg != absolute_section
2893 && seg != text_section
2894 && seg != data_section
2895 && seg != bss_section
2896 && seg != undefined_section)
2898 the_insn.error = _("bad segment");
2899 expr_end = input_line_pointer;
2900 input_line_pointer = save_in;
2903 expr_end = input_line_pointer;
2904 input_line_pointer = save_in;
2908 /* Subroutine of md_assemble to output one insn. */
2911 output_insn (insn, the_insn)
2912 const struct sparc_opcode *insn;
2913 struct sparc_it *the_insn;
2915 char *toP = frag_more (4);
2917 /* Put out the opcode. */
2918 if (INSN_BIG_ENDIAN)
2919 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2921 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2923 /* Put out the symbol-dependent stuff. */
2924 if (the_insn->reloc != BFD_RELOC_NONE)
2926 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2927 (toP - frag_now->fr_literal), /* Where. */
2932 /* Turn off overflow checking in fixup_segment. We'll do our
2933 own overflow checking in md_apply_fix. This is necessary because
2934 the insn size is 4 and fixup_segment will signal an overflow for
2935 large 8 byte quantities. */
2936 fixP->fx_no_overflow = 1;
2937 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2938 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2942 last_opcode = the_insn->opcode;
2945 dwarf2_emit_insn (4);
2949 /* This is identical to the md_atof in m68k.c. I think this is right,
2952 Turn a string in input_line_pointer into a floating point constant
2953 of type TYPE, and store the appropriate bytes in *LITP. The number
2954 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2955 returned, or NULL on OK. */
2957 /* Equal to MAX_PRECISION in atof-ieee.c. */
2958 #define MAX_LITTLENUMS 6
2961 md_atof (type, litP, sizeP)
2967 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2998 return _("Bad call to MD_ATOF()");
3001 t = atof_ieee (input_line_pointer, type, words);
3003 input_line_pointer = t;
3004 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3006 if (target_big_endian)
3008 for (i = 0; i < prec; i++)
3010 md_number_to_chars (litP, (valueT) words[i],
3011 sizeof (LITTLENUM_TYPE));
3012 litP += sizeof (LITTLENUM_TYPE);
3017 for (i = prec - 1; i >= 0; i--)
3019 md_number_to_chars (litP, (valueT) words[i],
3020 sizeof (LITTLENUM_TYPE));
3021 litP += sizeof (LITTLENUM_TYPE);
3028 /* Write a value out to the object file, using the appropriate
3032 md_number_to_chars (buf, val, n)
3037 if (target_big_endian)
3038 number_to_chars_bigendian (buf, val, n);
3039 else if (target_little_endian_data
3040 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3041 /* Output debug words, which are not in allocated sections, as big
3043 number_to_chars_bigendian (buf, val, n);
3044 else if (target_little_endian_data || ! target_big_endian)
3045 number_to_chars_littleendian (buf, val, n);
3048 /* Apply a fixS to the frags, now that we know the value it ought to
3052 md_apply_fix3 (fixP, valP, segment)
3055 segT segment ATTRIBUTE_UNUSED;
3057 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3058 offsetT val = * (offsetT *) valP;
3061 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3063 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3066 /* SPARC ELF relocations don't use an addend in the data field. */
3067 if (fixP->fx_addsy != NULL)
3069 switch (fixP->fx_r_type)
3071 case BFD_RELOC_SPARC_TLS_GD_HI22:
3072 case BFD_RELOC_SPARC_TLS_GD_LO10:
3073 case BFD_RELOC_SPARC_TLS_GD_ADD:
3074 case BFD_RELOC_SPARC_TLS_GD_CALL:
3075 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3076 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3077 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3078 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3079 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3080 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3081 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3082 case BFD_RELOC_SPARC_TLS_IE_HI22:
3083 case BFD_RELOC_SPARC_TLS_IE_LO10:
3084 case BFD_RELOC_SPARC_TLS_IE_LD:
3085 case BFD_RELOC_SPARC_TLS_IE_LDX:
3086 case BFD_RELOC_SPARC_TLS_IE_ADD:
3087 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3088 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3089 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3090 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3091 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3092 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3093 case BFD_RELOC_SPARC_TLS_TPOFF32:
3094 case BFD_RELOC_SPARC_TLS_TPOFF64:
3095 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3105 /* This is a hack. There should be a better way to
3106 handle this. Probably in terms of howto fields, once
3107 we can look at these fixups in terms of howtos. */
3108 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3109 val += fixP->fx_where + fixP->fx_frag->fr_address;
3112 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3113 generate a reloc, then we just want to let the reloc addend set
3114 the value. We do not want to also stuff the addend into the
3115 object file. Including the addend in the object file works when
3116 doing a static link, because the linker will ignore the object
3117 file contents. However, the dynamic linker does not ignore the
3118 object file contents. */
3119 if (fixP->fx_addsy != NULL
3120 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3123 /* When generating PIC code, we do not want an addend for a reloc
3124 against a local symbol. We adjust fx_addnumber to cancel out the
3125 value already included in val, and to also cancel out the
3126 adjustment which bfd_install_relocation will create. */
3128 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3129 && fixP->fx_addsy != NULL
3130 && ! S_IS_COMMON (fixP->fx_addsy)
3131 && symbol_section_p (fixP->fx_addsy))
3132 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3134 /* When generating PIC code, we need to fiddle to get
3135 bfd_install_relocation to do the right thing for a PC relative
3136 reloc against a local symbol which we are going to keep. */
3138 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3139 && fixP->fx_addsy != NULL
3140 && (S_IS_EXTERNAL (fixP->fx_addsy)
3141 || S_IS_WEAK (fixP->fx_addsy))
3142 && S_IS_DEFINED (fixP->fx_addsy)
3143 && ! S_IS_COMMON (fixP->fx_addsy))
3146 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3150 /* If this is a data relocation, just output VAL. */
3152 if (fixP->fx_r_type == BFD_RELOC_16
3153 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3155 md_number_to_chars (buf, val, 2);
3157 else if (fixP->fx_r_type == BFD_RELOC_32
3158 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3159 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3161 md_number_to_chars (buf, val, 4);
3163 else if (fixP->fx_r_type == BFD_RELOC_64
3164 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3166 md_number_to_chars (buf, val, 8);
3168 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3169 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3176 /* It's a relocation against an instruction. */
3178 if (INSN_BIG_ENDIAN)
3179 insn = bfd_getb32 ((unsigned char *) buf);
3181 insn = bfd_getl32 ((unsigned char *) buf);
3183 switch (fixP->fx_r_type)
3185 case BFD_RELOC_32_PCREL_S2:
3187 /* FIXME: This increment-by-one deserves a comment of why it's
3189 if (! sparc_pic_code
3190 || fixP->fx_addsy == NULL
3191 || symbol_section_p (fixP->fx_addsy))
3194 insn |= val & 0x3fffffff;
3196 /* See if we have a delay slot. */
3197 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3201 #define XCC (2 << 20)
3202 #define COND(x) (((x)&0xf)<<25)
3203 #define CONDA COND(0x8)
3204 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3205 #define INSN_BA (F2(0,2) | CONDA)
3206 #define INSN_OR F3(2, 0x2, 0)
3207 #define INSN_NOP F2(0,4)
3211 /* If the instruction is a call with either:
3213 arithmetic instruction with rd == %o7
3214 where rs1 != %o7 and rs2 if it is register != %o7
3215 then we can optimize if the call destination is near
3216 by changing the call into a branch always. */
3217 if (INSN_BIG_ENDIAN)
3218 delay = bfd_getb32 ((unsigned char *) buf + 4);
3220 delay = bfd_getl32 ((unsigned char *) buf + 4);
3221 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3223 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3224 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3225 || ((delay & RD (~0)) != RD (O7))))
3227 if ((delay & RS1 (~0)) == RS1 (O7)
3228 || ((delay & F3I (~0)) == 0
3229 && (delay & RS2 (~0)) == RS2 (O7)))
3231 /* Ensure the branch will fit into simm22. */
3232 if ((val & 0x3fe00000)
3233 && (val & 0x3fe00000) != 0x3fe00000)
3235 /* Check if the arch is v9 and branch will fit
3237 if (((val & 0x3c0000) == 0
3238 || (val & 0x3c0000) == 0x3c0000)
3239 && (sparc_arch_size == 64
3240 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3242 insn = INSN_BPA | (val & 0x7ffff);
3245 insn = INSN_BA | (val & 0x3fffff);
3246 if (fixP->fx_where >= 4
3247 && ((delay & (0xffffffff ^ RS1 (~0)))
3248 == (INSN_OR | RD (O7) | RS2 (G0))))
3253 if (INSN_BIG_ENDIAN)
3254 setter = bfd_getb32 ((unsigned char *) buf - 4);
3256 setter = bfd_getl32 ((unsigned char *) buf - 4);
3257 if ((setter & (0xffffffff ^ RD (~0)))
3258 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3265 If call foo was replaced with ba, replace
3266 or %rN, %g0, %o7 with nop. */
3267 reg = (delay & RS1 (~0)) >> 14;
3268 if (reg != ((setter & RD (~0)) >> 25)
3269 || reg == G0 || reg == O7)
3272 if (INSN_BIG_ENDIAN)
3273 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3275 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3280 case BFD_RELOC_SPARC_11:
3281 if (! in_signed_range (val, 0x7ff))
3282 as_bad_where (fixP->fx_file, fixP->fx_line,
3283 _("relocation overflow"));
3284 insn |= val & 0x7ff;
3287 case BFD_RELOC_SPARC_10:
3288 if (! in_signed_range (val, 0x3ff))
3289 as_bad_where (fixP->fx_file, fixP->fx_line,
3290 _("relocation overflow"));
3291 insn |= val & 0x3ff;
3294 case BFD_RELOC_SPARC_7:
3295 if (! in_bitfield_range (val, 0x7f))
3296 as_bad_where (fixP->fx_file, fixP->fx_line,
3297 _("relocation overflow"));
3301 case BFD_RELOC_SPARC_6:
3302 if (! in_bitfield_range (val, 0x3f))
3303 as_bad_where (fixP->fx_file, fixP->fx_line,
3304 _("relocation overflow"));
3308 case BFD_RELOC_SPARC_5:
3309 if (! in_bitfield_range (val, 0x1f))
3310 as_bad_where (fixP->fx_file, fixP->fx_line,
3311 _("relocation overflow"));
3315 case BFD_RELOC_SPARC_WDISP16:
3316 /* FIXME: simplify. */
3317 if (((val > 0) && (val & ~0x3fffc))
3318 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3319 as_bad_where (fixP->fx_file, fixP->fx_line,
3320 _("relocation overflow"));
3321 /* FIXME: The +1 deserves a comment. */
3322 val = (val >> 2) + 1;
3323 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3326 case BFD_RELOC_SPARC_WDISP19:
3327 /* FIXME: simplify. */
3328 if (((val > 0) && (val & ~0x1ffffc))
3329 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3330 as_bad_where (fixP->fx_file, fixP->fx_line,
3331 _("relocation overflow"));
3332 /* FIXME: The +1 deserves a comment. */
3333 val = (val >> 2) + 1;
3334 insn |= val & 0x7ffff;
3337 case BFD_RELOC_SPARC_HH22:
3338 val = BSR (val, 32);
3341 case BFD_RELOC_SPARC_LM22:
3342 case BFD_RELOC_HI22:
3343 if (!fixP->fx_addsy)
3344 insn |= (val >> 10) & 0x3fffff;
3346 /* FIXME: Need comment explaining why we do this. */
3350 case BFD_RELOC_SPARC22:
3351 if (val & ~0x003fffff)
3352 as_bad_where (fixP->fx_file, fixP->fx_line,
3353 _("relocation overflow"));
3354 insn |= (val & 0x3fffff);
3357 case BFD_RELOC_SPARC_HM10:
3358 val = BSR (val, 32);
3361 case BFD_RELOC_LO10:
3362 if (!fixP->fx_addsy)
3363 insn |= val & 0x3ff;
3365 /* FIXME: Need comment explaining why we do this. */
3369 case BFD_RELOC_SPARC_OLO10:
3371 val += fixP->tc_fix_data;
3374 case BFD_RELOC_SPARC13:
3375 if (! in_signed_range (val, 0x1fff))
3376 as_bad_where (fixP->fx_file, fixP->fx_line,
3377 _("relocation overflow"));
3378 insn |= val & 0x1fff;
3381 case BFD_RELOC_SPARC_WDISP22:
3382 val = (val >> 2) + 1;
3384 case BFD_RELOC_SPARC_BASE22:
3385 insn |= val & 0x3fffff;
3388 case BFD_RELOC_SPARC_H44:
3389 if (!fixP->fx_addsy)
3393 insn |= tval & 0x3fffff;
3397 case BFD_RELOC_SPARC_M44:
3398 if (!fixP->fx_addsy)
3399 insn |= (val >> 12) & 0x3ff;
3402 case BFD_RELOC_SPARC_L44:
3403 if (!fixP->fx_addsy)
3404 insn |= val & 0xfff;
3407 case BFD_RELOC_SPARC_HIX22:
3408 if (!fixP->fx_addsy)
3410 val ^= ~(offsetT) 0;
3411 insn |= (val >> 10) & 0x3fffff;
3415 case BFD_RELOC_SPARC_LOX10:
3416 if (!fixP->fx_addsy)
3417 insn |= 0x1c00 | (val & 0x3ff);
3420 case BFD_RELOC_NONE:
3422 as_bad_where (fixP->fx_file, fixP->fx_line,
3423 _("bad or unhandled relocation type: 0x%02x"),
3428 if (INSN_BIG_ENDIAN)
3429 bfd_putb32 (insn, (unsigned char *) buf);
3431 bfd_putl32 (insn, (unsigned char *) buf);
3434 /* Are we finished with this relocation now? */
3435 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3439 /* Translate internal representation of relocation info to BFD target
3443 tc_gen_reloc (section, fixp)
3444 asection *section ATTRIBUTE_UNUSED;
3447 static arelent *relocs[3];
3449 bfd_reloc_code_real_type code;
3451 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3454 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3455 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3456 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3458 switch (fixp->fx_r_type)
3462 case BFD_RELOC_HI22:
3463 case BFD_RELOC_LO10:
3464 case BFD_RELOC_32_PCREL_S2:
3465 case BFD_RELOC_SPARC13:
3466 case BFD_RELOC_SPARC22:
3467 case BFD_RELOC_SPARC_BASE13:
3468 case BFD_RELOC_SPARC_WDISP16:
3469 case BFD_RELOC_SPARC_WDISP19:
3470 case BFD_RELOC_SPARC_WDISP22:
3472 case BFD_RELOC_SPARC_5:
3473 case BFD_RELOC_SPARC_6:
3474 case BFD_RELOC_SPARC_7:
3475 case BFD_RELOC_SPARC_10:
3476 case BFD_RELOC_SPARC_11:
3477 case BFD_RELOC_SPARC_HH22:
3478 case BFD_RELOC_SPARC_HM10:
3479 case BFD_RELOC_SPARC_LM22:
3480 case BFD_RELOC_SPARC_PC_HH22:
3481 case BFD_RELOC_SPARC_PC_HM10:
3482 case BFD_RELOC_SPARC_PC_LM22:
3483 case BFD_RELOC_SPARC_H44:
3484 case BFD_RELOC_SPARC_M44:
3485 case BFD_RELOC_SPARC_L44:
3486 case BFD_RELOC_SPARC_HIX22:
3487 case BFD_RELOC_SPARC_LOX10:
3488 case BFD_RELOC_SPARC_REV32:
3489 case BFD_RELOC_SPARC_OLO10:
3490 case BFD_RELOC_SPARC_UA16:
3491 case BFD_RELOC_SPARC_UA32:
3492 case BFD_RELOC_SPARC_UA64:
3493 case BFD_RELOC_8_PCREL:
3494 case BFD_RELOC_16_PCREL:
3495 case BFD_RELOC_32_PCREL:
3496 case BFD_RELOC_64_PCREL:
3497 case BFD_RELOC_SPARC_PLT32:
3498 case BFD_RELOC_SPARC_PLT64:
3499 case BFD_RELOC_VTABLE_ENTRY:
3500 case BFD_RELOC_VTABLE_INHERIT:
3501 case BFD_RELOC_SPARC_TLS_GD_HI22:
3502 case BFD_RELOC_SPARC_TLS_GD_LO10:
3503 case BFD_RELOC_SPARC_TLS_GD_ADD:
3504 case BFD_RELOC_SPARC_TLS_GD_CALL:
3505 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3506 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3507 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3508 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3509 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3510 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3511 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3512 case BFD_RELOC_SPARC_TLS_IE_HI22:
3513 case BFD_RELOC_SPARC_TLS_IE_LO10:
3514 case BFD_RELOC_SPARC_TLS_IE_LD:
3515 case BFD_RELOC_SPARC_TLS_IE_LDX:
3516 case BFD_RELOC_SPARC_TLS_IE_ADD:
3517 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3518 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3519 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3520 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3521 code = fixp->fx_r_type;
3528 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3529 /* If we are generating PIC code, we need to generate a different
3533 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3535 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3538 #define GOTT_BASE "__GOTT_BASE__"
3539 #define GOTT_INDEX "__GOTT_INDEX__"
3542 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3548 case BFD_RELOC_32_PCREL_S2:
3549 if (generic_force_reloc (fixp))
3550 code = BFD_RELOC_SPARC_WPLT30;
3552 case BFD_RELOC_HI22:
3553 code = BFD_RELOC_SPARC_GOT22;
3554 if (fixp->fx_addsy != NULL)
3556 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3557 code = BFD_RELOC_SPARC_PC22;
3559 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3560 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3561 code = BFD_RELOC_HI22; /* Unchanged. */
3565 case BFD_RELOC_LO10:
3566 code = BFD_RELOC_SPARC_GOT10;
3567 if (fixp->fx_addsy != NULL)
3569 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3570 code = BFD_RELOC_SPARC_PC10;
3572 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3573 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3574 code = BFD_RELOC_LO10; /* Unchanged. */
3578 case BFD_RELOC_SPARC13:
3579 code = BFD_RELOC_SPARC_GOT13;
3585 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3587 if (code == BFD_RELOC_SPARC_OLO10)
3588 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3590 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3591 if (reloc->howto == 0)
3593 as_bad_where (fixp->fx_file, fixp->fx_line,
3594 _("internal error: can't export reloc type %d (`%s')"),
3595 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3601 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3604 if (reloc->howto->pc_relative == 0
3605 || code == BFD_RELOC_SPARC_PC10
3606 || code == BFD_RELOC_SPARC_PC22)
3607 reloc->addend = fixp->fx_addnumber;
3608 else if (sparc_pic_code
3609 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3610 && fixp->fx_addsy != NULL
3611 && (S_IS_EXTERNAL (fixp->fx_addsy)
3612 || S_IS_WEAK (fixp->fx_addsy))
3613 && S_IS_DEFINED (fixp->fx_addsy)
3614 && ! S_IS_COMMON (fixp->fx_addsy))
3615 reloc->addend = fixp->fx_addnumber;
3617 reloc->addend = fixp->fx_offset - reloc->address;
3619 #else /* elf or coff */
3621 if (code != BFD_RELOC_32_PCREL_S2
3622 && code != BFD_RELOC_SPARC_WDISP22
3623 && code != BFD_RELOC_SPARC_WDISP16
3624 && code != BFD_RELOC_SPARC_WDISP19
3625 && code != BFD_RELOC_SPARC_WPLT30
3626 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3627 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3628 reloc->addend = fixp->fx_addnumber;
3629 else if (symbol_section_p (fixp->fx_addsy))
3630 reloc->addend = (section->vma
3631 + fixp->fx_addnumber
3632 + md_pcrel_from (fixp));
3634 reloc->addend = fixp->fx_offset;
3637 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3638 on the same location. */
3639 if (code == BFD_RELOC_SPARC_OLO10)
3641 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3644 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3646 = symbol_get_bfdsym (section_symbol (absolute_section));
3647 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3648 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3649 reloc->addend = fixp->tc_fix_data;
3655 /* We have no need to default values of symbols. */
3658 md_undefined_symbol (name)
3659 char *name ATTRIBUTE_UNUSED;
3664 /* Round up a section size to the appropriate boundary. */
3667 md_section_align (segment, size)
3668 segT segment ATTRIBUTE_UNUSED;
3672 /* This is not right for ELF; a.out wants it, and COFF will force
3673 the alignment anyways. */
3674 valueT align = ((valueT) 1
3675 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3678 /* Turn alignment value into a mask. */
3680 newsize = (size + align) & ~align;
3687 /* Exactly what point is a PC-relative offset relative TO?
3688 On the sparc, they're relative to the address of the offset, plus
3689 its size. This gets us to the following instruction.
3690 (??? Is this right? FIXME-SOON) */
3692 md_pcrel_from (fixP)
3697 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3698 if (! sparc_pic_code
3699 || fixP->fx_addsy == NULL
3700 || symbol_section_p (fixP->fx_addsy))
3701 ret += fixP->fx_size;
3705 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3717 for (shift = 0; (value & 1) == 0; value >>= 1)
3720 return (value == 1) ? shift : -1;
3723 /* Sort of like s_lcomm. */
3726 static int max_alignment = 15;
3731 int ignore ATTRIBUTE_UNUSED;
3741 name = input_line_pointer;
3742 c = get_symbol_end ();
3743 p = input_line_pointer;
3747 if (*input_line_pointer != ',')
3749 as_bad (_("Expected comma after name"));
3750 ignore_rest_of_line ();
3754 ++input_line_pointer;
3756 if ((size = get_absolute_expression ()) < 0)
3758 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3759 ignore_rest_of_line ();
3764 symbolP = symbol_find_or_make (name);
3767 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3768 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3770 as_bad (_("bad .reserve segment -- expected BSS segment"));
3774 if (input_line_pointer[2] == '.')
3775 input_line_pointer += 7;
3777 input_line_pointer += 6;
3780 if (*input_line_pointer == ',')
3782 ++input_line_pointer;
3785 if (*input_line_pointer == '\n')
3787 as_bad (_("missing alignment"));
3788 ignore_rest_of_line ();
3792 align = (int) get_absolute_expression ();
3795 if (align > max_alignment)
3797 align = max_alignment;
3798 as_warn (_("alignment too large; assuming %d"), align);
3804 as_bad (_("negative alignment"));
3805 ignore_rest_of_line ();
3811 temp = mylog2 (align);
3814 as_bad (_("alignment not a power of 2"));
3815 ignore_rest_of_line ();
3822 record_alignment (bss_section, align);
3827 if (!S_IS_DEFINED (symbolP)
3829 && S_GET_OTHER (symbolP) == 0
3830 && S_GET_DESC (symbolP) == 0
3837 segT current_seg = now_seg;
3838 subsegT current_subseg = now_subseg;
3840 /* Switch to bss. */
3841 subseg_set (bss_section, 1);
3845 frag_align (align, 0, 0);
3847 /* Detach from old frag. */
3848 if (S_GET_SEGMENT (symbolP) == bss_section)
3849 symbol_get_frag (symbolP)->fr_symbol = NULL;
3851 symbol_set_frag (symbolP, frag_now);
3852 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3853 (offsetT) size, (char *) 0);
3856 S_SET_SEGMENT (symbolP, bss_section);
3858 subseg_set (current_seg, current_subseg);
3861 S_SET_SIZE (symbolP, size);
3867 as_warn ("Ignoring attempt to re-define symbol %s",
3868 S_GET_NAME (symbolP));
3869 } /* if not redefining. */
3871 demand_empty_rest_of_line ();
3876 int ignore ATTRIBUTE_UNUSED;
3884 name = input_line_pointer;
3885 c = get_symbol_end ();
3886 /* Just after name is now '\0'. */
3887 p = input_line_pointer;
3890 if (*input_line_pointer != ',')
3892 as_bad (_("Expected comma after symbol-name"));
3893 ignore_rest_of_line ();
3898 input_line_pointer++;
3900 if ((temp = get_absolute_expression ()) < 0)
3902 as_bad (_(".COMMon length (%lu) out of range ignored"),
3903 (unsigned long) temp);
3904 ignore_rest_of_line ();
3909 symbolP = symbol_find_or_make (name);
3911 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3913 as_bad (_("Ignoring attempt to re-define symbol"));
3914 ignore_rest_of_line ();
3917 if (S_GET_VALUE (symbolP) != 0)
3919 if (S_GET_VALUE (symbolP) != (valueT) size)
3921 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3922 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3928 S_SET_VALUE (symbolP, (valueT) size);
3929 S_SET_EXTERNAL (symbolP);
3932 know (symbol_get_frag (symbolP) == &zero_address_frag);
3933 if (*input_line_pointer != ',')
3935 as_bad (_("Expected comma after common length"));
3936 ignore_rest_of_line ();
3939 input_line_pointer++;
3941 if (*input_line_pointer != '"')
3943 temp = get_absolute_expression ();
3946 if (temp > max_alignment)
3948 temp = max_alignment;
3949 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3955 as_bad (_("negative alignment"));
3956 ignore_rest_of_line ();
3961 if (symbol_get_obj (symbolP)->local)
3969 old_subsec = now_subseg;
3974 align = mylog2 (temp);
3978 as_bad (_("alignment not a power of 2"));
3979 ignore_rest_of_line ();
3983 record_alignment (bss_section, align);
3984 subseg_set (bss_section, 0);
3986 frag_align (align, 0, 0);
3987 if (S_GET_SEGMENT (symbolP) == bss_section)
3988 symbol_get_frag (symbolP)->fr_symbol = 0;
3989 symbol_set_frag (symbolP, frag_now);
3990 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3991 (offsetT) size, (char *) 0);
3993 S_SET_SEGMENT (symbolP, bss_section);
3994 S_CLEAR_EXTERNAL (symbolP);
3995 S_SET_SIZE (symbolP, size);
3996 subseg_set (old_sec, old_subsec);
3999 #endif /* OBJ_ELF */
4002 S_SET_VALUE (symbolP, (valueT) size);
4004 S_SET_ALIGN (symbolP, temp);
4005 S_SET_SIZE (symbolP, size);
4007 S_SET_EXTERNAL (symbolP);
4008 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4013 input_line_pointer++;
4014 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4015 if (*input_line_pointer == '.')
4016 input_line_pointer++;
4017 /* @@ Some say data, some say bss. */
4018 if (strncmp (input_line_pointer, "bss\"", 4)
4019 && strncmp (input_line_pointer, "data\"", 5))
4021 while (*--input_line_pointer != '"')
4023 input_line_pointer--;
4024 goto bad_common_segment;
4026 while (*input_line_pointer++ != '"')
4028 goto allocate_common;
4031 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4033 demand_empty_rest_of_line ();
4038 p = input_line_pointer;
4039 while (*p && *p != '\n')
4043 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4045 input_line_pointer = p;
4046 ignore_rest_of_line ();
4051 /* Handle the .empty pseudo-op. This suppresses the warnings about
4052 invalid delay slot usage. */
4056 int ignore ATTRIBUTE_UNUSED;
4058 /* The easy way to implement is to just forget about the last
4065 int ignore ATTRIBUTE_UNUSED;
4068 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4070 input_line_pointer += 6;
4074 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4076 input_line_pointer += 6;
4080 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4082 input_line_pointer += 7;
4086 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4088 input_line_pointer += 5;
4089 /* We only support 2 segments -- text and data -- for now, so
4090 things in the "bss segment" will have to go into data for now.
4091 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4092 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4095 as_bad (_("Unknown segment type"));
4096 demand_empty_rest_of_line ();
4102 subseg_set (data_section, 1);
4103 demand_empty_rest_of_line ();
4108 int ignore ATTRIBUTE_UNUSED;
4110 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4112 ++input_line_pointer;
4114 ++input_line_pointer;
4117 /* This static variable is set by s_uacons to tell sparc_cons_align
4118 that the expression does not need to be aligned. */
4120 static int sparc_no_align_cons = 0;
4122 /* This static variable is set by sparc_cons to emit requested types
4123 of relocations in cons_fix_new_sparc. */
4125 static const char *sparc_cons_special_reloc;
4127 /* This handles the unaligned space allocation pseudo-ops, such as
4128 .uaword. .uaword is just like .word, but the value does not need
4135 /* Tell sparc_cons_align not to align this value. */
4136 sparc_no_align_cons = 1;
4138 sparc_no_align_cons = 0;
4141 /* This handles the native word allocation pseudo-op .nword.
4142 For sparc_arch_size 32 it is equivalent to .word, for
4143 sparc_arch_size 64 it is equivalent to .xword. */
4147 int bytes ATTRIBUTE_UNUSED;
4149 cons (sparc_arch_size == 32 ? 4 : 8);
4153 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4157 .register %g[2367],{#scratch|symbolname|#ignore}
4162 int ignore ATTRIBUTE_UNUSED;
4167 const char *regname;
4169 if (input_line_pointer[0] != '%'
4170 || input_line_pointer[1] != 'g'
4171 || ((input_line_pointer[2] & ~1) != '2'
4172 && (input_line_pointer[2] & ~1) != '6')
4173 || input_line_pointer[3] != ',')
4174 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4175 reg = input_line_pointer[2] - '0';
4176 input_line_pointer += 4;
4178 if (*input_line_pointer == '#')
4180 ++input_line_pointer;
4181 regname = input_line_pointer;
4182 c = get_symbol_end ();
4183 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4184 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4185 if (regname[0] == 'i')
4192 regname = input_line_pointer;
4193 c = get_symbol_end ();
4195 if (sparc_arch_size == 64)
4199 if ((regname && globals[reg] != (symbolS *) 1
4200 && strcmp (S_GET_NAME (globals[reg]), regname))
4201 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4202 as_bad (_("redefinition of global register"));
4206 if (regname == NULL)
4207 globals[reg] = (symbolS *) 1;
4212 if (symbol_find (regname))
4213 as_bad (_("Register symbol %s already defined."),
4216 globals[reg] = symbol_make (regname);
4217 flags = symbol_get_bfdsym (globals[reg])->flags;
4219 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4220 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4221 flags |= BSF_GLOBAL;
4222 symbol_get_bfdsym (globals[reg])->flags = flags;
4223 S_SET_VALUE (globals[reg], (valueT) reg);
4224 S_SET_ALIGN (globals[reg], reg);
4225 S_SET_SIZE (globals[reg], 0);
4226 /* Although we actually want undefined_section here,
4227 we have to use absolute_section, because otherwise
4228 generic as code will make it a COM section.
4229 We fix this up in sparc_adjust_symtab. */
4230 S_SET_SEGMENT (globals[reg], absolute_section);
4231 S_SET_OTHER (globals[reg], 0);
4232 elf_symbol (symbol_get_bfdsym (globals[reg]))
4233 ->internal_elf_sym.st_info =
4234 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4235 elf_symbol (symbol_get_bfdsym (globals[reg]))
4236 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4241 *input_line_pointer = c;
4243 demand_empty_rest_of_line ();
4246 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4247 symbols which need it. */
4250 sparc_adjust_symtab ()
4254 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4256 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4257 ->internal_elf_sym.st_info) != STT_REGISTER)
4260 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4261 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4264 S_SET_SEGMENT (sym, undefined_section);
4269 /* If the --enforce-aligned-data option is used, we require .word,
4270 et. al., to be aligned correctly. We do it by setting up an
4271 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4272 no unexpected alignment was introduced.
4274 The SunOS and Solaris native assemblers enforce aligned data by
4275 default. We don't want to do that, because gcc can deliberately
4276 generate misaligned data if the packed attribute is used. Instead,
4277 we permit misaligned data by default, and permit the user to set an
4278 option to check for it. */
4281 sparc_cons_align (nbytes)
4287 /* Only do this if we are enforcing aligned data. */
4288 if (! enforce_aligned_data)
4291 /* Don't align if this is an unaligned pseudo-op. */
4292 if (sparc_no_align_cons)
4295 nalign = mylog2 (nbytes);
4299 assert (nalign > 0);
4301 if (now_seg == absolute_section)
4303 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4304 as_bad (_("misaligned data"));
4308 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4309 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4311 record_alignment (now_seg, nalign);
4314 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4317 sparc_handle_align (fragp)
4323 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4325 switch (fragp->fr_type)
4329 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4333 p = fragp->fr_literal + fragp->fr_fix;
4344 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4346 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4347 if (INSN_BIG_ENDIAN)
4348 number_to_chars_bigendian (p, wval, 4);
4350 number_to_chars_littleendian (p, wval, 4);
4356 if (INSN_BIG_ENDIAN)
4357 number_to_chars_bigendian (p, 0x01000000, 4);
4359 number_to_chars_littleendian (p, 0x01000000, 4);
4361 fragp->fr_fix += fix;
4371 /* Some special processing for a Sparc ELF file. */
4374 sparc_elf_final_processing ()
4376 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4377 sort of BFD interface for this. */
4378 if (sparc_arch_size == 64)
4380 switch (sparc_memory_model)
4383 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4386 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4392 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4393 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4394 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4395 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4396 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4397 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4401 sparc_cons (exp, size)
4408 sparc_cons_special_reloc = NULL;
4409 save = input_line_pointer;
4410 if (input_line_pointer[0] == '%'
4411 && input_line_pointer[1] == 'r'
4412 && input_line_pointer[2] == '_')
4414 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4416 input_line_pointer += 7;
4417 sparc_cons_special_reloc = "disp";
4419 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4421 if (size != 4 && size != 8)
4422 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4425 input_line_pointer += 6;
4426 sparc_cons_special_reloc = "plt";
4429 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4431 if (size != 4 && size != 8)
4432 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4435 input_line_pointer += 13;
4436 sparc_cons_special_reloc = "tls_dtpoff";
4439 if (sparc_cons_special_reloc)
4446 if (*input_line_pointer != '8')
4448 input_line_pointer--;
4451 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4455 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4459 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4469 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4470 sparc_cons_special_reloc, size * 8, size);
4474 input_line_pointer += 2;
4475 if (*input_line_pointer != '(')
4477 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4478 sparc_cons_special_reloc, size * 8);
4485 input_line_pointer = save;
4486 sparc_cons_special_reloc = NULL;
4491 char *end = ++input_line_pointer;
4494 while (! is_end_of_line[(c = *end)])
4508 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4509 sparc_cons_special_reloc, size * 8);
4515 if (input_line_pointer != end)
4517 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4518 sparc_cons_special_reloc, size * 8);
4522 input_line_pointer++;
4524 c = *input_line_pointer;
4525 if (! is_end_of_line[c] && c != ',')
4526 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4527 sparc_cons_special_reloc, size * 8);
4533 if (sparc_cons_special_reloc == NULL)
4539 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4540 reloc for a cons. We could use the definition there, except that
4541 we want to handle little endian relocs specially. */
4544 cons_fix_new_sparc (frag, where, nbytes, exp)
4547 unsigned int nbytes;
4550 bfd_reloc_code_real_type r;
4552 r = (nbytes == 1 ? BFD_RELOC_8 :
4553 (nbytes == 2 ? BFD_RELOC_16 :
4554 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4556 if (target_little_endian_data
4558 && now_seg->flags & SEC_ALLOC)
4559 r = BFD_RELOC_SPARC_REV32;
4561 if (sparc_cons_special_reloc)
4563 if (*sparc_cons_special_reloc == 'd')
4566 case 1: r = BFD_RELOC_8_PCREL; break;
4567 case 2: r = BFD_RELOC_16_PCREL; break;
4568 case 4: r = BFD_RELOC_32_PCREL; break;
4569 case 8: r = BFD_RELOC_64_PCREL; break;
4572 else if (*sparc_cons_special_reloc == 'p')
4575 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4576 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4581 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4582 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4585 else if (sparc_no_align_cons)
4589 case 2: r = BFD_RELOC_SPARC_UA16; break;
4590 case 4: r = BFD_RELOC_SPARC_UA32; break;
4591 case 8: r = BFD_RELOC_SPARC_UA64; break;
4596 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4597 sparc_cons_special_reloc = NULL;
4601 sparc_cfi_frame_initial_instructions ()
4603 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4607 sparc_regname_to_dw2regnum (const char *regname)
4615 p = strchr (q, regname[0]);
4618 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4620 return (p - q) * 8 + regname[1] - '0';
4622 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4624 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4626 if (regname[0] == 'f' || regname[0] == 'r')
4628 unsigned int regnum;
4630 regnum = strtoul (regname + 1, &q, 10);
4633 if (regnum >= ((regname[0] == 'f'
4634 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4637 if (regname[0] == 'f')
4640 if (regnum >= 64 && (regnum & 1))
4649 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4651 sparc_cons_special_reloc = "disp";
4652 sparc_no_align_cons = 1;
4653 emit_expr (exp, nbytes);
4654 sparc_no_align_cons = 0;
4655 sparc_cons_special_reloc = NULL;