1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
48 class Inst <string p, string t, Op o> {
55 // Used to generate Builtins.def
56 class SInst<string p, string t> : Inst<p, t, OP_NONE> {}
57 class IInst<string p, string t> : Inst<p, t, OP_NONE> {}
58 class WInst<string p, string t> : Inst<p, t, OP_NONE> {}
60 // prototype: return (arg, arg, ...)
62 // t: best-fit integer (int/poly args)
63 // x: signed integer (int/float args)
64 // u: unsigned integer (int/float args)
65 // f: float (int args)
67 // w: double width elements, same num elts
68 // n: double width elements, half num elts
69 // h: half width elements, double num elts
70 // e: half width elements, double num elts, unsigned
73 // s: scalar of element type
74 // a: scalar of element type (splat to vector type)
75 // k: default elt width, double num elts
76 // #: array of default vectors
78 // c: const pointer type
93 ////////////////////////////////////////////////////////////////////////////////
95 def VADD : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
96 def VADDL : SInst<"wdd", "csiUcUsUi">;
97 def VADDW : SInst<"wwd", "csiUcUsUi">;
98 def VHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
99 def VRHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
100 def VQADD : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
101 def VADDHN : IInst<"dww", "csiUcUsUi">;
102 def VRADDHN : IInst<"dww", "csiUcUsUi">;
104 ////////////////////////////////////////////////////////////////////////////////
105 // E.3.2 Multiplication
106 def VMUL : Inst<"ddd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_MUL>;
107 def VMLA : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
108 def VMLAL : SInst<"wwdd", "csiUcUsUi">;
109 def VMLS : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
110 def VMLSL : SInst<"wwdd", "csiUcUsUi">;
111 def VQDMULH : SInst<"ddd", "siQsQi">;
112 def VQRDMULH : SInst<"ddd", "siQsQi">;
113 def VQDMLAL : SInst<"wwdd", "si">;
114 def VQDMLSL : SInst<"wwdd", "si">;
115 def VMULL : SInst<"wdd", "csiUcUsUiPc">;
116 def VQDMULL : SInst<"wdd", "si">;
118 ////////////////////////////////////////////////////////////////////////////////
120 def VSUB : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
121 def VSUBL : SInst<"wdd", "csiUcUsUi">;
122 def VSUBW : SInst<"wwd", "csiUcUsUi">;
123 def VQSUB : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
124 def VHSUB : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
125 def VSUBHN : IInst<"dww", "csiUcUsUi">;
126 def VRSUBHN : IInst<"dww", "csiUcUsUi">;
128 ////////////////////////////////////////////////////////////////////////////////
130 def VCEQ : Inst<"udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
131 def VCGE : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
132 def VCLE : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
133 def VCGT : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
134 def VCLT : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
135 def VCAGE : IInst<"udd", "fQf">;
136 def VCALE : IInst<"udd", "fQf">;
137 def VCAGT : IInst<"udd", "fQf">;
138 def VCALT : IInst<"udd", "fQf">;
139 def VTST : WInst<"udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
141 ////////////////////////////////////////////////////////////////////////////////
142 // E.3.5 Absolute Difference
143 def VABD : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
144 def VABDL : SInst<"wdd", "csiUcUsUi">;
145 def VABA : SInst<"dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
146 def VABAL : SInst<"wwdd", "csiUcUsUi">;
148 ////////////////////////////////////////////////////////////////////////////////
150 def VMAX : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
151 def VMIN : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
153 ////////////////////////////////////////////////////////////////////////////////
154 // E.3.7 Pairdise Addition
155 def VPADD : IInst<"ddd", "csiUcUsUif">;
156 def VPADDL : SInst<"nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
157 def VPADAL : SInst<"nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
159 ////////////////////////////////////////////////////////////////////////////////
160 // E.3.8-9 Folding Max/Min
161 def VPMAX : SInst<"ddd", "csiUcUsUif">;
162 def VPMIN : SInst<"ddd", "csiUcUsUif">;
164 ////////////////////////////////////////////////////////////////////////////////
165 // E.3.10 Reciprocal/Sqrt
166 def VRECPS : IInst<"ddd", "fQf">;
167 def VRSQRTS : IInst<"ddd", "fQf">;
169 ////////////////////////////////////////////////////////////////////////////////
170 // E.3.11 Shifts by signed variable
171 def VSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
172 def VQSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
173 def VRSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
174 def VQRSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
176 ////////////////////////////////////////////////////////////////////////////////
177 // E.3.12 Shifts by constant
179 def VSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
180 def VSHL_N : IInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
181 def VRSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
182 def VSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
183 def VRSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
184 def VQSHL_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
185 def VQSHLU_N : SInst<"udi", "csilQcQsQiQl">;
186 def VSHRN_N : IInst<"hki", "silUsUiUl">;
187 def VQSHRUN_N : SInst<"eki", "sil">;
188 def VQRSHRUN_N : SInst<"eki", "sil">;
189 def VQSHRN_N : SInst<"hki", "silUsUiUl">;
190 def VRSHRN_N : IInst<"hki", "silUsUiUl">;
191 def VQRSHRN_N : SInst<"hki", "silUsUiUl">;
192 def VSHLL_N : SInst<"wdi", "csiUcUsUi">;
194 ////////////////////////////////////////////////////////////////////////////////
195 // E.3.13 Shifts with insert
196 def VSRI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
197 def VSLI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
200 ////////////////////////////////////////////////////////////////////////////////
201 // E.3.14 Loads and stores of a single vector
202 def VLD1 : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
203 def VLD1_LANE : WInst<"dcdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
204 def VLD1_DUP : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
205 def VST1 : WInst<"vpd", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
206 def VST1_LANE : WInst<"vpdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
208 ////////////////////////////////////////////////////////////////////////////////
209 // E.3.15 Loads and stores of an N-element structure
210 def VLD2 : WInst<"2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
211 def VLD3 : WInst<"3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
212 def VLD4 : WInst<"4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
213 def VLD2_DUP : WInst<"2c", "UcUsUiUlcsilhfPcPs">;
214 def VLD3_DUP : WInst<"3c", "UcUsUiUlcsilhfPcPs">;
215 def VLD4_DUP : WInst<"4c", "UcUsUiUlcsilhfPcPs">;
216 def VLD2_LANE : WInst<"2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
217 def VLD3_LANE : WInst<"3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
218 def VLD4_LANE : WInst<"4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
219 def VST2 : WInst<"vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
220 def VST3 : WInst<"vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
221 def VST4 : WInst<"vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
222 def VST2_LANE : WInst<"vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
223 def VST3_LANE : WInst<"vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
224 def VST4_LANE : WInst<"vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
226 ////////////////////////////////////////////////////////////////////////////////
227 // E.3.16 Extract lanes from a vector
228 def VGET_LANE : IInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
230 ////////////////////////////////////////////////////////////////////////////////
231 // E.3.17 Set lanes within a vector
232 def VSET_LANE : IInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
234 ////////////////////////////////////////////////////////////////////////////////
235 // E.3.18 Initialize a vector from bit pattern
236 def VCREATE: Inst<"dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
238 ////////////////////////////////////////////////////////////////////////////////
239 // E.3.19 Set all lanes to same value
240 def VDUP_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
241 def VMOV_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
243 ////////////////////////////////////////////////////////////////////////////////
244 // E.3.20 Combining vectors
245 def VCOMBINE : Inst<"kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
247 ////////////////////////////////////////////////////////////////////////////////
248 // E.3.21 Splitting vectors
249 def VGET_HIGH : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_HI>;
250 def VGET_LOW : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_LO>;
252 ////////////////////////////////////////////////////////////////////////////////
253 // E.3.22 Converting vectors
254 def VCVT_S32 : SInst<"xd", "fQf">;
255 def VCVT_U32 : SInst<"ud", "fQf">;
256 def VCVT_F16 : SInst<"hk", "f">;
257 def VCVT_N_S32 : SInst<"xdi", "fQf">;
258 def VCVT_N_U32 : SInst<"udi", "fQf">;
259 def VCVT_F32 : SInst<"fd", "iUiQiQUi">;
260 def VCVT_F32_F16 : SInst<"kh", "f">;
261 def VCVT_N_F32 : SInst<"fdi", "iUiQiQUi">;
262 def VMOVN : IInst<"hk", "silUsUiUl">;
263 def VMOVL : SInst<"wd", "csiUcUsUi">;
264 def VQMOVN : SInst<"hk", "silUsUiUl">;
265 def VQMOVUN : SInst<"ek", "sil">;
267 ////////////////////////////////////////////////////////////////////////////////
268 // E.3.23-24 Table lookup, Extended table lookup
269 def VTBL1 : WInst<"ddt", "UccPc">;
270 def VTBL2 : WInst<"d2t", "UccPc">;
271 def VTBL3 : WInst<"d3t", "UccPc">;
272 def VTBL4 : WInst<"d4t", "UccPc">;
273 def VTBX1 : WInst<"dddt", "UccPc">;
274 def VTBX2 : WInst<"dd2t", "UccPc">;
275 def VTBX3 : WInst<"dd3t", "UccPc">;
276 def VTBX4 : WInst<"dd4t", "UccPc">;
278 ////////////////////////////////////////////////////////////////////////////////
279 // E.3.25 Operations with a scalar value
280 def VMLA_LANE : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
281 def VMLAL_LANE : SInst<"wwddi", "siUsUi">;
282 def VQDMLAL_LANE : SInst<"wwddi", "si">;
283 def VMLS_LANE : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
284 def VMLSL_LANE : SInst<"wwddi", "siUsUi">;
285 def VQDMLSL_LANE : SInst<"wwddi", "si">;
286 def VMUL_N : Inst<"dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
287 def VMULL_N : SInst<"wda", "siUsUi">;
288 def VMULL_LANE : SInst<"wddi", "siUsUi">;
289 def VQDMULL_N : SInst<"wda", "si">;
290 def VQDMULL_LANE : SInst<"wddi", "si">;
291 def VQDMULH_N : SInst<"dda", "siQsQi">;
292 def VQDMULH_LANE : SInst<"dddi", "siQsQi">;
293 def VQRDMULH_N : SInst<"dda", "siQsQi">;
294 def VQRDMULH_LANE : SInst<"dddi", "siQsQi">;
295 def VMLA_N : Inst<"ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
296 def VMLAL_N : SInst<"wwda", "siUsUi">;
297 def VQDMLAL_N : SInst<"wwda", "si">;
298 def VMLS_N : Inst<"ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
299 def VMLSL_N : SInst<"wwda", "siUsUi">;
300 def VQDMLSL_N : SInst<"wwda", "si">;
302 ////////////////////////////////////////////////////////////////////////////////
303 // E.3.26 Vector Extract
304 def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
306 ////////////////////////////////////////////////////////////////////////////////
307 // E.3.27 Reverse vector elements (sdap endianness)
308 def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", OP_REV64>;
309 def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>;
310 def VREV16 : Inst<"dd", "cUcPcQcQUcQPc", OP_REV16>;
312 ////////////////////////////////////////////////////////////////////////////////
313 // E.3.28 Other single operand arithmetic
314 def VABS : SInst<"dd", "csifQcQsQiQf">;
315 def VQABS : SInst<"dd", "csiQcQsQi">;
316 def VNEG : Inst<"dd", "csifQcQsQiQf", OP_NEG>;
317 def VQNEG : SInst<"dd", "csiQcQsQi">;
318 def VCLS : SInst<"dd", "csiQcQsQi">;
319 def VCLZ : IInst<"dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
320 def VCNT : WInst<"dd", "UccPcQUcQcQPc">;
321 def VRECPE : SInst<"dd", "fUiQfQUi">;
322 def VRSQRTE : SInst<"dd", "fUiQfQUi">;
324 ////////////////////////////////////////////////////////////////////////////////
325 // E.3.29 Logical operations
326 def VMVN : Inst<"dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
327 def VAND : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
328 def VORR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
329 def VEOR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
330 def VBIC : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
331 def VORN : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
332 def VBSL : Inst<"dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
334 ////////////////////////////////////////////////////////////////////////////////
335 // E.3.30 Transposition operations
336 def VTRN: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
337 def VZIP: WInst<"2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
338 def VUZP: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
340 ////////////////////////////////////////////////////////////////////////////////
341 // E.3.31 Vector reinterpret cast operations