1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
33 // RegAltNameIndex - The alternate name set to use for register operands of
34 // this register class when printing.
35 class RegAltNameIndex {
36 string Namespace = "";
38 def NoRegAltName : RegAltNameIndex;
40 // Register - You should define one instance of this class for each register
41 // in the target machine. String n will become the "name" of the register.
42 class Register<string n, list<string> altNames = []> {
43 string Namespace = "";
45 list<string> AltNames = altNames;
47 // Aliases - A list of registers that this register overlaps with. A read or
48 // modification of this register can potentially read or modify the aliased
50 list<Register> Aliases = [];
52 // SubRegs - A list of registers that are parts of this register. Note these
53 // are "immediate" sub-registers and the registers within the list do not
54 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
56 list<Register> SubRegs = [];
58 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
59 // to address it. Sub-sub-register indices are automatically inherited from
61 list<SubRegIndex> SubRegIndices = [];
63 // RegAltNameIndices - The alternate name indices which are valid for this
65 list<RegAltNameIndex> RegAltNameIndices = [];
67 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
68 // These values can be determined by locating the <target>.h file in the
69 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
70 // order of these names correspond to the enumeration used by gcc. A value of
71 // -1 indicates that the gcc number is undefined and -2 that register number
72 // is invalid for this mode/flavour.
73 list<int> DwarfNumbers = [];
75 // CostPerUse - Additional cost of instructions using this register compared
76 // to other registers in its class. The register allocator will try to
77 // minimize the number of instructions using a register with a CostPerUse.
78 // This is used by the x86-64 and ARM Thumb targets where some registers
79 // require larger instruction encodings.
82 // CoveredBySubRegs - When this bit is set, the value of this register is
83 // completely determined by the value of its sub-registers. For example, the
84 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
85 // covered by its sub-register AX.
86 bit CoveredBySubRegs = 0;
88 // HWEncoding - The target specific hardware encoding for this register.
89 bits<16> HWEncoding = 0;
92 // RegisterWithSubRegs - This can be used to define instances of Register which
93 // need to specify sub-registers.
94 // List "subregs" specifies which registers are sub-registers to this one. This
95 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
96 // This allows the code generator to be careful not to put two values with
97 // overlapping live ranges into registers which alias.
98 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
99 let SubRegs = subregs;
102 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
103 // of Operand's that are legal as type qualifiers in DAG patterns. This should
104 // only ever be used for defining multiclasses that are polymorphic over both
105 // RegisterClass's and other Operand's.
108 // RegisterClass - Now that all of the registers are defined, and aliases
109 // between registers are defined, specify which registers belong to which
110 // register classes. This also defines the default allocation order of
111 // registers by register allocators.
113 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
114 dag regList, RegAltNameIndex idx = NoRegAltName>
116 string Namespace = namespace;
118 // RegType - Specify the list ValueType of the registers in this register
119 // class. Note that all registers in a register class must have the same
120 // ValueTypes. This is a list because some targets permit storing different
121 // types in same register, for example vector values with 128-bit total size,
122 // but different count/size of items, like SSE on x86.
124 list<ValueType> RegTypes = regTypes;
126 // Size - Specify the spill size in bits of the registers. A default value of
127 // zero lets tablgen pick an appropriate size.
130 // Alignment - Specify the alignment required of the registers when they are
131 // stored or loaded to memory.
133 int Alignment = alignment;
135 // CopyCost - This value is used to specify the cost of copying a value
136 // between two registers in this register class. The default value is one
137 // meaning it takes a single instruction to perform the copying. A negative
138 // value means copying is extremely expensive or impossible.
141 // MemberList - Specify which registers are in this class. If the
142 // allocation_order_* method are not specified, this also defines the order of
143 // allocation used by the register allocator.
145 dag MemberList = regList;
147 // AltNameIndex - The alternate register name to use when printing operands
148 // of this register class. Every register in the register class must have
149 // a valid alternate name for the given index.
150 RegAltNameIndex altNameIndex = idx;
152 // isAllocatable - Specify that the register class can be used for virtual
153 // registers and register allocation. Some register classes are only used to
154 // model instruction operand constraints, and should have isAllocatable = 0.
155 bit isAllocatable = 1;
157 // AltOrders - List of alternative allocation orders. The default order is
158 // MemberList itself, and that is good enough for most targets since the
159 // register allocators automatically remove reserved registers and move
160 // callee-saved registers to the end.
161 list<dag> AltOrders = [];
163 // AltOrderSelect - The body of a function that selects the allocation order
164 // to use in a given machine function. The code will be inserted in a
165 // function like this:
167 // static inline unsigned f(const MachineFunction &MF) { ... }
169 // The function should return 0 to select the default order defined by
170 // MemberList, 1 to select the first AltOrders entry and so on.
171 code AltOrderSelect = [{}];
174 // The memberList in a RegisterClass is a dag of set operations. TableGen
175 // evaluates these set operations and expand them into register lists. These
176 // are the most common operation, see test/TableGen/SetTheory.td for more
177 // examples of what is possible:
179 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
180 // register class, or a sub-expression. This is also the way to simply list
183 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
185 // (and GPR, CSR) - Set intersection. All registers from the first set that are
186 // also in the second set.
188 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
189 // numbered registers. Takes an optional 4th operand which is a stride to use
190 // when generating the sequence.
192 // (shl GPR, 4) - Remove the first N elements.
194 // (trunc GPR, 4) - Truncate after the first N elements.
196 // (rotl GPR, 1) - Rotate N places to the left.
198 // (rotr GPR, 1) - Rotate N places to the right.
200 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
202 // (interleave A, B, ...) - Interleave the elements from each argument list.
204 // All of these operators work on ordered sets, not lists. That means
205 // duplicates are removed from sub-expressions.
207 // Set operators. The rest is defined in TargetSelectionDAG.td.
212 // RegisterTuples - Automatically generate super-registers by forming tuples of
213 // sub-registers. This is useful for modeling register sequence constraints
214 // with pseudo-registers that are larger than the architectural registers.
216 // The sub-register lists are zipped together:
218 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
220 // Generates the same registers as:
222 // let SubRegIndices = [sube, subo] in {
223 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
224 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
227 // The generated pseudo-registers inherit super-classes and fields from their
228 // first sub-register. Most fields from the Register class are inferred, and
229 // the AsmName and Dwarf numbers are cleared.
231 // RegisterTuples instances can be used in other set operations to form
232 // register classes and so on. This is the only way of using the generated
234 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
235 // SubRegs - N lists of registers to be zipped up. Super-registers are
236 // synthesized from the first element of each SubRegs list, the second
237 // element and so on.
238 list<dag> SubRegs = Regs;
240 // SubRegIndices - N SubRegIndex instances. This provides the names of the
241 // sub-registers in the synthesized super-registers.
242 list<SubRegIndex> SubRegIndices = Indices;
246 //===----------------------------------------------------------------------===//
247 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
248 // to the register numbering used by gcc and gdb. These values are used by a
249 // debug information writer to describe where values may be located during
251 class DwarfRegNum<list<int> Numbers> {
252 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
253 // These values can be determined by locating the <target>.h file in the
254 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
255 // order of these names correspond to the enumeration used by gcc. A value of
256 // -1 indicates that the gcc number is undefined and -2 that register number
257 // is invalid for this mode/flavour.
258 list<int> DwarfNumbers = Numbers;
261 // DwarfRegAlias - This class declares that a given register uses the same dwarf
262 // numbers as another one. This is useful for making it clear that the two
263 // registers do have the same number. It also lets us build a mapping
264 // from dwarf register number to llvm register.
265 class DwarfRegAlias<Register reg> {
266 Register DwarfAlias = reg;
269 //===----------------------------------------------------------------------===//
270 // Pull in the common support for scheduling
272 include "llvm/Target/TargetSchedule.td"
274 class Predicate; // Forward def
276 //===----------------------------------------------------------------------===//
277 // Instruction set description - These classes correspond to the C++ classes in
278 // the Target/TargetInstrInfo.h file.
281 string Namespace = "";
283 dag OutOperandList; // An dag containing the MI def operand list.
284 dag InOperandList; // An dag containing the MI use operand list.
285 string AsmString = ""; // The .s format to print the instruction with.
287 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
288 // otherwise, uninitialized.
291 // The follow state will eventually be inferred automatically from the
292 // instruction pattern.
294 list<Register> Uses = []; // Default to using no non-operand registers
295 list<Register> Defs = []; // Default to modifying no non-operand registers
297 // Predicates - List of predicates which will be turned into isel matching
299 list<Predicate> Predicates = [];
301 // Size - Size of encoded instruction, or zero if the size cannot be determined
305 // DecoderNamespace - The "namespace" in which this instruction exists, on
306 // targets like ARM which multiple ISA namespaces exist.
307 string DecoderNamespace = "";
309 // Code size, for instruction selection.
310 // FIXME: What does this actually mean?
313 // Added complexity passed onto matching pattern.
314 int AddedComplexity = 0;
316 // These bits capture information about the high-level semantics of the
318 bit isReturn = 0; // Is this instruction a return instruction?
319 bit isBranch = 0; // Is this instruction a branch instruction?
320 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
321 bit isCompare = 0; // Is this instruction a comparison instruction?
322 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
323 bit isBitcast = 0; // Is this instruction a bitcast instruction?
324 bit isBarrier = 0; // Can control flow fall through this instruction?
325 bit isCall = 0; // Is this instruction a call instruction?
326 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
327 bit mayLoad = 0; // Is it possible for this inst to read memory?
328 bit mayStore = 0; // Is it possible for this inst to write memory?
329 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
330 bit isCommutable = 0; // Is this 3 operand instruction commutable?
331 bit isTerminator = 0; // Is this part of the terminator for a basic block?
332 bit isReMaterializable = 0; // Is this instruction re-materializable?
333 bit isPredicable = 0; // Is this instruction predicable?
334 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
335 bit usesCustomInserter = 0; // Pseudo instr needing special help.
336 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
337 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
338 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
339 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
340 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
341 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
342 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
343 // If so, won't have encoding information for
344 // the [MC]CodeEmitter stuff.
346 // Side effect flags - When set, the flags have these meanings:
348 // hasSideEffects - The instruction has side effects that are not
349 // captured by any operands of the instruction or other flags.
351 // neverHasSideEffects - Set on an instruction with no pattern if it has no
353 bit hasSideEffects = 0;
354 bit neverHasSideEffects = 0;
356 // Is this instruction a "real" instruction (with a distinct machine
357 // encoding), or is it a pseudo instruction used for codegen modeling
359 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
360 // instructions can (and often do) still have encoding information
361 // associated with them. Once we've migrated all of them over to true
362 // pseudo-instructions that are lowered to real instructions prior to
363 // the printer/emitter, we can remove this attribute and just use isPseudo.
365 // The intended use is:
366 // isPseudo: Does not have encoding information and should be expanded,
367 // at the latest, during lowering to MCInst.
369 // isCodeGenOnly: Does have encoding information and can go through to the
370 // CodeEmitter unchanged, but duplicates a canonical instruction
371 // definition's encoding and should be ignored when constructing the
372 // assembler match tables.
373 bit isCodeGenOnly = 0;
375 // Is this instruction a pseudo instruction for use by the assembler parser.
376 bit isAsmParserOnly = 0;
378 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
380 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
382 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
383 /// be encoded into the output machineinstr.
384 string DisableEncoding = "";
386 string PostEncoderMethod = "";
387 string DecoderMethod = "";
389 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
390 bits<64> TSFlags = 0;
392 ///@name Assembler Parser Support
395 string AsmMatchConverter = "";
397 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
398 /// two-operand matcher inst-alias for a three operand instruction.
399 /// For example, the arm instruction "add r3, r3, r5" can be written
400 /// as "add r3, r5". The constraint is of the same form as a tied-operand
401 /// constraint. For example, "$Rn = $Rd".
402 string TwoOperandAliasConstraint = "";
407 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
408 /// Which instruction it expands to and how the operands map from the
410 class PseudoInstExpansion<dag Result> {
411 dag ResultInst = Result; // The instruction to generate.
415 /// Predicates - These are extra conditionals which are turned into instruction
416 /// selector matching code. Currently each predicate is just a string.
417 class Predicate<string cond> {
418 string CondString = cond;
420 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
421 /// matcher, this is true. Targets should set this by inheriting their
422 /// feature from the AssemblerPredicate class in addition to Predicate.
423 bit AssemblerMatcherPredicate = 0;
425 /// AssemblerCondString - Name of the subtarget feature being tested used
426 /// as alternative condition string used for assembler matcher.
427 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
428 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
429 /// It can also list multiple features separated by ",".
430 /// e.g. "ModeThumb,FeatureThumb2" is translated to
431 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
432 string AssemblerCondString = "";
434 /// PredicateName - User-level name to use for the predicate. Mainly for use
435 /// in diagnostics such as missing feature errors in the asm matcher.
436 string PredicateName = "";
439 /// NoHonorSignDependentRounding - This predicate is true if support for
440 /// sign-dependent-rounding is not enabled.
441 def NoHonorSignDependentRounding
442 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
444 class Requires<list<Predicate> preds> {
445 list<Predicate> Predicates = preds;
448 /// ops definition - This is just a simple marker used to identify the operand
449 /// list for an instruction. outs and ins are identical both syntactically and
450 /// semanticallyr; they are used to define def operands and use operands to
451 /// improve readibility. This should be used like this:
452 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
457 /// variable_ops definition - Mark this instruction as taking a variable number
462 /// PointerLikeRegClass - Values that are designed to have pointer width are
463 /// derived from this. TableGen treats the register class as having a symbolic
464 /// type that it doesn't know, and resolves the actual regclass to use by using
465 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
466 class PointerLikeRegClass<int Kind> {
467 int RegClassKind = Kind;
471 /// ptr_rc definition - Mark this operand as being a pointer value whose
472 /// register class is resolved dynamically via a callback to TargetInstrInfo.
473 /// FIXME: We should probably change this to a class which contain a list of
474 /// flags. But currently we have but one flag.
475 def ptr_rc : PointerLikeRegClass<0>;
477 /// unknown definition - Mark this operand as being of unknown type, causing
478 /// it to be resolved by inference in the context it is used.
481 /// AsmOperandClass - Representation for the kinds of operands which the target
482 /// specific parser can create and the assembly matcher may need to distinguish.
484 /// Operand classes are used to define the order in which instructions are
485 /// matched, to ensure that the instruction which gets matched for any
486 /// particular list of operands is deterministic.
488 /// The target specific parser must be able to classify a parsed operand into a
489 /// unique class which does not partially overlap with any other classes. It can
490 /// match a subset of some other class, in which case the super class field
491 /// should be defined.
492 class AsmOperandClass {
493 /// The name to use for this class, which should be usable as an enum value.
496 /// The super classes of this operand.
497 list<AsmOperandClass> SuperClasses = [];
499 /// The name of the method on the target specific operand to call to test
500 /// whether the operand is an instance of this class. If not set, this will
501 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
502 /// signature should be:
503 /// bool isFoo() const;
504 string PredicateMethod = ?;
506 /// The name of the method on the target specific operand to call to add the
507 /// target specific operand to an MCInst. If not set, this will default to
508 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
509 /// signature should be:
510 /// void addFooOperands(MCInst &Inst, unsigned N) const;
511 string RenderMethod = ?;
513 /// The name of the method on the target specific operand to call to custom
514 /// handle the operand parsing. This is useful when the operands do not relate
515 /// to immediates or registers and are very instruction specific (as flags to
516 /// set in a processor register, coprocessor number, ...).
517 string ParserMethod = ?;
519 // The diagnostic type to present when referencing this operand in a
520 // match failure error message. By default, use a generic "invalid operand"
521 // diagnostic. The target AsmParser maps these codes to text.
522 string DiagnosticType = "";
525 def ImmAsmOperand : AsmOperandClass {
529 /// Operand Types - These provide the built-in operand types that may be used
530 /// by a target. Targets can optionally provide their own operand types as
531 /// needed, though this should not be needed for RISC targets.
532 class Operand<ValueType ty> : DAGOperand {
534 string PrintMethod = "printOperand";
535 string EncoderMethod = "";
536 string DecoderMethod = "";
537 string AsmOperandLowerMethod = ?;
538 string OperandType = "OPERAND_UNKNOWN";
539 dag MIOperandInfo = (ops);
541 // ParserMatchClass - The "match class" that operands of this type fit
542 // in. Match classes are used to define the order in which instructions are
543 // match, to ensure that which instructions gets matched is deterministic.
545 // The target specific parser must be able to classify an parsed operand into
546 // a unique class, which does not partially overlap with any other classes. It
547 // can match a subset of some other class, in which case the AsmOperandClass
548 // should declare the other operand as one of its super classes.
549 AsmOperandClass ParserMatchClass = ImmAsmOperand;
552 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
554 // RegClass - The register class of the operand.
555 RegisterClass RegClass = regclass;
556 // PrintMethod - The target method to call to print register operands of
557 // this type. The method normally will just use an alt-name index to look
558 // up the name to print. Default to the generic printOperand().
559 string PrintMethod = pm;
560 // ParserMatchClass - The "match class" that operands of this type fit
561 // in. Match classes are used to define the order in which instructions are
562 // match, to ensure that which instructions gets matched is deterministic.
564 // The target specific parser must be able to classify an parsed operand into
565 // a unique class, which does not partially overlap with any other classes. It
566 // can match a subset of some other class, in which case the AsmOperandClass
567 // should declare the other operand as one of its super classes.
568 AsmOperandClass ParserMatchClass;
571 let OperandType = "OPERAND_IMMEDIATE" in {
572 def i1imm : Operand<i1>;
573 def i8imm : Operand<i8>;
574 def i16imm : Operand<i16>;
575 def i32imm : Operand<i32>;
576 def i64imm : Operand<i64>;
578 def f32imm : Operand<f32>;
579 def f64imm : Operand<f64>;
582 /// zero_reg definition - Special node to stand for the zero register.
586 /// PredicateOperand - This can be used to define a predicate operand for an
587 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
588 /// AlwaysVal specifies the value of this predicate when set to "always
590 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
592 let MIOperandInfo = OpTypes;
593 dag DefaultOps = AlwaysVal;
596 /// OptionalDefOperand - This is used to define a optional definition operand
597 /// for an instruction. DefaultOps is the register the operand represents if
598 /// none is supplied, e.g. zero_reg.
599 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
601 let MIOperandInfo = OpTypes;
602 dag DefaultOps = defaultops;
606 // InstrInfo - This class should only be instantiated once to provide parameters
607 // which are global to the target machine.
610 // Target can specify its instructions in either big or little-endian formats.
611 // For instance, while both Sparc and PowerPC are big-endian platforms, the
612 // Sparc manual specifies its instructions in the format [31..0] (big), while
613 // PowerPC specifies them using the format [0..31] (little).
614 bit isLittleEndianEncoding = 0;
617 // Standard Pseudo Instructions.
618 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
619 // Only these instructions are allowed in the TargetOpcode namespace.
620 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
621 def PHI : Instruction {
622 let OutOperandList = (outs);
623 let InOperandList = (ins variable_ops);
624 let AsmString = "PHINODE";
626 def INLINEASM : Instruction {
627 let OutOperandList = (outs);
628 let InOperandList = (ins variable_ops);
630 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
632 def PROLOG_LABEL : Instruction {
633 let OutOperandList = (outs);
634 let InOperandList = (ins i32imm:$id);
637 let isNotDuplicable = 1;
639 def EH_LABEL : Instruction {
640 let OutOperandList = (outs);
641 let InOperandList = (ins i32imm:$id);
644 let isNotDuplicable = 1;
646 def GC_LABEL : Instruction {
647 let OutOperandList = (outs);
648 let InOperandList = (ins i32imm:$id);
651 let isNotDuplicable = 1;
653 def KILL : Instruction {
654 let OutOperandList = (outs);
655 let InOperandList = (ins variable_ops);
657 let neverHasSideEffects = 1;
659 def EXTRACT_SUBREG : Instruction {
660 let OutOperandList = (outs unknown:$dst);
661 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
663 let neverHasSideEffects = 1;
665 def INSERT_SUBREG : Instruction {
666 let OutOperandList = (outs unknown:$dst);
667 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
669 let neverHasSideEffects = 1;
670 let Constraints = "$supersrc = $dst";
672 def IMPLICIT_DEF : Instruction {
673 let OutOperandList = (outs unknown:$dst);
674 let InOperandList = (ins);
676 let neverHasSideEffects = 1;
677 let isReMaterializable = 1;
678 let isAsCheapAsAMove = 1;
680 def SUBREG_TO_REG : Instruction {
681 let OutOperandList = (outs unknown:$dst);
682 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
684 let neverHasSideEffects = 1;
686 def COPY_TO_REGCLASS : Instruction {
687 let OutOperandList = (outs unknown:$dst);
688 let InOperandList = (ins unknown:$src, i32imm:$regclass);
690 let neverHasSideEffects = 1;
691 let isAsCheapAsAMove = 1;
693 def DBG_VALUE : Instruction {
694 let OutOperandList = (outs);
695 let InOperandList = (ins variable_ops);
696 let AsmString = "DBG_VALUE";
697 let neverHasSideEffects = 1;
699 def REG_SEQUENCE : Instruction {
700 let OutOperandList = (outs unknown:$dst);
701 let InOperandList = (ins variable_ops);
703 let neverHasSideEffects = 1;
704 let isAsCheapAsAMove = 1;
706 def COPY : Instruction {
707 let OutOperandList = (outs unknown:$dst);
708 let InOperandList = (ins unknown:$src);
710 let neverHasSideEffects = 1;
711 let isAsCheapAsAMove = 1;
713 def BUNDLE : Instruction {
714 let OutOperandList = (outs);
715 let InOperandList = (ins variable_ops);
716 let AsmString = "BUNDLE";
720 //===----------------------------------------------------------------------===//
721 // AsmParser - This class can be implemented by targets that wish to implement
724 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
725 // syntax on X86 for example).
728 // AsmParserClassName - This specifies the suffix to use for the asmparser
729 // class. Generated AsmParser classes are always prefixed with the target
731 string AsmParserClassName = "AsmParser";
733 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
734 // function of the AsmParser class to call on every matched instruction.
735 // This can be used to perform target specific instruction post-processing.
736 string AsmParserInstCleanup = "";
738 def DefaultAsmParser : AsmParser;
740 //===----------------------------------------------------------------------===//
741 // AsmParserVariant - Subtargets can have multiple different assembly parsers
742 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
743 // implemented by targets to describe such variants.
745 class AsmParserVariant {
746 // Variant - AsmParsers can be of multiple different variants. Variants are
747 // used to support targets that need to parser multiple formats for the
748 // assembly language.
751 // CommentDelimiter - If given, the delimiter string used to recognize
752 // comments which are hard coded in the .td assembler strings for individual
754 string CommentDelimiter = "";
756 // RegisterPrefix - If given, the token prefix which indicates a register
757 // token. This is used by the matcher to automatically recognize hard coded
758 // register tokens as constrained registers, instead of tokens, for the
759 // purposes of matching.
760 string RegisterPrefix = "";
762 def DefaultAsmParserVariant : AsmParserVariant;
764 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
765 /// matches instructions and aliases.
766 class AssemblerPredicate<string cond, string name = ""> {
767 bit AssemblerMatcherPredicate = 1;
768 string AssemblerCondString = cond;
769 string PredicateName = name;
772 /// TokenAlias - This class allows targets to define assembler token
773 /// operand aliases. That is, a token literal operand which is equivalent
774 /// to another, canonical, token literal. For example, ARM allows:
775 /// vmov.u32 s4, #0 -> vmov.i32, #0
776 /// 'u32' is a more specific designator for the 32-bit integer type specifier
777 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
778 /// def : TokenAlias<".u32", ".i32">;
780 /// This works by marking the match class of 'From' as a subclass of the
781 /// match class of 'To'.
782 class TokenAlias<string From, string To> {
783 string FromToken = From;
787 /// MnemonicAlias - This class allows targets to define assembler mnemonic
788 /// aliases. This should be used when all forms of one mnemonic are accepted
789 /// with a different mnemonic. For example, X86 allows:
790 /// sal %al, 1 -> shl %al, 1
791 /// sal %ax, %cl -> shl %ax, %cl
792 /// sal %eax, %cl -> shl %eax, %cl
793 /// etc. Though "sal" is accepted with many forms, all of them are directly
794 /// translated to a shl, so it can be handled with (in the case of X86, it
795 /// actually has one for each suffix as well):
796 /// def : MnemonicAlias<"sal", "shl">;
798 /// Mnemonic aliases are mapped before any other translation in the match phase,
799 /// and do allow Requires predicates, e.g.:
801 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
802 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
804 class MnemonicAlias<string From, string To> {
805 string FromMnemonic = From;
806 string ToMnemonic = To;
808 // Predicates - Predicates that must be true for this remapping to happen.
809 list<Predicate> Predicates = [];
812 /// InstAlias - This defines an alternate assembly syntax that is allowed to
813 /// match an instruction that has a different (more canonical) assembly
815 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
816 string AsmString = Asm; // The .s format to match the instruction with.
817 dag ResultInst = Result; // The MCInst to generate.
818 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
820 // Predicates - Predicates that must be true for this to match.
821 list<Predicate> Predicates = [];
824 //===----------------------------------------------------------------------===//
825 // AsmWriter - This class can be implemented by targets that need to customize
826 // the format of the .s file writer.
828 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
829 // on X86 for example).
832 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
833 // class. Generated AsmWriter classes are always prefixed with the target
835 string AsmWriterClassName = "AsmPrinter";
837 // Variant - AsmWriters can be of multiple different variants. Variants are
838 // used to support targets that need to emit assembly code in ways that are
839 // mostly the same for different targets, but have minor differences in
840 // syntax. If the asmstring contains {|} characters in them, this integer
841 // will specify which alternative to use. For example "{x|y|z}" with Variant
842 // == 1, will expand to "y".
846 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
847 // layout, the asmwriter can actually generate output in this columns (in
848 // verbose-asm mode). These two values indicate the width of the first column
849 // (the "opcode" area) and the width to reserve for subsequent operands. When
850 // verbose asm mode is enabled, operands will be indented to respect this.
851 int FirstOperandColumn = -1;
853 // OperandSpacing - Space between operand columns.
854 int OperandSpacing = -1;
856 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
857 // generation of the printInstruction() method. For MC printers, it takes
858 // an MCInstr* operand, otherwise it takes a MachineInstr*.
859 bit isMCAsmWriter = 0;
861 def DefaultAsmWriter : AsmWriter;
864 //===----------------------------------------------------------------------===//
865 // Target - This class contains the "global" target information
868 // InstructionSet - Instruction set description for this target.
869 InstrInfo InstructionSet;
871 // AssemblyParsers - The AsmParser instances available for this target.
872 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
874 /// AssemblyParserVariants - The AsmParserVariant instances available for
876 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
878 // AssemblyWriters - The AsmWriter instances available for this target.
879 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
882 //===----------------------------------------------------------------------===//
883 // SubtargetFeature - A characteristic of the chip set.
885 class SubtargetFeature<string n, string a, string v, string d,
886 list<SubtargetFeature> i = []> {
887 // Name - Feature name. Used by command line (-mattr=) to determine the
888 // appropriate target chip.
892 // Attribute - Attribute to be set by feature.
894 string Attribute = a;
896 // Value - Value the attribute to be set to by feature.
900 // Desc - Feature description. Used by command line (-mattr=) to display help
905 // Implies - Features that this feature implies are present. If one of those
906 // features isn't set, then this one shouldn't be set either.
908 list<SubtargetFeature> Implies = i;
911 //===----------------------------------------------------------------------===//
912 // Processor chip sets - These values represent each of the chip sets supported
913 // by the scheduler. Each Processor definition requires corresponding
914 // instruction itineraries.
916 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
917 // Name - Chip set name. Used by command line (-mcpu=) to determine the
918 // appropriate target chip.
922 // SchedModel - The machine model for scheduling and instruction cost.
924 SchedMachineModel SchedModel = NoSchedModel;
926 // ProcItin - The scheduling information for the target processor.
928 ProcessorItineraries ProcItin = pi;
930 // Features - list of
931 list<SubtargetFeature> Features = f;
934 // ProcessorModel allows subtargets to specify the more general
935 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
936 // gradually move to this newer form.
937 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
938 : Processor<n, NoItineraries, f> {
942 //===----------------------------------------------------------------------===//
943 // Pull in the common support for calling conventions.
945 include "llvm/Target/TargetCallingConv.td"
947 //===----------------------------------------------------------------------===//
948 // Pull in the common support for DAG isel generation.
950 include "llvm/Target/TargetSelectionDAG.td"