1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<int size, int offset = 0> {
26 string Namespace = "";
28 // Size - Size (in bits) of the sub-registers represented by this index.
31 // Offset - Offset of the first bit that is part of this sub-register index.
32 // Set it to -1 if the same index is used to represent sub-registers that can
33 // be at different offsets (for example when using an index to access an
34 // element in a register tuple).
37 // ComposedOf - A list of two SubRegIndex instances, [A, B].
38 // This indicates that this SubRegIndex is the result of composing A and B.
39 // See ComposedSubRegIndex.
40 list<SubRegIndex> ComposedOf = [];
42 // CoveringSubRegIndices - A list of two or more sub-register indexes that
43 // cover this sub-register.
45 // This field should normally be left blank as TableGen can infer it.
47 // TableGen automatically detects sub-registers that straddle the registers
48 // in the SubRegs field of a Register definition. For example:
50 // Q0 = dsub_0 -> D0, dsub_1 -> D1
51 // Q1 = dsub_0 -> D2, dsub_1 -> D3
52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
57 // CoveringSubRegIndices = [dsub_1, dsub_2].
58 list<SubRegIndex> CoveringSubRegIndices = [];
61 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
62 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
63 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
65 !if(!eq(B.Offset, -1), -1,
66 !add(A.Offset, B.Offset)))> {
68 let ComposedOf = [A, B];
71 // RegAltNameIndex - The alternate name set to use for register operands of
72 // this register class when printing.
73 class RegAltNameIndex {
74 string Namespace = "";
76 def NoRegAltName : RegAltNameIndex;
78 // Register - You should define one instance of this class for each register
79 // in the target machine. String n will become the "name" of the register.
80 class Register<string n, list<string> altNames = []> {
81 string Namespace = "";
83 list<string> AltNames = altNames;
85 // Aliases - A list of registers that this register overlaps with. A read or
86 // modification of this register can potentially read or modify the aliased
88 list<Register> Aliases = [];
90 // SubRegs - A list of registers that are parts of this register. Note these
91 // are "immediate" sub-registers and the registers within the list do not
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
97 // to address it. Sub-sub-register indices are automatically inherited from
99 list<SubRegIndex> SubRegIndices = [];
101 // RegAltNameIndices - The alternate name indices which are valid for this
103 list<RegAltNameIndex> RegAltNameIndices = [];
105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
106 // These values can be determined by locating the <target>.h file in the
107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
108 // order of these names correspond to the enumeration used by gcc. A value of
109 // -1 indicates that the gcc number is undefined and -2 that register number
110 // is invalid for this mode/flavour.
111 list<int> DwarfNumbers = [];
113 // CostPerUse - Additional cost of instructions using this register compared
114 // to other registers in its class. The register allocator will try to
115 // minimize the number of instructions using a register with a CostPerUse.
116 // This is used by the x86-64 and ARM Thumb targets where some registers
117 // require larger instruction encodings.
120 // CoveredBySubRegs - When this bit is set, the value of this register is
121 // completely determined by the value of its sub-registers. For example, the
122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
123 // covered by its sub-register AX.
124 bit CoveredBySubRegs = 0;
126 // HWEncoding - The target specific hardware encoding for this register.
127 bits<16> HWEncoding = 0;
130 // RegisterWithSubRegs - This can be used to define instances of Register which
131 // need to specify sub-registers.
132 // List "subregs" specifies which registers are sub-registers to this one. This
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
134 // This allows the code generator to be careful not to put two values with
135 // overlapping live ranges into registers which alias.
136 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
137 let SubRegs = subregs;
140 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
141 // of Operand's that are legal as type qualifiers in DAG patterns. This should
142 // only ever be used for defining multiclasses that are polymorphic over both
143 // RegisterClass's and other Operand's.
145 string OperandNamespace = "MCOI";
146 string DecoderMethod = "";
149 // RegisterClass - Now that all of the registers are defined, and aliases
150 // between registers are defined, specify which registers belong to which
151 // register classes. This also defines the default allocation order of
152 // registers by register allocators.
154 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
155 dag regList, RegAltNameIndex idx = NoRegAltName>
157 string Namespace = namespace;
159 // RegType - Specify the list ValueType of the registers in this register
160 // class. Note that all registers in a register class must have the same
161 // ValueTypes. This is a list because some targets permit storing different
162 // types in same register, for example vector values with 128-bit total size,
163 // but different count/size of items, like SSE on x86.
165 list<ValueType> RegTypes = regTypes;
167 // Size - Specify the spill size in bits of the registers. A default value of
168 // zero lets tablgen pick an appropriate size.
171 // Alignment - Specify the alignment required of the registers when they are
172 // stored or loaded to memory.
174 int Alignment = alignment;
176 // CopyCost - This value is used to specify the cost of copying a value
177 // between two registers in this register class. The default value is one
178 // meaning it takes a single instruction to perform the copying. A negative
179 // value means copying is extremely expensive or impossible.
182 // MemberList - Specify which registers are in this class. If the
183 // allocation_order_* method are not specified, this also defines the order of
184 // allocation used by the register allocator.
186 dag MemberList = regList;
188 // AltNameIndex - The alternate register name to use when printing operands
189 // of this register class. Every register in the register class must have
190 // a valid alternate name for the given index.
191 RegAltNameIndex altNameIndex = idx;
193 // isAllocatable - Specify that the register class can be used for virtual
194 // registers and register allocation. Some register classes are only used to
195 // model instruction operand constraints, and should have isAllocatable = 0.
196 bit isAllocatable = 1;
198 // AltOrders - List of alternative allocation orders. The default order is
199 // MemberList itself, and that is good enough for most targets since the
200 // register allocators automatically remove reserved registers and move
201 // callee-saved registers to the end.
202 list<dag> AltOrders = [];
204 // AltOrderSelect - The body of a function that selects the allocation order
205 // to use in a given machine function. The code will be inserted in a
206 // function like this:
208 // static inline unsigned f(const MachineFunction &MF) { ... }
210 // The function should return 0 to select the default order defined by
211 // MemberList, 1 to select the first AltOrders entry and so on.
212 code AltOrderSelect = [{}];
214 // Specify allocation priority for register allocators using a greedy
215 // heuristic. Classes with higher priority values are assigned first. This is
216 // useful as it is sometimes beneficial to assign registers to highly
217 // constrained classes first. The value has to be in the range [0,63].
218 int AllocationPriority = 0;
221 // The memberList in a RegisterClass is a dag of set operations. TableGen
222 // evaluates these set operations and expand them into register lists. These
223 // are the most common operation, see test/TableGen/SetTheory.td for more
224 // examples of what is possible:
226 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
227 // register class, or a sub-expression. This is also the way to simply list
230 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
232 // (and GPR, CSR) - Set intersection. All registers from the first set that are
233 // also in the second set.
235 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
236 // numbered registers. Takes an optional 4th operand which is a stride to use
237 // when generating the sequence.
239 // (shl GPR, 4) - Remove the first N elements.
241 // (trunc GPR, 4) - Truncate after the first N elements.
243 // (rotl GPR, 1) - Rotate N places to the left.
245 // (rotr GPR, 1) - Rotate N places to the right.
247 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
249 // (interleave A, B, ...) - Interleave the elements from each argument list.
251 // All of these operators work on ordered sets, not lists. That means
252 // duplicates are removed from sub-expressions.
254 // Set operators. The rest is defined in TargetSelectionDAG.td.
259 // RegisterTuples - Automatically generate super-registers by forming tuples of
260 // sub-registers. This is useful for modeling register sequence constraints
261 // with pseudo-registers that are larger than the architectural registers.
263 // The sub-register lists are zipped together:
265 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
267 // Generates the same registers as:
269 // let SubRegIndices = [sube, subo] in {
270 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
271 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
274 // The generated pseudo-registers inherit super-classes and fields from their
275 // first sub-register. Most fields from the Register class are inferred, and
276 // the AsmName and Dwarf numbers are cleared.
278 // RegisterTuples instances can be used in other set operations to form
279 // register classes and so on. This is the only way of using the generated
281 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
282 // SubRegs - N lists of registers to be zipped up. Super-registers are
283 // synthesized from the first element of each SubRegs list, the second
284 // element and so on.
285 list<dag> SubRegs = Regs;
287 // SubRegIndices - N SubRegIndex instances. This provides the names of the
288 // sub-registers in the synthesized super-registers.
289 list<SubRegIndex> SubRegIndices = Indices;
293 //===----------------------------------------------------------------------===//
294 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
295 // to the register numbering used by gcc and gdb. These values are used by a
296 // debug information writer to describe where values may be located during
298 class DwarfRegNum<list<int> Numbers> {
299 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
300 // These values can be determined by locating the <target>.h file in the
301 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
302 // order of these names correspond to the enumeration used by gcc. A value of
303 // -1 indicates that the gcc number is undefined and -2 that register number
304 // is invalid for this mode/flavour.
305 list<int> DwarfNumbers = Numbers;
308 // DwarfRegAlias - This class declares that a given register uses the same dwarf
309 // numbers as another one. This is useful for making it clear that the two
310 // registers do have the same number. It also lets us build a mapping
311 // from dwarf register number to llvm register.
312 class DwarfRegAlias<Register reg> {
313 Register DwarfAlias = reg;
316 //===----------------------------------------------------------------------===//
317 // Pull in the common support for scheduling
319 include "llvm/Target/TargetSchedule.td"
321 class Predicate; // Forward def
323 //===----------------------------------------------------------------------===//
324 // Instruction set description - These classes correspond to the C++ classes in
325 // the Target/TargetInstrInfo.h file.
328 string Namespace = "";
330 dag OutOperandList; // An dag containing the MI def operand list.
331 dag InOperandList; // An dag containing the MI use operand list.
332 string AsmString = ""; // The .s format to print the instruction with.
334 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
335 // otherwise, uninitialized.
338 // The follow state will eventually be inferred automatically from the
339 // instruction pattern.
341 list<Register> Uses = []; // Default to using no non-operand registers
342 list<Register> Defs = []; // Default to modifying no non-operand registers
344 // Predicates - List of predicates which will be turned into isel matching
346 list<Predicate> Predicates = [];
348 // Size - Size of encoded instruction, or zero if the size cannot be determined
352 // DecoderNamespace - The "namespace" in which this instruction exists, on
353 // targets like ARM which multiple ISA namespaces exist.
354 string DecoderNamespace = "";
356 // Code size, for instruction selection.
357 // FIXME: What does this actually mean?
360 // Added complexity passed onto matching pattern.
361 int AddedComplexity = 0;
363 // These bits capture information about the high-level semantics of the
365 bit isReturn = 0; // Is this instruction a return instruction?
366 bit isBranch = 0; // Is this instruction a branch instruction?
367 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
368 bit isCompare = 0; // Is this instruction a comparison instruction?
369 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
370 bit isBitcast = 0; // Is this instruction a bitcast instruction?
371 bit isSelect = 0; // Is this instruction a select instruction?
372 bit isBarrier = 0; // Can control flow fall through this instruction?
373 bit isCall = 0; // Is this instruction a call instruction?
374 bit isAdd = 0; // Is this instruction an add instruction?
375 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
376 bit mayLoad = ?; // Is it possible for this inst to read memory?
377 bit mayStore = ?; // Is it possible for this inst to write memory?
378 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
379 bit isCommutable = 0; // Is this 3 operand instruction commutable?
380 bit isTerminator = 0; // Is this part of the terminator for a basic block?
381 bit isReMaterializable = 0; // Is this instruction re-materializable?
382 bit isPredicable = 0; // Is this instruction predicable?
383 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
384 bit usesCustomInserter = 0; // Pseudo instr needing special help.
385 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
386 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
387 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
388 bit isConvergent = 0; // Is this instruction convergent?
389 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
390 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
391 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
392 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
393 // If so, make sure to override
394 // TargetInstrInfo::getRegSequenceLikeInputs.
395 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
396 // If so, won't have encoding information for
397 // the [MC]CodeEmitter stuff.
398 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
399 // If so, make sure to override
400 // TargetInstrInfo::getExtractSubregLikeInputs.
401 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
402 // If so, make sure to override
403 // TargetInstrInfo::getInsertSubregLikeInputs.
405 // Does the instruction have side effects that are not captured by any
406 // operands of the instruction or other flags?
407 bit hasSideEffects = ?;
409 // Is this instruction a "real" instruction (with a distinct machine
410 // encoding), or is it a pseudo instruction used for codegen modeling
412 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
413 // instructions can (and often do) still have encoding information
414 // associated with them. Once we've migrated all of them over to true
415 // pseudo-instructions that are lowered to real instructions prior to
416 // the printer/emitter, we can remove this attribute and just use isPseudo.
418 // The intended use is:
419 // isPseudo: Does not have encoding information and should be expanded,
420 // at the latest, during lowering to MCInst.
422 // isCodeGenOnly: Does have encoding information and can go through to the
423 // CodeEmitter unchanged, but duplicates a canonical instruction
424 // definition's encoding and should be ignored when constructing the
425 // assembler match tables.
426 bit isCodeGenOnly = 0;
428 // Is this instruction a pseudo instruction for use by the assembler parser.
429 bit isAsmParserOnly = 0;
431 // This instruction is not expected to be queried for scheduling latencies
432 // and therefore needs no scheduling information even for a complete
434 bit hasNoSchedulingInfo = 0;
436 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
438 // Scheduling information from TargetSchedule.td.
439 list<SchedReadWrite> SchedRW;
441 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
443 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
444 /// be encoded into the output machineinstr.
445 string DisableEncoding = "";
447 string PostEncoderMethod = "";
448 string DecoderMethod = "";
450 // Is the instruction decoder method able to completely determine if the
451 // given instruction is valid or not. If the TableGen definition of the
452 // instruction specifies bitpattern A??B where A and B are static bits, the
453 // hasCompleteDecoder flag says whether the decoder method fully handles the
454 // ?? space, i.e. if it is a final arbiter for the instruction validity.
455 // If not then the decoder attempts to continue decoding when the decoder
458 // This allows to handle situations where the encoding is not fully
459 // orthogonal. Example:
460 // * InstA with bitpattern 0b0000????,
461 // * InstB with bitpattern 0b000000?? but the associated decoder method
462 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
464 // The decoder tries to decode a bitpattern that matches both InstA and
465 // InstB bitpatterns first as InstB (because it is the most specific
466 // encoding). In the default case (hasCompleteDecoder = 1), when
467 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
468 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
469 // DecodeInstB() is not able to determine if all possible values of ?? are
470 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
471 // decode the bitpattern as InstA too.
472 bit hasCompleteDecoder = 1;
474 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
475 bits<64> TSFlags = 0;
477 ///@name Assembler Parser Support
480 string AsmMatchConverter = "";
482 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
483 /// two-operand matcher inst-alias for a three operand instruction.
484 /// For example, the arm instruction "add r3, r3, r5" can be written
485 /// as "add r3, r5". The constraint is of the same form as a tied-operand
486 /// constraint. For example, "$Rn = $Rd".
487 string TwoOperandAliasConstraint = "";
489 /// Assembler variant name to use for this instruction. If specified then
490 /// instruction will be presented only in MatchTable for this variant. If
491 /// not specified then assembler variants will be determined based on
493 string AsmVariantName = "";
497 /// UseNamedOperandTable - If set, the operand indices of this instruction
498 /// can be queried via the getNamedOperandIdx() function which is generated
500 bit UseNamedOperandTable = 0;
503 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
504 /// Which instruction it expands to and how the operands map from the
506 class PseudoInstExpansion<dag Result> {
507 dag ResultInst = Result; // The instruction to generate.
511 /// Predicates - These are extra conditionals which are turned into instruction
512 /// selector matching code. Currently each predicate is just a string.
513 class Predicate<string cond> {
514 string CondString = cond;
516 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
517 /// matcher, this is true. Targets should set this by inheriting their
518 /// feature from the AssemblerPredicate class in addition to Predicate.
519 bit AssemblerMatcherPredicate = 0;
521 /// AssemblerCondString - Name of the subtarget feature being tested used
522 /// as alternative condition string used for assembler matcher.
523 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
524 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
525 /// It can also list multiple features separated by ",".
526 /// e.g. "ModeThumb,FeatureThumb2" is translated to
527 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
528 string AssemblerCondString = "";
530 /// PredicateName - User-level name to use for the predicate. Mainly for use
531 /// in diagnostics such as missing feature errors in the asm matcher.
532 string PredicateName = "";
534 /// Setting this to '1' indicates that the predicate must be recomputed on
535 /// every function change. Most predicates can leave this at '0'.
537 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
538 bit RecomputePerFunction = 0;
541 /// NoHonorSignDependentRounding - This predicate is true if support for
542 /// sign-dependent-rounding is not enabled.
543 def NoHonorSignDependentRounding
544 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
546 class Requires<list<Predicate> preds> {
547 list<Predicate> Predicates = preds;
550 /// ops definition - This is just a simple marker used to identify the operand
551 /// list for an instruction. outs and ins are identical both syntactically and
552 /// semantically; they are used to define def operands and use operands to
553 /// improve readibility. This should be used like this:
554 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
559 /// variable_ops definition - Mark this instruction as taking a variable number
564 /// PointerLikeRegClass - Values that are designed to have pointer width are
565 /// derived from this. TableGen treats the register class as having a symbolic
566 /// type that it doesn't know, and resolves the actual regclass to use by using
567 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
568 class PointerLikeRegClass<int Kind> {
569 int RegClassKind = Kind;
573 /// ptr_rc definition - Mark this operand as being a pointer value whose
574 /// register class is resolved dynamically via a callback to TargetInstrInfo.
575 /// FIXME: We should probably change this to a class which contain a list of
576 /// flags. But currently we have but one flag.
577 def ptr_rc : PointerLikeRegClass<0>;
579 /// unknown definition - Mark this operand as being of unknown type, causing
580 /// it to be resolved by inference in the context it is used.
582 def unknown : unknown_class;
584 /// AsmOperandClass - Representation for the kinds of operands which the target
585 /// specific parser can create and the assembly matcher may need to distinguish.
587 /// Operand classes are used to define the order in which instructions are
588 /// matched, to ensure that the instruction which gets matched for any
589 /// particular list of operands is deterministic.
591 /// The target specific parser must be able to classify a parsed operand into a
592 /// unique class which does not partially overlap with any other classes. It can
593 /// match a subset of some other class, in which case the super class field
594 /// should be defined.
595 class AsmOperandClass {
596 /// The name to use for this class, which should be usable as an enum value.
599 /// The super classes of this operand.
600 list<AsmOperandClass> SuperClasses = [];
602 /// The name of the method on the target specific operand to call to test
603 /// whether the operand is an instance of this class. If not set, this will
604 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
605 /// signature should be:
606 /// bool isFoo() const;
607 string PredicateMethod = ?;
609 /// The name of the method on the target specific operand to call to add the
610 /// target specific operand to an MCInst. If not set, this will default to
611 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
612 /// signature should be:
613 /// void addFooOperands(MCInst &Inst, unsigned N) const;
614 string RenderMethod = ?;
616 /// The name of the method on the target specific operand to call to custom
617 /// handle the operand parsing. This is useful when the operands do not relate
618 /// to immediates or registers and are very instruction specific (as flags to
619 /// set in a processor register, coprocessor number, ...).
620 string ParserMethod = ?;
622 // The diagnostic type to present when referencing this operand in a
623 // match failure error message. By default, use a generic "invalid operand"
624 // diagnostic. The target AsmParser maps these codes to text.
625 string DiagnosticType = "";
627 /// Set to 1 if this operand is optional and not always required. Typically,
628 /// the AsmParser will emit an error when it finishes parsing an
629 /// instruction if it hasn't matched all the operands yet. However, this
630 /// error will be suppressed if all of the remaining unmatched operands are
631 /// marked as IsOptional.
633 /// Optional arguments must be at the end of the operand list.
636 /// The name of the method on the target specific asm parser that returns the
637 /// default operand for this optional operand. This method is only used if
638 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
639 /// where Foo is the AsmOperandClass name. The method signature should be:
640 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
641 string DefaultMethod = ?;
644 def ImmAsmOperand : AsmOperandClass {
648 /// Operand Types - These provide the built-in operand types that may be used
649 /// by a target. Targets can optionally provide their own operand types as
650 /// needed, though this should not be needed for RISC targets.
651 class Operand<ValueType ty> : DAGOperand {
653 string PrintMethod = "printOperand";
654 string EncoderMethod = "";
655 bit hasCompleteDecoder = 1;
656 string OperandType = "OPERAND_UNKNOWN";
657 dag MIOperandInfo = (ops);
659 // MCOperandPredicate - Optionally, a code fragment operating on
660 // const MCOperand &MCOp, and returning a bool, to indicate if
661 // the value of MCOp is valid for the specific subclass of Operand
662 code MCOperandPredicate;
664 // ParserMatchClass - The "match class" that operands of this type fit
665 // in. Match classes are used to define the order in which instructions are
666 // match, to ensure that which instructions gets matched is deterministic.
668 // The target specific parser must be able to classify an parsed operand into
669 // a unique class, which does not partially overlap with any other classes. It
670 // can match a subset of some other class, in which case the AsmOperandClass
671 // should declare the other operand as one of its super classes.
672 AsmOperandClass ParserMatchClass = ImmAsmOperand;
675 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
677 // RegClass - The register class of the operand.
678 RegisterClass RegClass = regclass;
679 // PrintMethod - The target method to call to print register operands of
680 // this type. The method normally will just use an alt-name index to look
681 // up the name to print. Default to the generic printOperand().
682 string PrintMethod = pm;
684 // EncoderMethod - The target method name to call to encode this register
686 string EncoderMethod = "";
688 // ParserMatchClass - The "match class" that operands of this type fit
689 // in. Match classes are used to define the order in which instructions are
690 // match, to ensure that which instructions gets matched is deterministic.
692 // The target specific parser must be able to classify an parsed operand into
693 // a unique class, which does not partially overlap with any other classes. It
694 // can match a subset of some other class, in which case the AsmOperandClass
695 // should declare the other operand as one of its super classes.
696 AsmOperandClass ParserMatchClass;
698 string OperandType = "OPERAND_REGISTER";
701 let OperandType = "OPERAND_IMMEDIATE" in {
702 def i1imm : Operand<i1>;
703 def i8imm : Operand<i8>;
704 def i16imm : Operand<i16>;
705 def i32imm : Operand<i32>;
706 def i64imm : Operand<i64>;
708 def f32imm : Operand<f32>;
709 def f64imm : Operand<f64>;
712 // Register operands for generic instructions don't have an MVT, but do have
713 // constraints linking the operands (e.g. all operands of a G_ADD must
714 // have the same LLT).
715 class TypedOperand<string Ty> : Operand<untyped> {
716 let OperandType = Ty;
719 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
720 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
721 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
722 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
723 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
724 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
726 /// zero_reg definition - Special node to stand for the zero register.
730 /// All operands which the MC layer classifies as predicates should inherit from
731 /// this class in some manner. This is already handled for the most commonly
732 /// used PredicateOperand, but may be useful in other circumstances.
735 /// OperandWithDefaultOps - This Operand class can be used as the parent class
736 /// for an Operand that needs to be initialized with a default value if
737 /// no value is supplied in a pattern. This class can be used to simplify the
738 /// pattern definitions for instructions that have target specific flags
739 /// encoded as immediate operands.
740 class OperandWithDefaultOps<ValueType ty, dag defaultops>
742 dag DefaultOps = defaultops;
745 /// PredicateOperand - This can be used to define a predicate operand for an
746 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
747 /// AlwaysVal specifies the value of this predicate when set to "always
749 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
750 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
751 let MIOperandInfo = OpTypes;
754 /// OptionalDefOperand - This is used to define a optional definition operand
755 /// for an instruction. DefaultOps is the register the operand represents if
756 /// none is supplied, e.g. zero_reg.
757 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
758 : OperandWithDefaultOps<ty, defaultops> {
759 let MIOperandInfo = OpTypes;
763 // InstrInfo - This class should only be instantiated once to provide parameters
764 // which are global to the target machine.
767 // Target can specify its instructions in either big or little-endian formats.
768 // For instance, while both Sparc and PowerPC are big-endian platforms, the
769 // Sparc manual specifies its instructions in the format [31..0] (big), while
770 // PowerPC specifies them using the format [0..31] (little).
771 bit isLittleEndianEncoding = 0;
773 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
774 // by default, and TableGen will infer their value from the instruction
775 // pattern when possible.
777 // Normally, TableGen will issue an error it it can't infer the value of a
778 // property that hasn't been set explicitly. When guessInstructionProperties
779 // is set, it will guess a safe value instead.
781 // This option is a temporary migration help. It will go away.
782 bit guessInstructionProperties = 1;
784 // TableGen's instruction encoder generator has support for matching operands
785 // to bit-field variables both by name and by position. While matching by
786 // name is preferred, this is currently not possible for complex operands,
787 // and some targets still reply on the positional encoding rules. When
788 // generating a decoder for such targets, the positional encoding rules must
789 // be used by the decoder generator as well.
791 // This option is temporary; it will go away once the TableGen decoder
792 // generator has better support for complex operands and targets have
793 // migrated away from using positionally encoded operands.
794 bit decodePositionallyEncodedOperands = 0;
796 // When set, this indicates that there will be no overlap between those
797 // operands that are matched by ordering (positional operands) and those
800 // This option is temporary; it will go away once the TableGen decoder
801 // generator has better support for complex operands and targets have
802 // migrated away from using positionally encoded operands.
803 bit noNamedPositionallyEncodedOperands = 0;
806 // Standard Pseudo Instructions.
807 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
808 // Only these instructions are allowed in the TargetOpcode namespace.
809 let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
810 Namespace = "TargetOpcode" in {
811 def PHI : Instruction {
812 let OutOperandList = (outs unknown:$dst);
813 let InOperandList = (ins variable_ops);
814 let AsmString = "PHINODE";
816 def INLINEASM : Instruction {
817 let OutOperandList = (outs);
818 let InOperandList = (ins variable_ops);
820 let hasSideEffects = 0; // Note side effect is encoded in an operand.
822 def CFI_INSTRUCTION : Instruction {
823 let OutOperandList = (outs);
824 let InOperandList = (ins i32imm:$id);
827 let isNotDuplicable = 1;
829 def EH_LABEL : Instruction {
830 let OutOperandList = (outs);
831 let InOperandList = (ins i32imm:$id);
834 let isNotDuplicable = 1;
836 def GC_LABEL : Instruction {
837 let OutOperandList = (outs);
838 let InOperandList = (ins i32imm:$id);
841 let isNotDuplicable = 1;
843 def KILL : Instruction {
844 let OutOperandList = (outs);
845 let InOperandList = (ins variable_ops);
847 let hasSideEffects = 0;
849 def EXTRACT_SUBREG : Instruction {
850 let OutOperandList = (outs unknown:$dst);
851 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
853 let hasSideEffects = 0;
855 def INSERT_SUBREG : Instruction {
856 let OutOperandList = (outs unknown:$dst);
857 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
859 let hasSideEffects = 0;
860 let Constraints = "$supersrc = $dst";
862 def IMPLICIT_DEF : Instruction {
863 let OutOperandList = (outs unknown:$dst);
864 let InOperandList = (ins);
866 let hasSideEffects = 0;
867 let isReMaterializable = 1;
868 let isAsCheapAsAMove = 1;
870 def SUBREG_TO_REG : Instruction {
871 let OutOperandList = (outs unknown:$dst);
872 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
874 let hasSideEffects = 0;
876 def COPY_TO_REGCLASS : Instruction {
877 let OutOperandList = (outs unknown:$dst);
878 let InOperandList = (ins unknown:$src, i32imm:$regclass);
880 let hasSideEffects = 0;
881 let isAsCheapAsAMove = 1;
883 def DBG_VALUE : Instruction {
884 let OutOperandList = (outs);
885 let InOperandList = (ins variable_ops);
886 let AsmString = "DBG_VALUE";
887 let hasSideEffects = 0;
889 def REG_SEQUENCE : Instruction {
890 let OutOperandList = (outs unknown:$dst);
891 let InOperandList = (ins unknown:$supersrc, variable_ops);
893 let hasSideEffects = 0;
894 let isAsCheapAsAMove = 1;
896 def COPY : Instruction {
897 let OutOperandList = (outs unknown:$dst);
898 let InOperandList = (ins unknown:$src);
900 let hasSideEffects = 0;
901 let isAsCheapAsAMove = 1;
902 let hasNoSchedulingInfo = 0;
904 def BUNDLE : Instruction {
905 let OutOperandList = (outs);
906 let InOperandList = (ins variable_ops);
907 let AsmString = "BUNDLE";
909 def LIFETIME_START : Instruction {
910 let OutOperandList = (outs);
911 let InOperandList = (ins i32imm:$id);
912 let AsmString = "LIFETIME_START";
913 let hasSideEffects = 0;
915 def LIFETIME_END : Instruction {
916 let OutOperandList = (outs);
917 let InOperandList = (ins i32imm:$id);
918 let AsmString = "LIFETIME_END";
919 let hasSideEffects = 0;
921 def STACKMAP : Instruction {
922 let OutOperandList = (outs);
923 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
926 let usesCustomInserter = 1;
928 def PATCHPOINT : Instruction {
929 let OutOperandList = (outs unknown:$dst);
930 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
931 i32imm:$nargs, i32imm:$cc, variable_ops);
934 let usesCustomInserter = 1;
936 def STATEPOINT : Instruction {
937 let OutOperandList = (outs);
938 let InOperandList = (ins variable_ops);
939 let usesCustomInserter = 1;
942 let hasSideEffects = 1;
945 def LOAD_STACK_GUARD : Instruction {
946 let OutOperandList = (outs ptr_rc:$dst);
947 let InOperandList = (ins);
949 bit isReMaterializable = 1;
950 let hasSideEffects = 0;
953 def LOCAL_ESCAPE : Instruction {
954 // This instruction is really just a label. It has to be part of the chain so
955 // that it doesn't get dropped from the DAG, but it produces nothing and has
957 let OutOperandList = (outs);
958 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
959 let hasSideEffects = 0;
962 def FAULTING_OP : Instruction {
963 let OutOperandList = (outs unknown:$dst);
964 let InOperandList = (ins variable_ops);
965 let usesCustomInserter = 1;
968 let isTerminator = 1;
971 def PATCHABLE_OP : Instruction {
972 let OutOperandList = (outs unknown:$dst);
973 let InOperandList = (ins variable_ops);
974 let usesCustomInserter = 1;
977 let hasSideEffects = 1;
979 def PATCHABLE_FUNCTION_ENTER : Instruction {
980 let OutOperandList = (outs);
981 let InOperandList = (ins);
982 let AsmString = "# XRay Function Enter.";
983 let usesCustomInserter = 1;
984 let hasSideEffects = 0;
986 def PATCHABLE_RET : Instruction {
987 let OutOperandList = (outs unknown:$dst);
988 let InOperandList = (ins variable_ops);
989 let AsmString = "# XRay Function Patchable RET.";
990 let usesCustomInserter = 1;
991 let hasSideEffects = 1;
994 def PATCHABLE_FUNCTION_EXIT : Instruction {
995 let OutOperandList = (outs);
996 let InOperandList = (ins);
997 let AsmString = "# XRay Function Exit.";
998 let usesCustomInserter = 1;
999 let hasSideEffects = 0; // FIXME: is this correct?
1000 let isReturn = 0; // Original return instruction will follow
1002 def PATCHABLE_TAIL_CALL : Instruction {
1003 let OutOperandList = (outs unknown:$dst);
1004 let InOperandList = (ins variable_ops);
1005 let AsmString = "# XRay Tail Call Exit.";
1006 let usesCustomInserter = 1;
1007 let hasSideEffects = 1;
1010 def PATCHABLE_EVENT_CALL : Instruction {
1011 let OutOperandList = (outs);
1012 let InOperandList = (ins ptr_rc:$event, i8imm:$size);
1013 let AsmString = "# XRay Custom Event Log.";
1014 let usesCustomInserter = 1;
1018 let hasSideEffects = 1;
1020 def FENTRY_CALL : Instruction {
1021 let OutOperandList = (outs unknown:$dst);
1022 let InOperandList = (ins variable_ops);
1023 let AsmString = "# FEntry call";
1024 let usesCustomInserter = 1;
1027 let hasSideEffects = 1;
1030 // Generic opcodes used in GlobalISel.
1031 include "llvm/Target/GenericOpcodes.td"
1035 //===----------------------------------------------------------------------===//
1036 // AsmParser - This class can be implemented by targets that wish to implement
1039 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1040 // syntax on X86 for example).
1043 // AsmParserClassName - This specifies the suffix to use for the asmparser
1044 // class. Generated AsmParser classes are always prefixed with the target
1046 string AsmParserClassName = "AsmParser";
1048 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1049 // function of the AsmParser class to call on every matched instruction.
1050 // This can be used to perform target specific instruction post-processing.
1051 string AsmParserInstCleanup = "";
1053 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1054 // written register name matcher
1055 bit ShouldEmitMatchRegisterName = 1;
1057 // Set to true if the target needs a generated 'alternative register name'
1060 // This generates a function which can be used to lookup registers from
1061 // their aliases. This function will fail when called on targets where
1062 // several registers share the same alias (i.e. not a 1:1 mapping).
1063 bit ShouldEmitMatchRegisterAltName = 0;
1065 // HasMnemonicFirst - Set to false if target instructions don't always
1066 // start with a mnemonic as the first token.
1067 bit HasMnemonicFirst = 1;
1069 def DefaultAsmParser : AsmParser;
1071 //===----------------------------------------------------------------------===//
1072 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1073 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1074 // implemented by targets to describe such variants.
1076 class AsmParserVariant {
1077 // Variant - AsmParsers can be of multiple different variants. Variants are
1078 // used to support targets that need to parser multiple formats for the
1079 // assembly language.
1082 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1085 // CommentDelimiter - If given, the delimiter string used to recognize
1086 // comments which are hard coded in the .td assembler strings for individual
1088 string CommentDelimiter = "";
1090 // RegisterPrefix - If given, the token prefix which indicates a register
1091 // token. This is used by the matcher to automatically recognize hard coded
1092 // register tokens as constrained registers, instead of tokens, for the
1093 // purposes of matching.
1094 string RegisterPrefix = "";
1096 // TokenizingCharacters - Characters that are standalone tokens
1097 string TokenizingCharacters = "[]*!";
1099 // SeparatorCharacters - Characters that are not tokens
1100 string SeparatorCharacters = " \t,";
1102 // BreakCharacters - Characters that start new identifiers
1103 string BreakCharacters = "";
1105 def DefaultAsmParserVariant : AsmParserVariant;
1107 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1108 /// matches instructions and aliases.
1109 class AssemblerPredicate<string cond, string name = ""> {
1110 bit AssemblerMatcherPredicate = 1;
1111 string AssemblerCondString = cond;
1112 string PredicateName = name;
1115 /// TokenAlias - This class allows targets to define assembler token
1116 /// operand aliases. That is, a token literal operand which is equivalent
1117 /// to another, canonical, token literal. For example, ARM allows:
1118 /// vmov.u32 s4, #0 -> vmov.i32, #0
1119 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1120 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1121 /// def : TokenAlias<".u32", ".i32">;
1123 /// This works by marking the match class of 'From' as a subclass of the
1124 /// match class of 'To'.
1125 class TokenAlias<string From, string To> {
1126 string FromToken = From;
1127 string ToToken = To;
1130 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1131 /// aliases. This should be used when all forms of one mnemonic are accepted
1132 /// with a different mnemonic. For example, X86 allows:
1133 /// sal %al, 1 -> shl %al, 1
1134 /// sal %ax, %cl -> shl %ax, %cl
1135 /// sal %eax, %cl -> shl %eax, %cl
1136 /// etc. Though "sal" is accepted with many forms, all of them are directly
1137 /// translated to a shl, so it can be handled with (in the case of X86, it
1138 /// actually has one for each suffix as well):
1139 /// def : MnemonicAlias<"sal", "shl">;
1141 /// Mnemonic aliases are mapped before any other translation in the match phase,
1142 /// and do allow Requires predicates, e.g.:
1144 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1145 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1147 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1149 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1151 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1152 /// applied unconditionally.
1153 class MnemonicAlias<string From, string To, string VariantName = ""> {
1154 string FromMnemonic = From;
1155 string ToMnemonic = To;
1156 string AsmVariantName = VariantName;
1158 // Predicates - Predicates that must be true for this remapping to happen.
1159 list<Predicate> Predicates = [];
1162 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1163 /// match an instruction that has a different (more canonical) assembly
1165 class InstAlias<string Asm, dag Result, int Emit = 1> {
1166 string AsmString = Asm; // The .s format to match the instruction with.
1167 dag ResultInst = Result; // The MCInst to generate.
1169 // This determines which order the InstPrinter detects aliases for
1170 // printing. A larger value makes the alias more likely to be
1171 // emitted. The Instruction's own definition is notionally 0.5, so 0
1172 // disables printing and 1 enables it if there are no conflicting aliases.
1173 int EmitPriority = Emit;
1175 // Predicates - Predicates that must be true for this to match.
1176 list<Predicate> Predicates = [];
1178 // If the instruction specified in Result has defined an AsmMatchConverter
1179 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1180 // function when converting the OperandVector into an MCInst instead of the
1181 // function that is generated by the dag Result.
1182 // Setting this to 0 will cause the alias to ignore the Result instruction's
1183 // defined AsmMatchConverter and instead use the function generated by the
1185 bit UseInstAsmMatchConverter = 1;
1187 // Assembler variant name to use for this alias. If not specified then
1188 // assembler variants will be determined based on AsmString
1189 string AsmVariantName = "";
1192 //===----------------------------------------------------------------------===//
1193 // AsmWriter - This class can be implemented by targets that need to customize
1194 // the format of the .s file writer.
1196 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1197 // on X86 for example).
1200 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1201 // class. Generated AsmWriter classes are always prefixed with the target
1203 string AsmWriterClassName = "InstPrinter";
1205 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1206 // the various print methods.
1207 // FIXME: Remove after all ports are updated.
1208 int PassSubtarget = 0;
1210 // Variant - AsmWriters can be of multiple different variants. Variants are
1211 // used to support targets that need to emit assembly code in ways that are
1212 // mostly the same for different targets, but have minor differences in
1213 // syntax. If the asmstring contains {|} characters in them, this integer
1214 // will specify which alternative to use. For example "{x|y|z}" with Variant
1215 // == 1, will expand to "y".
1218 def DefaultAsmWriter : AsmWriter;
1221 //===----------------------------------------------------------------------===//
1222 // Target - This class contains the "global" target information
1225 // InstructionSet - Instruction set description for this target.
1226 InstrInfo InstructionSet;
1228 // AssemblyParsers - The AsmParser instances available for this target.
1229 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1231 /// AssemblyParserVariants - The AsmParserVariant instances available for
1233 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1235 // AssemblyWriters - The AsmWriter instances available for this target.
1236 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1239 //===----------------------------------------------------------------------===//
1240 // SubtargetFeature - A characteristic of the chip set.
1242 class SubtargetFeature<string n, string a, string v, string d,
1243 list<SubtargetFeature> i = []> {
1244 // Name - Feature name. Used by command line (-mattr=) to determine the
1245 // appropriate target chip.
1249 // Attribute - Attribute to be set by feature.
1251 string Attribute = a;
1253 // Value - Value the attribute to be set to by feature.
1257 // Desc - Feature description. Used by command line (-mattr=) to display help
1262 // Implies - Features that this feature implies are present. If one of those
1263 // features isn't set, then this one shouldn't be set either.
1265 list<SubtargetFeature> Implies = i;
1268 /// Specifies a Subtarget feature that this instruction is deprecated on.
1269 class Deprecated<SubtargetFeature dep> {
1270 SubtargetFeature DeprecatedFeatureMask = dep;
1273 /// A custom predicate used to determine if an instruction is
1274 /// deprecated or not.
1275 class ComplexDeprecationPredicate<string dep> {
1276 string ComplexDeprecationPredicate = dep;
1279 //===----------------------------------------------------------------------===//
1280 // Processor chip sets - These values represent each of the chip sets supported
1281 // by the scheduler. Each Processor definition requires corresponding
1282 // instruction itineraries.
1284 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1285 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1286 // appropriate target chip.
1290 // SchedModel - The machine model for scheduling and instruction cost.
1292 SchedMachineModel SchedModel = NoSchedModel;
1294 // ProcItin - The scheduling information for the target processor.
1296 ProcessorItineraries ProcItin = pi;
1298 // Features - list of
1299 list<SubtargetFeature> Features = f;
1302 // ProcessorModel allows subtargets to specify the more general
1303 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1304 // gradually move to this newer form.
1306 // Although this class always passes NoItineraries to the Processor
1307 // class, the SchedMachineModel may still define valid Itineraries.
1308 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1309 : Processor<n, NoItineraries, f> {
1313 //===----------------------------------------------------------------------===//
1314 // InstrMapping - This class is used to create mapping tables to relate
1315 // instructions with each other based on the values specified in RowFields,
1316 // ColFields, KeyCol and ValueCols.
1318 class InstrMapping {
1319 // FilterClass - Used to limit search space only to the instructions that
1320 // define the relationship modeled by this InstrMapping record.
1323 // RowFields - List of fields/attributes that should be same for all the
1324 // instructions in a row of the relation table. Think of this as a set of
1325 // properties shared by all the instructions related by this relationship
1326 // model and is used to categorize instructions into subgroups. For instance,
1327 // if we want to define a relation that maps 'Add' instruction to its
1328 // predicated forms, we can define RowFields like this:
1330 // let RowFields = BaseOp
1331 // All add instruction predicated/non-predicated will have to set their BaseOp
1332 // to the same value.
1334 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1335 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1336 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1337 list<string> RowFields = [];
1339 // List of fields/attributes that are same for all the instructions
1340 // in a column of the relation table.
1341 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1342 // based on the 'predSense' values. All the instruction in a specific
1343 // column have the same value and it is fixed for the column according
1344 // to the values set in 'ValueCols'.
1345 list<string> ColFields = [];
1347 // Values for the fields/attributes listed in 'ColFields'.
1348 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1349 // that models this relation) should be non-predicated.
1350 // In the example above, 'Add' is the key instruction.
1351 list<string> KeyCol = [];
1353 // List of values for the fields/attributes listed in 'ColFields', one for
1354 // each column in the relation table.
1356 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1357 // table. First column requires all the instructions to have predSense
1358 // set to 'true' and second column requires it to be 'false'.
1359 list<list<string> > ValueCols = [];
1362 //===----------------------------------------------------------------------===//
1363 // Pull in the common support for calling conventions.
1365 include "llvm/Target/TargetCallingConv.td"
1367 //===----------------------------------------------------------------------===//
1368 // Pull in the common support for DAG isel generation.
1370 include "llvm/Target/TargetSelectionDAG.td"
1372 //===----------------------------------------------------------------------===//
1373 // Pull in the common support for Global ISel register bank info generation.
1375 include "llvm/Target/GlobalISel/RegisterBank.td"
1377 //===----------------------------------------------------------------------===//
1378 // Pull in the common support for DAG isel generation.
1380 include "llvm/Target/GlobalISel/Target.td"
1382 //===----------------------------------------------------------------------===//
1383 // Pull in the common support for the Global ISel DAG-based selector generation.
1385 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"