1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
20 class TargetRegisterClass;
21 class TargetRegisterInfo;
23 //===----------------------------------------------------------------------===//
24 // Machine Operand Flags and Description
25 //===----------------------------------------------------------------------===//
28 // Operand constraints: only "tied_to" for now.
29 enum OperandConstraint {
30 TIED_TO = 0 // Must be allocated the same register as.
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the TargetOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
43 /// TargetOperandInfo - This holds information about one operand of a machine
44 /// instruction, indicating the register class for register operands, etc.
46 class TargetOperandInfo {
48 /// RegClass - This specifies the register class enumeration of the operand
49 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
50 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
51 /// get a dynamic register class.
53 /// NOTE: This member should be considered to be private, all access should go
54 /// through "getRegClass(TRI)" below.
55 unsigned short RegClass;
57 /// Flags - These are flags from the TOI::OperandFlags enum.
60 /// Lower 16 bits are used to specify which constraints are set. The higher 16
61 /// bits are used to specify the value of constraints (4 bits each).
63 /// Currently no other information.
65 /// getRegClass - Get the register class for the operand, handling resolution
66 /// of "symbolic" pointer register classes etc. If this is not a register
67 /// operand, this returns null.
68 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
71 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
72 /// requires a callback to look up its register class.
73 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
75 /// isPredicate - Set if this is one of the operands that made up of
76 /// the predicate operand that controls an isPredicable() instruction.
77 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
79 /// isOptionalDef - Set if this operand is a optional def.
81 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
85 //===----------------------------------------------------------------------===//
86 // Machine Instruction Flags and Description
87 //===----------------------------------------------------------------------===//
89 /// TargetInstrDesc flags - These should be considered private to the
90 /// implementation of the TargetInstrDesc class. Clients should use the
91 /// predicate methods on TargetInstrDesc, not use these directly. These
92 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
109 UnmodeledSideEffects,
120 /// TargetInstrDesc - Describe properties that are true of each
121 /// instruction in the target description file. This captures information about
122 /// side effects, register use and many other things. There is one instance of
123 /// this struct for each target instruction class, and the MachineInstr class
124 /// points to this struct directly to describe itself.
125 class TargetInstrDesc {
127 unsigned short Opcode; // The opcode number
128 unsigned short NumOperands; // Num of args (may be more if variable_ops)
129 unsigned short NumDefs; // Num of args that are definitions
130 unsigned short SchedClass; // enum identifying instr sched class
131 const char * Name; // Name of the instruction record in td file
132 unsigned Flags; // Flags identifying machine instr class
133 unsigned TSFlags; // Target Specific Flag values
134 const unsigned *ImplicitUses; // Registers implicitly read by this instr
135 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
136 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
137 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
139 /// getOperandConstraint - Returns the value of the specific constraint if
140 /// it is set. Returns -1 if it is not set.
141 int getOperandConstraint(unsigned OpNum,
142 TOI::OperandConstraint Constraint) const {
143 if (OpNum < NumOperands &&
144 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
145 unsigned Pos = 16 + Constraint * 4;
146 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
151 /// getOpcode - Return the opcode number for this descriptor.
152 unsigned getOpcode() const {
156 /// getName - Return the name of the record in the .td file for this
157 /// instruction, for example "ADD8ri".
158 const char *getName() const {
162 /// getNumOperands - Return the number of declared MachineOperands for this
163 /// MachineInstruction. Note that variadic (isVariadic() returns true)
164 /// instructions may have additional operands at the end of the list, and note
165 /// that the machine instruction may include implicit register def/uses as
167 unsigned getNumOperands() const {
171 /// getNumDefs - Return the number of MachineOperands that are register
172 /// definitions. Register definitions always occur at the start of the
173 /// machine operand list. This is the number of "outs" in the .td file,
174 /// and does not include implicit defs.
175 unsigned getNumDefs() const {
179 /// isVariadic - Return true if this instruction can have a variable number of
180 /// operands. In this case, the variable operands will be after the normal
181 /// operands but before the implicit definitions and uses (if any are
183 bool isVariadic() const {
184 return Flags & (1 << TID::Variadic);
187 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
188 /// ARM instructions which can set condition code if 's' bit is set.
189 bool hasOptionalDef() const {
190 return Flags & (1 << TID::HasOptionalDef);
193 /// getImplicitUses - Return a list of registers that are potentially
194 /// read by any instance of this machine instruction. For example, on X86,
195 /// the "adc" instruction adds two register operands and adds the carry bit in
196 /// from the flags register. In this case, the instruction is marked as
197 /// implicitly reading the flags. Likewise, the variable shift instruction on
198 /// X86 is marked as implicitly reading the 'CL' register, which it always
201 /// This method returns null if the instruction has no implicit uses.
202 const unsigned *getImplicitUses() const {
206 /// getImplicitDefs - Return a list of registers that are potentially
207 /// written by any instance of this machine instruction. For example, on X86,
208 /// many instructions implicitly set the flags register. In this case, they
209 /// are marked as setting the FLAGS. Likewise, many instructions always
210 /// deposit their result in a physical register. For example, the X86 divide
211 /// instruction always deposits the quotient and remainder in the EAX/EDX
212 /// registers. For that instruction, this will return a list containing the
213 /// EAX/EDX/EFLAGS registers.
215 /// This method returns null if the instruction has no implicit defs.
216 const unsigned *getImplicitDefs() const {
220 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
221 /// uses the specified physical register.
222 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
223 if (const unsigned *ImpUses = ImplicitUses)
224 for (; *ImpUses; ++ImpUses)
225 if (*ImpUses == Reg) return true;
229 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
230 /// defines the specified physical register.
231 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
232 if (const unsigned *ImpDefs = ImplicitDefs)
233 for (; *ImpDefs; ++ImpDefs)
234 if (*ImpDefs == Reg) return true;
238 /// getRegClassBarriers - Return a list of register classes that are
239 /// completely clobbered by this machine instruction. For example, on X86
240 /// the call instructions will completely clobber all the registers in the
241 /// fp stack and XMM classes.
243 /// This method returns null if the instruction doesn't completely clobber
244 /// any register class.
245 const TargetRegisterClass **getRegClassBarriers() const {
249 /// getSchedClass - Return the scheduling class for this instruction. The
250 /// scheduling class is an index into the InstrItineraryData table. This
251 /// returns zero if there is no known scheduling information for the
254 unsigned getSchedClass() const {
258 bool isReturn() const {
259 return Flags & (1 << TID::Return);
262 bool isCall() const {
263 return Flags & (1 << TID::Call);
266 /// isBarrier - Returns true if the specified instruction stops control flow
267 /// from executing the instruction immediately following it. Examples include
268 /// unconditional branches and return instructions.
269 bool isBarrier() const {
270 return Flags & (1 << TID::Barrier);
273 /// isTerminator - Returns true if this instruction part of the terminator for
274 /// a basic block. Typically this is things like return and branch
277 /// Various passes use this to insert code into the bottom of a basic block,
278 /// but before control flow occurs.
279 bool isTerminator() const {
280 return Flags & (1 << TID::Terminator);
283 /// isBranch - Returns true if this is a conditional, unconditional, or
284 /// indirect branch. Predicates below can be used to discriminate between
285 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
286 /// get more information.
287 bool isBranch() const {
288 return Flags & (1 << TID::Branch);
291 /// isIndirectBranch - Return true if this is an indirect branch, such as a
292 /// branch through a register.
293 bool isIndirectBranch() const {
294 return Flags & (1 << TID::IndirectBranch);
297 /// isConditionalBranch - Return true if this is a branch which may fall
298 /// through to the next instruction or may transfer control flow to some other
299 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
300 /// information about this branch.
301 bool isConditionalBranch() const {
302 return isBranch() & !isBarrier() & !isIndirectBranch();
305 /// isUnconditionalBranch - Return true if this is a branch which always
306 /// transfers control flow to some other block. The
307 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
308 /// about this branch.
309 bool isUnconditionalBranch() const {
310 return isBranch() & isBarrier() & !isIndirectBranch();
313 // isPredicable - Return true if this instruction has a predicate operand that
314 // controls execution. It may be set to 'always', or may be set to other
315 /// values. There are various methods in TargetInstrInfo that can be used to
316 /// control and modify the predicate in this instruction.
317 bool isPredicable() const {
318 return Flags & (1 << TID::Predicable);
321 /// isNotDuplicable - Return true if this instruction cannot be safely
322 /// duplicated. For example, if the instruction has a unique labels attached
323 /// to it, duplicating it would cause multiple definition errors.
324 bool isNotDuplicable() const {
325 return Flags & (1 << TID::NotDuplicable);
328 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
329 /// which must be filled by the code generator.
330 bool hasDelaySlot() const {
331 return Flags & (1 << TID::DelaySlot);
334 /// canFoldAsLoad - Return true for instructions that can be folded as
335 /// memory operands in other instructions. The most common use for this
336 /// is instructions that are simple loads from memory that don't modify
337 /// the loaded value in any way, but it can also be used for instructions
338 /// that can be expressed as constant-pool loads, such as V_SETALLONES
339 /// on x86, to allow them to be folded when it is beneficial.
340 /// This should only be set on instructions that return a value in their
341 /// only virtual register definition.
342 bool canFoldAsLoad() const {
343 return Flags & (1 << TID::FoldableAsLoad);
346 //===--------------------------------------------------------------------===//
347 // Side Effect Analysis
348 //===--------------------------------------------------------------------===//
350 /// mayLoad - Return true if this instruction could possibly read memory.
351 /// Instructions with this flag set are not necessarily simple load
352 /// instructions, they may load a value and modify it, for example.
353 bool mayLoad() const {
354 return Flags & (1 << TID::MayLoad);
358 /// mayStore - Return true if this instruction could possibly modify memory.
359 /// Instructions with this flag set are not necessarily simple store
360 /// instructions, they may store a modified value based on their operands, or
361 /// may not actually modify anything, for example.
362 bool mayStore() const {
363 return Flags & (1 << TID::MayStore);
366 /// hasUnmodeledSideEffects - Return true if this instruction has side
367 /// effects that are not modeled by other flags. This does not return true
368 /// for instructions whose effects are captured by:
370 /// 1. Their operand list and implicit definition/use list. Register use/def
371 /// info is explicit for instructions.
372 /// 2. Memory accesses. Use mayLoad/mayStore.
373 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
375 /// Examples of side effects would be modifying 'invisible' machine state like
376 /// a control register, flushing a cache, modifying a register invisible to
379 bool hasUnmodeledSideEffects() const {
380 return Flags & (1 << TID::UnmodeledSideEffects);
383 //===--------------------------------------------------------------------===//
384 // Flags that indicate whether an instruction can be modified by a method.
385 //===--------------------------------------------------------------------===//
387 /// isCommutable - Return true if this may be a 2- or 3-address
388 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
389 /// result if Y and Z are exchanged. If this flag is set, then the
390 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
393 /// Note that this flag may be set on instructions that are only commutable
394 /// sometimes. In these cases, the call to commuteInstruction will fail.
395 /// Also note that some instructions require non-trivial modification to
397 bool isCommutable() const {
398 return Flags & (1 << TID::Commutable);
401 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
402 /// which can be changed into a 3-address instruction if needed. Doing this
403 /// transformation can be profitable in the register allocator, because it
404 /// means that the instruction can use a 2-address form if possible, but
405 /// degrade into a less efficient form if the source and dest register cannot
406 /// be assigned to the same register. For example, this allows the x86
407 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
408 /// is the same speed as the shift but has bigger code size.
410 /// If this returns true, then the target must implement the
411 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
412 /// is allowed to fail if the transformation isn't valid for this specific
413 /// instruction (e.g. shl reg, 4 on x86).
415 bool isConvertibleTo3Addr() const {
416 return Flags & (1 << TID::ConvertibleTo3Addr);
419 /// usesCustomInsertionHook - Return true if this instruction requires
420 /// custom insertion support when the DAG scheduler is inserting it into a
421 /// machine basic block. If this is true for the instruction, it basically
422 /// means that it is a pseudo instruction used at SelectionDAG time that is
423 /// expanded out into magic code by the target when MachineInstrs are formed.
425 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
426 /// is used to insert this into the MachineBasicBlock.
427 bool usesCustomInsertionHook() const {
428 return Flags & (1 << TID::UsesCustomInserter);
431 /// isRematerializable - Returns true if this instruction is a candidate for
432 /// remat. This flag is deprecated, please don't use it anymore. If this
433 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
434 /// verify the instruction is really rematable.
435 bool isRematerializable() const {
436 return Flags & (1 << TID::Rematerializable);
439 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
440 /// less) than a move instruction. This is useful during certain types of
441 /// optimizations (e.g., remat during two-address conversion or machine licm)
442 /// where we would like to remat or hoist the instruction, but not if it costs
443 /// more than moving the instruction into the appropriate register. Note, we
444 /// are not marking copies from and to the same register class with this flag.
445 bool isAsCheapAsAMove() const {
446 return Flags & (1 << TID::CheapAsAMove);
449 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
450 /// have special register allocation requirements that are not captured by the
451 /// operand register classes. e.g. ARM::STRD's two source registers must be an
452 /// even / odd pair, ARM::STM registers have to be in ascending order.
453 /// Post-register allocation passes should not attempt to change allocations
454 /// for sources of instructions with this flag.
455 bool hasExtraSrcRegAllocReq() const {
456 return Flags & (1 << TID::ExtraSrcRegAllocReq);
459 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
460 /// have special register allocation requirements that are not captured by the
461 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
462 /// even / odd pair, ARM::LDM registers have to be in ascending order.
463 /// Post-register allocation passes should not attempt to change allocations
464 /// for definitions of instructions with this flag.
465 bool hasExtraDefRegAllocReq() const {
466 return Flags & (1 << TID::ExtraDefRegAllocReq);
470 } // end namespace llvm