1 //===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares Mips TargetInfo objects.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Support/Compiler.h"
25 class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
26 void setDataLayout() {
30 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
31 else if (ABI == "n32")
32 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
33 else if (ABI == "n64")
34 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
36 llvm_unreachable("Invalid ABI");
39 resetDataLayout(("E-" + Layout).str());
41 resetDataLayout(("e-" + Layout).str());
44 static const Builtin::Info BuiltinInfo[];
52 bool CanUseBSDABICalls;
53 enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
54 enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
57 bool UseIndirectJumpHazard;
60 enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
64 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
65 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
66 IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
67 IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
68 DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
69 UseIndirectJumpHazard(false), FPMode(FPXX) {
70 TheCXXABI.set(TargetCXXABI::GenericMIPS);
72 if (Triple.isMIPS32())
74 else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
79 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
81 CanUseBSDABICalls = Triple.isOSFreeBSD() ||
85 bool isIEEE754_2008Default() const {
86 return CPU == "mips32r6" || CPU == "mips64r6";
89 bool isFP64Default() const {
90 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
93 bool isNan2008() const override { return IsNan2008; }
95 bool processorSupportsGPR64() const;
97 StringRef getABI() const override { return ABI; }
99 bool setABI(const std::string &Name) override {
119 void setO32ABITypes() {
120 Int64Type = SignedLongLong;
121 IntMaxType = Int64Type;
122 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
123 LongDoubleWidth = LongDoubleAlign = 64;
124 LongWidth = LongAlign = 32;
125 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
126 PointerWidth = PointerAlign = 32;
127 PtrDiffType = SignedInt;
128 SizeType = UnsignedInt;
132 void setN32N64ABITypes() {
133 LongDoubleWidth = LongDoubleAlign = 128;
134 LongDoubleFormat = &llvm::APFloat::IEEEquad();
135 if (getTriple().isOSFreeBSD()) {
136 LongDoubleWidth = LongDoubleAlign = 64;
137 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
139 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
143 void setN64ABITypes() {
145 if (getTriple().isOSOpenBSD()) {
146 Int64Type = SignedLongLong;
148 Int64Type = SignedLong;
150 IntMaxType = Int64Type;
151 LongWidth = LongAlign = 64;
152 PointerWidth = PointerAlign = 64;
153 PtrDiffType = SignedLong;
154 SizeType = UnsignedLong;
157 void setN32ABITypes() {
159 Int64Type = SignedLongLong;
160 IntMaxType = Int64Type;
161 LongWidth = LongAlign = 32;
162 PointerWidth = PointerAlign = 32;
163 PtrDiffType = SignedInt;
164 SizeType = UnsignedInt;
167 bool isValidCPUName(StringRef Name) const override;
168 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
170 bool setCPU(const std::string &Name) override {
172 return isValidCPUName(Name);
175 const std::string &getCPU() const { return CPU; }
177 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
179 const std::vector<std::string> &FeaturesVec) const override {
183 Features["mips64r2"] = Features["cnmips"] = true;
185 Features[CPU] = true;
186 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
189 unsigned getISARev() const;
191 void getTargetDefines(const LangOptions &Opts,
192 MacroBuilder &Builder) const override;
194 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
196 bool hasFeature(StringRef Feature) const override;
198 BuiltinVaListKind getBuiltinVaListKind() const override {
199 return TargetInfo::VoidPtrBuiltinVaList;
202 ArrayRef<const char *> getGCCRegNames() const override {
203 static const char *const GCCRegNames[] = {
204 // CPU register names
205 // Must match second column of GCCRegAliases
206 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
207 "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
208 "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
210 // Floating point register names
211 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
212 "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
213 "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
214 "$f28", "$f29", "$f30", "$f31",
215 // Hi/lo and condition register names
216 "hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
217 "$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
219 // MSA register names
220 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
221 "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
222 "$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
223 "$w28", "$w29", "$w30", "$w31",
224 // MSA control register names
225 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
226 "$msarequest", "$msamap", "$msaunmap"
228 return llvm::makeArrayRef(GCCRegNames);
231 bool validateAsmConstraint(const char *&Name,
232 TargetInfo::ConstraintInfo &Info) const override {
236 case 'r': // CPU registers.
237 case 'd': // Equivalent to "r" unless generating MIPS16 code.
238 case 'y': // Equivalent to "r", backward compatibility only.
239 case 'f': // floating-point registers.
240 case 'c': // $25 for indirect jumps
241 case 'l': // lo register
242 case 'x': // hilo register pair
243 Info.setAllowsRegister();
245 case 'I': // Signed 16-bit constant
246 case 'J': // Integer 0
247 case 'K': // Unsigned 16-bit constant
248 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
249 case 'M': // Constants not loadable via lui, addiu, or ori
250 case 'N': // Constant -1 to -65535
251 case 'O': // A signed 15-bit constant
252 case 'P': // A constant between 1 go 65535
254 case 'R': // An address that can be used in a non-macro load or store
255 Info.setAllowsMemory();
258 if (Name[1] == 'C') { // An address usable by ll, and sc.
259 Info.setAllowsMemory();
260 Name++; // Skip over 'Z'.
267 std::string convertConstraint(const char *&Constraint) const override {
269 switch (*Constraint) {
270 case 'Z': // Two-character constraint; add "^" hint for later parsing.
271 if (Constraint[1] == 'C') {
272 R = std::string("^") + std::string(Constraint, 2);
278 return TargetInfo::convertConstraint(Constraint);
281 const char *getClobbers() const override {
282 // In GCC, $1 is not widely used in generated code (it's used only in a few
283 // specific situations), so there is no real need for users to add it to
284 // the clobbers list if they want to use it in their inline assembly code.
286 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
287 // code generation, so using it in inline assembly without adding it to the
288 // clobbers list can cause conflicts between the inline assembly code and
289 // the surrounding generated code.
291 // Another problem is that LLVM is allowed to choose $1 for inline assembly
292 // operands, which will conflict with the ".set at" assembler option (which
293 // we use only for inline assembly, in order to maintain compatibility with
294 // GCC) and will also conflict with the user's usage of $1.
296 // The easiest way to avoid these conflicts and keep $1 as an allocatable
297 // register for generated code is to automatically clobber $1 for all inline
300 // FIXME: We should automatically clobber $1 only for inline assembly code
301 // which actually uses it. This would allow LLVM to use $1 for inline
302 // assembly operands if the user's assembly code doesn't use it.
306 bool handleTargetFeatures(std::vector<std::string> &Features,
307 DiagnosticsEngine &Diags) override {
310 IsNan2008 = isIEEE754_2008Default();
311 IsAbs2008 = isIEEE754_2008Default();
312 IsSingleFloat = false;
313 FloatABI = HardFloat;
315 FPMode = isFP64Default() ? FP64 : FPXX;
317 for (const auto &Feature : Features) {
318 if (Feature == "+single-float")
319 IsSingleFloat = true;
320 else if (Feature == "+soft-float")
321 FloatABI = SoftFloat;
322 else if (Feature == "+mips16")
324 else if (Feature == "+micromips")
326 else if (Feature == "+dsp")
327 DspRev = std::max(DspRev, DSP1);
328 else if (Feature == "+dspr2")
329 DspRev = std::max(DspRev, DSP2);
330 else if (Feature == "+msa")
332 else if (Feature == "+nomadd4")
334 else if (Feature == "+fp64")
336 else if (Feature == "-fp64")
338 else if (Feature == "+fpxx")
340 else if (Feature == "+nan2008")
342 else if (Feature == "-nan2008")
344 else if (Feature == "+abs2008")
346 else if (Feature == "-abs2008")
348 else if (Feature == "+noabicalls")
350 else if (Feature == "+use-indirect-jump-hazard")
351 UseIndirectJumpHazard = true;
359 int getEHDataRegisterNumber(unsigned RegNo) const override {
367 bool isCLZForZeroUndef() const override { return false; }
369 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
370 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
371 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
372 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
373 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
374 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
375 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
376 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
377 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
378 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
379 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
380 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
383 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
384 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
385 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
386 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
387 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
388 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
389 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
390 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
391 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
392 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
393 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
397 return llvm::makeArrayRef(O32RegAliases);
398 return llvm::makeArrayRef(NewABIRegAliases);
401 bool hasInt128Type() const override {
402 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
405 bool validateTarget(DiagnosticsEngine &Diags) const override;
407 } // namespace targets
410 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H