1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements X86 TargetInfo objects.
12 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
17 #include "clang/Basic/TargetBuiltins.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
24 const Builtin::Info BuiltinInfoX86[] = {
25 #define BUILTIN(ID, TYPE, ATTRS) \
26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
31 #include "clang/Basic/BuiltinsX86.def"
33 #define BUILTIN(ID, TYPE, ATTRS) \
34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
39 #include "clang/Basic/BuiltinsX86_64.def"
42 static const char *const GCCRegNames[] = {
43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
60 "k2", "k3", "k4", "k5", "k6", "k7",
61 "cr0", "cr2", "cr3", "cr4", "cr8",
62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
63 "bnd0", "bnd1", "bnd2", "bnd3",
66 const TargetInfo::AddlRegName AddlRegNames[] = {
67 {{"al", "ah", "eax", "rax"}, 0},
68 {{"bl", "bh", "ebx", "rbx"}, 3},
69 {{"cl", "ch", "ecx", "rcx"}, 2},
70 {{"dl", "dh", "edx", "rdx"}, 1},
75 {{"r8d", "r8w", "r8b"}, 38},
76 {{"r9d", "r9w", "r9b"}, 39},
77 {{"r10d", "r10w", "r10b"}, 40},
78 {{"r11d", "r11w", "r11b"}, 41},
79 {{"r12d", "r12w", "r12b"}, 42},
80 {{"r13d", "r13w", "r13b"}, 43},
81 {{"r14d", "r14w", "r14b"}, 44},
82 {{"r15d", "r15w", "r15b"}, 45},
85 } // namespace targets
88 using namespace clang;
89 using namespace clang::targets;
91 bool X86TargetInfo::setFPMath(StringRef Name) {
103 bool X86TargetInfo::initFeatureMap(
104 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
105 const std::vector<std::string> &FeaturesVec) const {
106 // FIXME: This *really* should not be here.
107 // X86_64 always has SSE2.
108 if (getTriple().getArch() == llvm::Triple::x86_64)
109 setFeatureEnabledImpl(Features, "sse2", true);
111 const CPUKind Kind = getCPUKind(CPU);
113 // Enable X87 for all X86 processors but Lakemont.
114 if (Kind != CK_Lakemont)
115 setFeatureEnabledImpl(Features, "x87", true);
131 setFeatureEnabledImpl(Features, "mmx", true);
135 setFeatureEnabledImpl(Features, "vaes", true);
136 setFeatureEnabledImpl(Features, "gfni", true);
137 setFeatureEnabledImpl(Features, "vpclmulqdq", true);
138 setFeatureEnabledImpl(Features, "avx512bitalg", true);
139 setFeatureEnabledImpl(Features, "avx512vnni", true);
140 setFeatureEnabledImpl(Features, "avx512vbmi2", true);
141 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
142 setFeatureEnabledImpl(Features, "clwb", true);
145 setFeatureEnabledImpl(Features, "avx512ifma", true);
146 setFeatureEnabledImpl(Features, "avx512vbmi", true);
147 setFeatureEnabledImpl(Features, "sha", true);
149 case CK_SkylakeServer:
150 setFeatureEnabledImpl(Features, "avx512f", true);
151 setFeatureEnabledImpl(Features, "avx512cd", true);
152 setFeatureEnabledImpl(Features, "avx512dq", true);
153 setFeatureEnabledImpl(Features, "avx512bw", true);
154 setFeatureEnabledImpl(Features, "avx512vl", true);
155 if (Kind == CK_SkylakeServer) {
156 setFeatureEnabledImpl(Features, "pku", true);
157 setFeatureEnabledImpl(Features, "clwb", true);
160 case CK_SkylakeClient:
161 setFeatureEnabledImpl(Features, "xsavec", true);
162 setFeatureEnabledImpl(Features, "xsaves", true);
163 setFeatureEnabledImpl(Features, "mpx", true);
164 setFeatureEnabledImpl(Features, "sgx", true);
165 setFeatureEnabledImpl(Features, "clflushopt", true);
166 setFeatureEnabledImpl(Features, "rtm", true);
169 setFeatureEnabledImpl(Features, "rdseed", true);
170 setFeatureEnabledImpl(Features, "adx", true);
171 setFeatureEnabledImpl(Features, "prfchw", true);
174 setFeatureEnabledImpl(Features, "avx2", true);
175 setFeatureEnabledImpl(Features, "lzcnt", true);
176 setFeatureEnabledImpl(Features, "bmi", true);
177 setFeatureEnabledImpl(Features, "bmi2", true);
178 setFeatureEnabledImpl(Features, "fma", true);
179 setFeatureEnabledImpl(Features, "movbe", true);
182 setFeatureEnabledImpl(Features, "rdrnd", true);
183 setFeatureEnabledImpl(Features, "f16c", true);
184 setFeatureEnabledImpl(Features, "fsgsbase", true);
187 setFeatureEnabledImpl(Features, "avx", true);
188 setFeatureEnabledImpl(Features, "xsave", true);
189 setFeatureEnabledImpl(Features, "xsaveopt", true);
192 setFeatureEnabledImpl(Features, "aes", true);
193 setFeatureEnabledImpl(Features, "pclmul", true);
196 setFeatureEnabledImpl(Features, "sse4.2", true);
199 setFeatureEnabledImpl(Features, "sse4.1", true);
202 setFeatureEnabledImpl(Features, "ssse3", true);
207 setFeatureEnabledImpl(Features, "sse3", true);
208 setFeatureEnabledImpl(Features, "cx16", true);
213 setFeatureEnabledImpl(Features, "sse2", true);
217 setFeatureEnabledImpl(Features, "sse", true);
218 setFeatureEnabledImpl(Features, "fxsr", true);
222 setFeatureEnabledImpl(Features, "sha", true);
223 setFeatureEnabledImpl(Features, "rdrnd", true);
224 setFeatureEnabledImpl(Features, "rdseed", true);
225 setFeatureEnabledImpl(Features, "xsave", true);
226 setFeatureEnabledImpl(Features, "xsaveopt", true);
227 setFeatureEnabledImpl(Features, "xsavec", true);
228 setFeatureEnabledImpl(Features, "xsaves", true);
229 setFeatureEnabledImpl(Features, "clflushopt", true);
230 setFeatureEnabledImpl(Features, "mpx", true);
231 setFeatureEnabledImpl(Features, "fsgsbase", true);
234 setFeatureEnabledImpl(Features, "aes", true);
235 setFeatureEnabledImpl(Features, "pclmul", true);
236 setFeatureEnabledImpl(Features, "sse4.2", true);
237 setFeatureEnabledImpl(Features, "prfchw", true);
240 setFeatureEnabledImpl(Features, "movbe", true);
241 setFeatureEnabledImpl(Features, "ssse3", true);
242 setFeatureEnabledImpl(Features, "fxsr", true);
243 setFeatureEnabledImpl(Features, "cx16", true);
247 // TODO: Add avx5124fmaps/avx5124vnniw.
248 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
251 setFeatureEnabledImpl(Features, "avx512f", true);
252 setFeatureEnabledImpl(Features, "avx512cd", true);
253 setFeatureEnabledImpl(Features, "avx512er", true);
254 setFeatureEnabledImpl(Features, "avx512pf", true);
255 setFeatureEnabledImpl(Features, "prfchw", true);
256 setFeatureEnabledImpl(Features, "prefetchwt1", true);
257 setFeatureEnabledImpl(Features, "fxsr", true);
258 setFeatureEnabledImpl(Features, "rdseed", true);
259 setFeatureEnabledImpl(Features, "adx", true);
260 setFeatureEnabledImpl(Features, "lzcnt", true);
261 setFeatureEnabledImpl(Features, "bmi", true);
262 setFeatureEnabledImpl(Features, "bmi2", true);
263 setFeatureEnabledImpl(Features, "rtm", true);
264 setFeatureEnabledImpl(Features, "fma", true);
265 setFeatureEnabledImpl(Features, "rdrnd", true);
266 setFeatureEnabledImpl(Features, "f16c", true);
267 setFeatureEnabledImpl(Features, "fsgsbase", true);
268 setFeatureEnabledImpl(Features, "aes", true);
269 setFeatureEnabledImpl(Features, "pclmul", true);
270 setFeatureEnabledImpl(Features, "cx16", true);
271 setFeatureEnabledImpl(Features, "xsaveopt", true);
272 setFeatureEnabledImpl(Features, "xsave", true);
273 setFeatureEnabledImpl(Features, "movbe", true);
280 setFeatureEnabledImpl(Features, "3dnow", true);
284 setFeatureEnabledImpl(Features, "sse4a", true);
285 setFeatureEnabledImpl(Features, "lzcnt", true);
286 setFeatureEnabledImpl(Features, "popcnt", true);
289 setFeatureEnabledImpl(Features, "sse3", true);
292 setFeatureEnabledImpl(Features, "sse2", true);
295 setFeatureEnabledImpl(Features, "sse", true);
296 setFeatureEnabledImpl(Features, "fxsr", true);
300 setFeatureEnabledImpl(Features, "3dnowa", true);
304 setFeatureEnabledImpl(Features, "avx", true);
305 setFeatureEnabledImpl(Features, "aes", true);
306 setFeatureEnabledImpl(Features, "pclmul", true);
307 setFeatureEnabledImpl(Features, "bmi", true);
308 setFeatureEnabledImpl(Features, "f16c", true);
309 setFeatureEnabledImpl(Features, "xsaveopt", true);
310 setFeatureEnabledImpl(Features, "movbe", true);
313 setFeatureEnabledImpl(Features, "ssse3", true);
314 setFeatureEnabledImpl(Features, "sse4a", true);
315 setFeatureEnabledImpl(Features, "lzcnt", true);
316 setFeatureEnabledImpl(Features, "popcnt", true);
317 setFeatureEnabledImpl(Features, "prfchw", true);
318 setFeatureEnabledImpl(Features, "cx16", true);
319 setFeatureEnabledImpl(Features, "fxsr", true);
323 setFeatureEnabledImpl(Features, "adx", true);
324 setFeatureEnabledImpl(Features, "aes", true);
325 setFeatureEnabledImpl(Features, "avx2", true);
326 setFeatureEnabledImpl(Features, "bmi", true);
327 setFeatureEnabledImpl(Features, "bmi2", true);
328 setFeatureEnabledImpl(Features, "clflushopt", true);
329 setFeatureEnabledImpl(Features, "clzero", true);
330 setFeatureEnabledImpl(Features, "cx16", true);
331 setFeatureEnabledImpl(Features, "f16c", true);
332 setFeatureEnabledImpl(Features, "fma", true);
333 setFeatureEnabledImpl(Features, "fsgsbase", true);
334 setFeatureEnabledImpl(Features, "fxsr", true);
335 setFeatureEnabledImpl(Features, "lzcnt", true);
336 setFeatureEnabledImpl(Features, "mwaitx", true);
337 setFeatureEnabledImpl(Features, "movbe", true);
338 setFeatureEnabledImpl(Features, "pclmul", true);
339 setFeatureEnabledImpl(Features, "popcnt", true);
340 setFeatureEnabledImpl(Features, "prfchw", true);
341 setFeatureEnabledImpl(Features, "rdrnd", true);
342 setFeatureEnabledImpl(Features, "rdseed", true);
343 setFeatureEnabledImpl(Features, "sha", true);
344 setFeatureEnabledImpl(Features, "sse4a", true);
345 setFeatureEnabledImpl(Features, "xsave", true);
346 setFeatureEnabledImpl(Features, "xsavec", true);
347 setFeatureEnabledImpl(Features, "xsaveopt", true);
348 setFeatureEnabledImpl(Features, "xsaves", true);
352 setFeatureEnabledImpl(Features, "avx2", true);
353 setFeatureEnabledImpl(Features, "bmi2", true);
354 setFeatureEnabledImpl(Features, "mwaitx", true);
357 setFeatureEnabledImpl(Features, "fsgsbase", true);
358 setFeatureEnabledImpl(Features, "xsaveopt", true);
361 setFeatureEnabledImpl(Features, "bmi", true);
362 setFeatureEnabledImpl(Features, "fma", true);
363 setFeatureEnabledImpl(Features, "f16c", true);
364 setFeatureEnabledImpl(Features, "tbm", true);
367 // xop implies avx, sse4a and fma4.
368 setFeatureEnabledImpl(Features, "xop", true);
369 setFeatureEnabledImpl(Features, "lwp", true);
370 setFeatureEnabledImpl(Features, "lzcnt", true);
371 setFeatureEnabledImpl(Features, "aes", true);
372 setFeatureEnabledImpl(Features, "pclmul", true);
373 setFeatureEnabledImpl(Features, "prfchw", true);
374 setFeatureEnabledImpl(Features, "cx16", true);
375 setFeatureEnabledImpl(Features, "fxsr", true);
376 setFeatureEnabledImpl(Features, "xsave", true);
379 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
382 // Can't do this earlier because we need to be able to explicitly enable
383 // or disable these features and the things that they depend upon.
385 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
386 auto I = Features.find("sse4.2");
387 if (I != Features.end() && I->getValue() &&
388 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
390 Features["popcnt"] = true;
392 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
393 I = Features.find("3dnow");
394 if (I != Features.end() && I->getValue() &&
395 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
397 Features["prfchw"] = true;
399 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
401 I = Features.find("sse");
402 if (I != Features.end() && I->getValue() &&
403 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
405 Features["mmx"] = true;
410 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
411 X86SSEEnum Level, bool Enabled) {
415 Features["avx512f"] = true;
418 Features["avx2"] = true;
421 Features["avx"] = true;
422 Features["xsave"] = true;
425 Features["sse4.2"] = true;
428 Features["sse4.1"] = true;
431 Features["ssse3"] = true;
434 Features["sse3"] = true;
437 Features["sse2"] = true;
440 Features["sse"] = true;
451 Features["sse"] = false;
454 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
455 Features["gfni"] = false;
458 Features["sse3"] = false;
459 setXOPLevel(Features, NoXOP, false);
462 Features["ssse3"] = false;
465 Features["sse4.1"] = false;
468 Features["sse4.2"] = false;
471 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
472 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
473 setXOPLevel(Features, FMA4, false);
476 Features["avx2"] = false;
479 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
480 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
481 Features["avx512vl"] = Features["avx512vbmi"] =
482 Features["avx512ifma"] = Features["avx512vpopcntdq"] =
483 Features["avx512bitalg"] = Features["avx512vnni"] =
484 Features["avx512vbmi2"] = false;
489 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
490 MMX3DNowEnum Level, bool Enabled) {
494 Features["3dnowa"] = true;
497 Features["3dnow"] = true;
500 Features["mmx"] = true;
511 Features["mmx"] = false;
514 Features["3dnow"] = false;
517 Features["3dnowa"] = false;
522 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
527 Features["xop"] = true;
530 Features["fma4"] = true;
531 setSSELevel(Features, AVX, true);
534 Features["sse4a"] = true;
535 setSSELevel(Features, SSE3, true);
546 Features["sse4a"] = false;
549 Features["fma4"] = false;
552 Features["xop"] = false;
557 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
558 StringRef Name, bool Enabled) {
559 // This is a bit of a hack to deal with the sse4 target feature when used
560 // as part of the target attribute. We handle sse4 correctly everywhere
561 // else. See below for more information on how we handle the sse4 options.
563 Features[Name] = Enabled;
566 setMMXLevel(Features, MMX, Enabled);
567 } else if (Name == "sse") {
568 setSSELevel(Features, SSE1, Enabled);
569 } else if (Name == "sse2") {
570 setSSELevel(Features, SSE2, Enabled);
571 } else if (Name == "sse3") {
572 setSSELevel(Features, SSE3, Enabled);
573 } else if (Name == "ssse3") {
574 setSSELevel(Features, SSSE3, Enabled);
575 } else if (Name == "sse4.2") {
576 setSSELevel(Features, SSE42, Enabled);
577 } else if (Name == "sse4.1") {
578 setSSELevel(Features, SSE41, Enabled);
579 } else if (Name == "3dnow") {
580 setMMXLevel(Features, AMD3DNow, Enabled);
581 } else if (Name == "3dnowa") {
582 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
583 } else if (Name == "aes") {
585 setSSELevel(Features, SSE2, Enabled);
587 Features["vaes"] = false;
588 } else if (Name == "vaes") {
590 setSSELevel(Features, AVX, Enabled);
591 Features["aes"] = true;
593 } else if (Name == "pclmul") {
595 setSSELevel(Features, SSE2, Enabled);
597 Features["vpclmulqdq"] = false;
598 } else if (Name == "vpclmulqdq") {
600 setSSELevel(Features, AVX, Enabled);
601 Features["pclmul"] = true;
603 } else if (Name == "gfni") {
605 setSSELevel(Features, SSE2, Enabled);
606 } else if (Name == "avx") {
607 setSSELevel(Features, AVX, Enabled);
608 } else if (Name == "avx2") {
609 setSSELevel(Features, AVX2, Enabled);
610 } else if (Name == "avx512f") {
611 setSSELevel(Features, AVX512F, Enabled);
612 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
613 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
614 Name == "avx512vbmi" || Name == "avx512ifma" ||
615 Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
616 Name == "avx512vnni" || Name == "avx512vbmi2") {
618 setSSELevel(Features, AVX512F, Enabled);
619 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
620 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
621 Features["avx512bw"] = true;
622 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
623 if (Name == "avx512bw" && !Enabled)
624 Features["avx512vbmi"] = Features["avx512vbmi2"] =
625 Features["avx512bitalg"] = false;
626 } else if (Name == "fma") {
628 setSSELevel(Features, AVX, Enabled);
629 } else if (Name == "fma4") {
630 setXOPLevel(Features, FMA4, Enabled);
631 } else if (Name == "xop") {
632 setXOPLevel(Features, XOP, Enabled);
633 } else if (Name == "sse4a") {
634 setXOPLevel(Features, SSE4A, Enabled);
635 } else if (Name == "f16c") {
637 setSSELevel(Features, AVX, Enabled);
638 } else if (Name == "sha") {
640 setSSELevel(Features, SSE2, Enabled);
641 } else if (Name == "sse4") {
642 // We can get here via the __target__ attribute since that's not controlled
643 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
644 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
647 setSSELevel(Features, SSE42, Enabled);
649 setSSELevel(Features, SSE41, Enabled);
650 } else if (Name == "xsave") {
652 Features["xsaveopt"] = false;
653 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
655 Features["xsave"] = true;
659 /// handleTargetFeatures - Perform initialization based on the user
660 /// configured set of features.
661 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
662 DiagnosticsEngine &Diags) {
663 for (const auto &Feature : Features) {
664 if (Feature[0] != '+')
667 if (Feature == "+aes") {
669 } else if (Feature == "+vaes") {
671 } else if (Feature == "+pclmul") {
673 } else if (Feature == "+vpclmulqdq") {
674 HasVPCLMULQDQ = true;
675 } else if (Feature == "+lzcnt") {
677 } else if (Feature == "+rdrnd") {
679 } else if (Feature == "+fsgsbase") {
681 } else if (Feature == "+bmi") {
683 } else if (Feature == "+bmi2") {
685 } else if (Feature == "+popcnt") {
687 } else if (Feature == "+rtm") {
689 } else if (Feature == "+prfchw") {
691 } else if (Feature == "+rdseed") {
693 } else if (Feature == "+adx") {
695 } else if (Feature == "+tbm") {
697 } else if (Feature == "+lwp") {
699 } else if (Feature == "+fma") {
701 } else if (Feature == "+f16c") {
703 } else if (Feature == "+gfni") {
705 } else if (Feature == "+avx512cd") {
707 } else if (Feature == "+avx512vpopcntdq") {
708 HasAVX512VPOPCNTDQ = true;
709 } else if (Feature == "+avx512vnni") {
710 HasAVX512VNNI = true;
711 } else if (Feature == "+avx512er") {
713 } else if (Feature == "+avx512pf") {
715 } else if (Feature == "+avx512dq") {
717 } else if (Feature == "+avx512bitalg") {
718 HasAVX512BITALG = true;
719 } else if (Feature == "+avx512bw") {
721 } else if (Feature == "+avx512vl") {
723 } else if (Feature == "+avx512vbmi") {
724 HasAVX512VBMI = true;
725 } else if (Feature == "+avx512vbmi2") {
726 HasAVX512VBMI2 = true;
727 } else if (Feature == "+avx512ifma") {
728 HasAVX512IFMA = true;
729 } else if (Feature == "+sha") {
731 } else if (Feature == "+mpx") {
733 } else if (Feature == "+shstk") {
735 } else if (Feature == "+ibt") {
737 } else if (Feature == "+movbe") {
739 } else if (Feature == "+sgx") {
741 } else if (Feature == "+cx16") {
743 } else if (Feature == "+fxsr") {
745 } else if (Feature == "+xsave") {
747 } else if (Feature == "+xsaveopt") {
749 } else if (Feature == "+xsavec") {
751 } else if (Feature == "+xsaves") {
753 } else if (Feature == "+mwaitx") {
755 } else if (Feature == "+pku") {
757 } else if (Feature == "+clflushopt") {
758 HasCLFLUSHOPT = true;
759 } else if (Feature == "+clwb") {
761 } else if (Feature == "+prefetchwt1") {
762 HasPREFETCHWT1 = true;
763 } else if (Feature == "+clzero") {
767 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
768 .Case("+avx512f", AVX512F)
771 .Case("+sse4.2", SSE42)
772 .Case("+sse4.1", SSE41)
773 .Case("+ssse3", SSSE3)
778 SSELevel = std::max(SSELevel, Level);
780 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
781 .Case("+3dnowa", AMD3DNowAthlon)
782 .Case("+3dnow", AMD3DNow)
784 .Default(NoMMX3DNow);
785 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
787 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
790 .Case("+sse4a", SSE4A)
792 XOPLevel = std::max(XOPLevel, XLevel);
795 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
796 // matches the selected sse level.
797 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
798 (FPMath == FP_387 && SSELevel >= SSE1)) {
799 Diags.Report(diag::err_target_unsupported_fpmath)
800 << (FPMath == FP_SSE ? "sse" : "387");
805 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
809 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
810 /// definitions for this particular subtarget.
811 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
812 MacroBuilder &Builder) const {
813 // Target identification.
814 if (getTriple().getArch() == llvm::Triple::x86_64) {
815 Builder.defineMacro("__amd64__");
816 Builder.defineMacro("__amd64");
817 Builder.defineMacro("__x86_64");
818 Builder.defineMacro("__x86_64__");
819 if (getTriple().getArchName() == "x86_64h") {
820 Builder.defineMacro("__x86_64h");
821 Builder.defineMacro("__x86_64h__");
824 DefineStd(Builder, "i386", Opts);
827 // Subtarget options.
828 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
829 // truly should be based on -mtune options.
834 // The rest are coming from the i386 define above.
835 Builder.defineMacro("__tune_i386__");
841 defineCPUMacros(Builder, "i486");
844 Builder.defineMacro("__pentium_mmx__");
845 Builder.defineMacro("__tune_pentium_mmx__");
849 defineCPUMacros(Builder, "i586");
850 defineCPUMacros(Builder, "pentium");
854 Builder.defineMacro("__tune_pentium3__");
858 Builder.defineMacro("__tune_pentium2__");
861 defineCPUMacros(Builder, "i686");
862 defineCPUMacros(Builder, "pentiumpro");
865 defineCPUMacros(Builder, "pentium4");
870 defineCPUMacros(Builder, "nocona");
874 defineCPUMacros(Builder, "core2");
877 defineCPUMacros(Builder, "atom");
880 defineCPUMacros(Builder, "slm");
883 defineCPUMacros(Builder, "goldmont");
891 case CK_SkylakeClient:
892 case CK_SkylakeServer:
895 // FIXME: Historically, we defined this legacy name, it would be nice to
896 // remove it at some point. We've never exposed fine-grained names for
897 // recent primary x86 CPUs, and we should keep it that way.
898 defineCPUMacros(Builder, "corei7");
901 defineCPUMacros(Builder, "knl");
906 defineCPUMacros(Builder, "i586", /*Tuning*/false);
907 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
908 Builder.defineMacro("__tune_lakemont__");
911 Builder.defineMacro("__k6_2__");
912 Builder.defineMacro("__tune_k6_2__");
915 if (CPU != CK_K6_2) { // In case of fallthrough
916 // FIXME: GCC may be enabling these in cases where some other k6
917 // architecture is specified but -m3dnow is explicitly provided. The
918 // exact semantics need to be determined and emulated here.
919 Builder.defineMacro("__k6_3__");
920 Builder.defineMacro("__tune_k6_3__");
924 defineCPUMacros(Builder, "k6");
928 defineCPUMacros(Builder, "athlon");
929 if (SSELevel != NoSSE) {
930 Builder.defineMacro("__athlon_sse__");
931 Builder.defineMacro("__tune_athlon_sse__");
937 defineCPUMacros(Builder, "k8");
940 defineCPUMacros(Builder, "amdfam10");
943 defineCPUMacros(Builder, "btver1");
946 defineCPUMacros(Builder, "btver2");
949 defineCPUMacros(Builder, "bdver1");
952 defineCPUMacros(Builder, "bdver2");
955 defineCPUMacros(Builder, "bdver3");
958 defineCPUMacros(Builder, "bdver4");
961 defineCPUMacros(Builder, "znver1");
964 defineCPUMacros(Builder, "geode");
968 // Target properties.
969 Builder.defineMacro("__REGISTER_PREFIX__", "");
971 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
972 // functions in glibc header files that use FP Stack inline asm which the
973 // backend can't deal with (PR879).
974 Builder.defineMacro("__NO_MATH_INLINES");
977 Builder.defineMacro("__AES__");
980 Builder.defineMacro("__VAES__");
983 Builder.defineMacro("__PCLMUL__");
986 Builder.defineMacro("__VPCLMULQDQ__");
989 Builder.defineMacro("__LZCNT__");
992 Builder.defineMacro("__RDRND__");
995 Builder.defineMacro("__FSGSBASE__");
998 Builder.defineMacro("__BMI__");
1001 Builder.defineMacro("__BMI2__");
1004 Builder.defineMacro("__POPCNT__");
1007 Builder.defineMacro("__RTM__");
1010 Builder.defineMacro("__PRFCHW__");
1013 Builder.defineMacro("__RDSEED__");
1016 Builder.defineMacro("__ADX__");
1019 Builder.defineMacro("__TBM__");
1022 Builder.defineMacro("__LWP__");
1025 Builder.defineMacro("__MWAITX__");
1029 Builder.defineMacro("__XOP__");
1032 Builder.defineMacro("__FMA4__");
1035 Builder.defineMacro("__SSE4A__");
1042 Builder.defineMacro("__FMA__");
1045 Builder.defineMacro("__F16C__");
1048 Builder.defineMacro("__GFNI__");
1051 Builder.defineMacro("__AVX512CD__");
1052 if (HasAVX512VPOPCNTDQ)
1053 Builder.defineMacro("__AVX512VPOPCNTDQ__");
1055 Builder.defineMacro("__AVX512VNNI__");
1057 Builder.defineMacro("__AVX512ER__");
1059 Builder.defineMacro("__AVX512PF__");
1061 Builder.defineMacro("__AVX512DQ__");
1062 if (HasAVX512BITALG)
1063 Builder.defineMacro("__AVX512BITALG__");
1065 Builder.defineMacro("__AVX512BW__");
1067 Builder.defineMacro("__AVX512VL__");
1069 Builder.defineMacro("__AVX512VBMI__");
1071 Builder.defineMacro("__AVX512VBMI2__");
1073 Builder.defineMacro("__AVX512IFMA__");
1076 Builder.defineMacro("__SHA__");
1079 Builder.defineMacro("__FXSR__");
1081 Builder.defineMacro("__XSAVE__");
1083 Builder.defineMacro("__XSAVEOPT__");
1085 Builder.defineMacro("__XSAVEC__");
1087 Builder.defineMacro("__XSAVES__");
1089 Builder.defineMacro("__PKU__");
1091 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1093 Builder.defineMacro("__CLFLUSHOPT__");
1095 Builder.defineMacro("__CLWB__");
1097 Builder.defineMacro("__MPX__");
1099 Builder.defineMacro("__SHSTK__");
1101 Builder.defineMacro("__SGX__");
1103 Builder.defineMacro("__PREFETCHWT1__");
1105 Builder.defineMacro("__CLZERO__");
1107 // Each case falls through to the previous one here.
1110 Builder.defineMacro("__AVX512F__");
1113 Builder.defineMacro("__AVX2__");
1116 Builder.defineMacro("__AVX__");
1119 Builder.defineMacro("__SSE4_2__");
1122 Builder.defineMacro("__SSE4_1__");
1125 Builder.defineMacro("__SSSE3__");
1128 Builder.defineMacro("__SSE3__");
1131 Builder.defineMacro("__SSE2__");
1132 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1135 Builder.defineMacro("__SSE__");
1136 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1142 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1152 Builder.defineMacro("_M_IX86_FP", Twine(2));
1155 Builder.defineMacro("_M_IX86_FP", Twine(1));
1158 Builder.defineMacro("_M_IX86_FP", Twine(0));
1163 // Each case falls through to the previous one here.
1164 switch (MMX3DNowLevel) {
1165 case AMD3DNowAthlon:
1166 Builder.defineMacro("__3dNOW_A__");
1169 Builder.defineMacro("__3dNOW__");
1172 Builder.defineMacro("__MMX__");
1178 if (CPU >= CK_i486) {
1179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1184 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1187 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1190 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1191 return llvm::StringSwitch<bool>(Name)
1192 .Case("3dnow", true)
1193 .Case("3dnowa", true)
1198 .Case("avx512f", true)
1199 .Case("avx512cd", true)
1200 .Case("avx512vpopcntdq", true)
1201 .Case("avx512vnni", true)
1202 .Case("avx512er", true)
1203 .Case("avx512pf", true)
1204 .Case("avx512dq", true)
1205 .Case("avx512bitalg", true)
1206 .Case("avx512bw", true)
1207 .Case("avx512vl", true)
1208 .Case("avx512vbmi", true)
1209 .Case("avx512vbmi2", true)
1210 .Case("avx512ifma", true)
1213 .Case("clflushopt", true)
1215 .Case("clzero", true)
1220 .Case("fsgsbase", true)
1224 .Case("lzcnt", true)
1226 .Case("movbe", true)
1228 .Case("mwaitx", true)
1229 .Case("pclmul", true)
1231 .Case("popcnt", true)
1232 .Case("prefetchwt1", true)
1233 .Case("prfchw", true)
1234 .Case("rdrnd", true)
1235 .Case("rdseed", true)
1239 .Case("shstk", true)
1243 .Case("ssse3", true)
1245 .Case("sse4.1", true)
1246 .Case("sse4.2", true)
1247 .Case("sse4a", true)
1250 .Case("vpclmulqdq", true)
1253 .Case("xsave", true)
1254 .Case("xsavec", true)
1255 .Case("xsaves", true)
1256 .Case("xsaveopt", true)
1260 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1261 return llvm::StringSwitch<bool>(Feature)
1262 .Case("adx", HasADX)
1263 .Case("aes", HasAES)
1264 .Case("avx", SSELevel >= AVX)
1265 .Case("avx2", SSELevel >= AVX2)
1266 .Case("avx512f", SSELevel >= AVX512F)
1267 .Case("avx512cd", HasAVX512CD)
1268 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1269 .Case("avx512vnni", HasAVX512VNNI)
1270 .Case("avx512er", HasAVX512ER)
1271 .Case("avx512pf", HasAVX512PF)
1272 .Case("avx512dq", HasAVX512DQ)
1273 .Case("avx512bitalg", HasAVX512BITALG)
1274 .Case("avx512bw", HasAVX512BW)
1275 .Case("avx512vl", HasAVX512VL)
1276 .Case("avx512vbmi", HasAVX512VBMI)
1277 .Case("avx512vbmi2", HasAVX512VBMI2)
1278 .Case("avx512ifma", HasAVX512IFMA)
1279 .Case("bmi", HasBMI)
1280 .Case("bmi2", HasBMI2)
1281 .Case("clflushopt", HasCLFLUSHOPT)
1282 .Case("clwb", HasCLWB)
1283 .Case("clzero", HasCLZERO)
1284 .Case("cx16", HasCX16)
1285 .Case("f16c", HasF16C)
1286 .Case("fma", HasFMA)
1287 .Case("fma4", XOPLevel >= FMA4)
1288 .Case("fsgsbase", HasFSGSBASE)
1289 .Case("fxsr", HasFXSR)
1290 .Case("gfni", HasGFNI)
1291 .Case("ibt", HasIBT)
1292 .Case("lwp", HasLWP)
1293 .Case("lzcnt", HasLZCNT)
1294 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1295 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1296 .Case("mmx", MMX3DNowLevel >= MMX)
1297 .Case("movbe", HasMOVBE)
1298 .Case("mpx", HasMPX)
1299 .Case("mwaitx", HasMWAITX)
1300 .Case("pclmul", HasPCLMUL)
1301 .Case("pku", HasPKU)
1302 .Case("popcnt", HasPOPCNT)
1303 .Case("prefetchwt1", HasPREFETCHWT1)
1304 .Case("prfchw", HasPRFCHW)
1305 .Case("rdrnd", HasRDRND)
1306 .Case("rdseed", HasRDSEED)
1307 .Case("rtm", HasRTM)
1308 .Case("sgx", HasSGX)
1309 .Case("sha", HasSHA)
1310 .Case("shstk", HasSHSTK)
1311 .Case("sse", SSELevel >= SSE1)
1312 .Case("sse2", SSELevel >= SSE2)
1313 .Case("sse3", SSELevel >= SSE3)
1314 .Case("ssse3", SSELevel >= SSSE3)
1315 .Case("sse4.1", SSELevel >= SSE41)
1316 .Case("sse4.2", SSELevel >= SSE42)
1317 .Case("sse4a", XOPLevel >= SSE4A)
1318 .Case("tbm", HasTBM)
1319 .Case("vaes", HasVAES)
1320 .Case("vpclmulqdq", HasVPCLMULQDQ)
1322 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1323 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1324 .Case("xop", XOPLevel >= XOP)
1325 .Case("xsave", HasXSAVE)
1326 .Case("xsavec", HasXSAVEC)
1327 .Case("xsaves", HasXSAVES)
1328 .Case("xsaveopt", HasXSAVEOPT)
1332 // We can't use a generic validation scheme for the features accepted here
1333 // versus subtarget features accepted in the target attribute because the
1334 // bitfield structure that's initialized in the runtime only supports the
1335 // below currently rather than the full range of subtarget features. (See
1336 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1337 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1338 return llvm::StringSwitch<bool>(FeatureStr)
1339 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1340 #include "llvm/Support/X86TargetParser.def"
1344 // We can't use a generic validation scheme for the cpus accepted here
1345 // versus subtarget cpus accepted in the target attribute because the
1346 // variables intitialized by the runtime only support the below currently
1347 // rather than the full range of cpus.
1348 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1349 return llvm::StringSwitch<bool>(FeatureStr)
1350 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1351 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1352 .Cases(STR, ALIAS, true)
1353 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1354 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1355 #include "llvm/Support/X86TargetParser.def"
1359 bool X86TargetInfo::validateAsmConstraint(
1360 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1364 // Constant constraints.
1365 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1367 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1368 // x86_64 instructions.
1370 Info.setRequiresImmediate();
1373 Info.setRequiresImmediate(0, 31);
1376 Info.setRequiresImmediate(0, 63);
1379 Info.setRequiresImmediate(-128, 127);
1382 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1385 Info.setRequiresImmediate(0, 3);
1388 Info.setRequiresImmediate(0, 255);
1391 Info.setRequiresImmediate(0, 127);
1393 // Register constraints.
1394 case 'Y': // 'Y' is the first character for several 2-character constraints.
1395 // Shift the pointer to the second character of the constraint.
1401 case '0': // First SSE register.
1403 case 't': // Any SSE register, when SSE2 is enabled.
1404 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1405 case 'm': // Any MMX register, when inter-unit moves enabled.
1406 case 'k': // AVX512 arch mask registers: k1-k7.
1407 Info.setAllowsRegister();
1410 case 'f': // Any x87 floating point stack register.
1411 // Constraint 'f' cannot be used for output operands.
1412 if (Info.ConstraintStr[0] == '=')
1414 Info.setAllowsRegister();
1422 case 'A': // edx:eax.
1423 case 't': // Top of floating point stack.
1424 case 'u': // Second from top of floating point stack.
1425 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1426 case 'y': // Any MMX register.
1427 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1428 case 'x': // Any SSE register.
1429 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
1430 // for intermideate k reg operations).
1431 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1432 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1433 case 'l': // "Index" registers: any general register that can be used as an
1434 // index in a base+index memory access.
1435 Info.setAllowsRegister();
1437 // Floating point constant constraints.
1438 case 'C': // SSE floating point constant.
1439 case 'G': // x87 floating point constant.
1444 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1445 unsigned Size) const {
1446 // Strip off constraint modifiers.
1447 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1448 Constraint = Constraint.substr(1);
1450 return validateOperandSize(Constraint, Size);
1453 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1454 unsigned Size) const {
1455 return validateOperandSize(Constraint, Size);
1458 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1459 unsigned Size) const {
1460 switch (Constraint[0]) {
1464 // Registers k0-k7 (AVX512) size limit is 64 bit.
1472 // 'Y' is the first character for several 2-character constraints.
1473 switch (Constraint[1]) {
1477 // 'Ym' is synonymous with 'y'.
1483 if (SSELevel >= SSE1)
1484 return Size <= 128U;
1489 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1490 if (SSELevel < SSE2)
1496 if (SSELevel >= AVX512F)
1497 // 512-bit zmm registers can be used if target supports AVX512F.
1498 return Size <= 512U;
1499 else if (SSELevel >= AVX)
1500 // 256-bit ymm registers can be used if target supports AVX.
1501 return Size <= 256U;
1502 return Size <= 128U;
1509 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1510 switch (*Constraint) {
1512 return std::string("{ax}");
1514 return std::string("{bx}");
1516 return std::string("{cx}");
1518 return std::string("{dx}");
1520 return std::string("{si}");
1522 return std::string("{di}");
1523 case 'p': // address
1524 return std::string("im");
1525 case 't': // top of floating point stack.
1526 return std::string("{st}");
1527 case 'u': // second from top of floating point stack.
1528 return std::string("{st(1)}"); // second from top of floating point stack.
1530 switch (Constraint[1]) {
1532 // Break from inner switch and fall through (copy single char),
1533 // continue parsing after copying the current constraint into
1534 // the return string.
1543 // "^" hints llvm that this is a 2 letter constraint.
1544 // "Constraint++" is used to promote the string iterator
1545 // to the next constraint.
1546 return std::string("^") + std::string(Constraint++, 2);
1550 return std::string(1, *Constraint);
1554 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1555 // Perform any per-CPU checks necessary to determine if this CPU is
1557 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1558 // invalid without explaining *why*.
1561 // No processor selected!
1563 #define PROC(ENUM, STRING, IS64BIT) \
1565 return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1566 #include "clang/Basic/X86Target.def"
1568 llvm_unreachable("Unhandled CPU kind");
1571 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1572 return llvm::StringSwitch<CPUKind>(CPU)
1573 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1574 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1575 #include "clang/Basic/X86Target.def"
1576 .Default(CK_Generic);
1579 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1580 return llvm::makeArrayRef(GCCRegNames);
1583 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1584 return llvm::makeArrayRef(AddlRegNames);
1587 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1588 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1589 Builtin::FirstTSBuiltin + 1);
1592 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1593 return llvm::makeArrayRef(BuiltinInfoX86,
1594 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);