1 //===--- X86.h - Declare X86 target feature support -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares X86 TargetInfo objects.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
15 #define LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
17 #include "OSTargets.h"
18 #include "clang/Basic/TargetInfo.h"
19 #include "clang/Basic/TargetOptions.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/Support/Compiler.h"
26 // X86 target abstract base class; x86-32 and x86-64 are very close, so
27 // most of the implementation can be shared.
28 class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
47 } MMX3DNowLevel = NoMMX3DNow;
48 enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
52 bool HasPCLMUL = false;
53 bool HasVPCLMULQDQ = false;
55 bool HasLZCNT = false;
56 bool HasRDRND = false;
57 bool HasFSGSBASE = false;
60 bool HasPOPCNT = false;
62 bool HasPRFCHW = false;
63 bool HasRDSEED = false;
69 bool HasAVX512CD = false;
70 bool HasAVX512VPOPCNTDQ = false;
71 bool HasAVX512VNNI = false;
72 bool HasAVX512ER = false;
73 bool HasAVX512PF = false;
74 bool HasAVX512DQ = false;
75 bool HasAVX512BITALG = false;
76 bool HasAVX512BW = false;
77 bool HasAVX512VL = false;
78 bool HasAVX512VBMI = false;
79 bool HasAVX512VBMI2 = false;
80 bool HasAVX512IFMA = false;
83 bool HasSHSTK = false;
88 bool HasXSAVE = false;
89 bool HasXSAVEOPT = false;
90 bool HasXSAVEC = false;
91 bool HasXSAVES = false;
92 bool HasMWAITX = false;
93 bool HasCLZERO = false;
95 bool HasCLFLUSHOPT = false;
97 bool HasMOVBE = false;
98 bool HasPREFETCHWT1 = false;
100 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
102 /// Each enumeration represents a particular CPU supported by Clang. These
103 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
106 #define PROC(ENUM, STRING, IS64BIT) CK_##ENUM,
107 #include "clang/Basic/X86Target.def"
110 bool checkCPUKind(CPUKind Kind) const;
112 CPUKind getCPUKind(StringRef CPU) const;
114 enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default;
117 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
118 : TargetInfo(Triple) {
119 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
122 unsigned getFloatEvalMethod() const override {
123 // X87 evaluates with 80 bits "long double" precision.
124 return SSELevel == NoSSE ? 2 : 0;
127 ArrayRef<const char *> getGCCRegNames() const override;
129 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
133 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
135 bool validateCpuSupports(StringRef Name) const override;
137 bool validateCpuIs(StringRef Name) const override;
139 bool validateAsmConstraint(const char *&Name,
140 TargetInfo::ConstraintInfo &info) const override;
142 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
143 bool &HasSizeMismatch) const override {
144 // esp and ebp are the only 32-bit registers the x86 backend can currently
146 if (RegName.equals("esp") || RegName.equals("ebp")) {
147 // Check that the register size is 32-bit.
148 HasSizeMismatch = RegSize != 32;
155 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
157 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
159 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
161 std::string convertConstraint(const char *&Constraint) const override;
162 const char *getClobbers() const override {
163 return "~{dirflag},~{fpsr},~{flags}";
166 StringRef getConstraintRegister(const StringRef &Constraint,
167 const StringRef &Expression) const override {
168 StringRef::iterator I, E;
169 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
176 // For the register constraints, return the matching register name
189 // In case the constraint is 'r' we need to return Expression
192 // Double letters Y<x> constraints
194 if ((++I != E) && ((*I == '0') || (*I == 'z')))
202 bool useFP16ConversionIntrinsics() const override {
206 void getTargetDefines(const LangOptions &Opts,
207 MacroBuilder &Builder) const override;
209 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
212 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
215 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
218 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
219 bool Enabled) const override {
220 setFeatureEnabledImpl(Features, Name, Enabled);
223 // This exists purely to cut down on the number of virtual calls in
224 // initFeatureMap which calls this repeatedly.
225 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
226 StringRef Name, bool Enabled);
229 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
231 const std::vector<std::string> &FeaturesVec) const override;
233 bool isValidFeatureName(StringRef Name) const override;
235 bool hasFeature(StringRef Feature) const override;
237 bool handleTargetFeatures(std::vector<std::string> &Features,
238 DiagnosticsEngine &Diags) override;
240 StringRef getABI() const override {
241 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
243 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
245 if (getTriple().getArch() == llvm::Triple::x86 &&
246 MMX3DNowLevel == NoMMX3DNow)
251 bool isValidCPUName(StringRef Name) const override {
252 return checkCPUKind(getCPUKind(Name));
255 bool setCPU(const std::string &Name) override {
256 return checkCPUKind(CPU = getCPUKind(Name));
259 bool setFPMath(StringRef Name) override;
261 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
262 // Most of the non-ARM calling conventions are i386 conventions.
267 case CC_X86VectorCall:
272 case CC_IntelOclBicc:
273 case CC_OpenCLKernel:
280 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
281 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
284 bool hasSjLjLowering() const override { return true; }
286 void setSupportedOpenCLOpts() override {
287 getSupportedOpenCLOpts().supportAll();
291 // X86-32 generic target
292 class LLVM_LIBRARY_VISIBILITY X86_32TargetInfo : public X86TargetInfo {
294 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
295 : X86TargetInfo(Triple, Opts) {
296 DoubleAlign = LongLongAlign = 32;
297 LongDoubleWidth = 96;
298 LongDoubleAlign = 32;
300 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
301 SizeType = UnsignedInt;
302 PtrDiffType = SignedInt;
303 IntPtrType = SignedInt;
306 // Use fpret for all types.
307 RealTypeUsesObjCFPRet =
308 ((1 << TargetInfo::Float) | (1 << TargetInfo::Double) |
309 (1 << TargetInfo::LongDouble));
311 // x86-32 has atomics up to 8 bytes
312 // FIXME: Check that we actually have cmpxchg8b before setting
313 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
314 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
317 BuiltinVaListKind getBuiltinVaListKind() const override {
318 return TargetInfo::CharPtrBuiltinVaList;
321 int getEHDataRegisterNumber(unsigned RegNo) const override {
329 bool validateOperandSize(StringRef Constraint, unsigned Size) const override {
330 switch (Constraint[0]) {
347 return X86TargetInfo::validateOperandSize(Constraint, Size);
350 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
353 class LLVM_LIBRARY_VISIBILITY NetBSDI386TargetInfo
354 : public NetBSDTargetInfo<X86_32TargetInfo> {
356 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
357 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
359 unsigned getFloatEvalMethod() const override {
360 unsigned Major, Minor, Micro;
361 getTriple().getOSVersion(Major, Minor, Micro);
362 // New NetBSD uses the default rounding mode.
363 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
364 return X86_32TargetInfo::getFloatEvalMethod();
365 // NetBSD before 6.99.26 defaults to "double" rounding.
370 class LLVM_LIBRARY_VISIBILITY OpenBSDI386TargetInfo
371 : public OpenBSDTargetInfo<X86_32TargetInfo> {
373 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
374 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
375 SizeType = UnsignedLong;
376 IntPtrType = SignedLong;
377 PtrDiffType = SignedLong;
381 class LLVM_LIBRARY_VISIBILITY DarwinI386TargetInfo
382 : public DarwinTargetInfo<X86_32TargetInfo> {
384 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
385 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
386 LongDoubleWidth = 128;
387 LongDoubleAlign = 128;
389 MaxVectorAlign = 256;
390 // The watchOS simulator uses the builtin bool type for Objective-C.
391 llvm::Triple T = llvm::Triple(Triple);
393 UseSignedCharForObjCBool = false;
394 SizeType = UnsignedLong;
395 IntPtrType = SignedLong;
396 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
397 HasAlignMac68kSupport = true;
400 bool handleTargetFeatures(std::vector<std::string> &Features,
401 DiagnosticsEngine &Diags) override {
402 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
405 // We now know the features we have: we can decide how to align vectors.
407 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
412 // x86-32 Windows target
413 class LLVM_LIBRARY_VISIBILITY WindowsX86_32TargetInfo
414 : public WindowsTargetInfo<X86_32TargetInfo> {
416 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
417 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
418 DoubleAlign = LongLongAlign = 64;
420 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
421 resetDataLayout(IsWinCOFF
422 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
423 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
427 // x86-32 Windows Visual Studio target
428 class LLVM_LIBRARY_VISIBILITY MicrosoftX86_32TargetInfo
429 : public WindowsX86_32TargetInfo {
431 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
432 const TargetOptions &Opts)
433 : WindowsX86_32TargetInfo(Triple, Opts) {
434 LongDoubleWidth = LongDoubleAlign = 64;
435 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
438 void getTargetDefines(const LangOptions &Opts,
439 MacroBuilder &Builder) const override {
440 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
441 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
442 // The value of the following reflects processor type.
443 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
444 // We lost the original triple, so we use the default.
445 Builder.defineMacro("_M_IX86", "600");
449 // x86-32 MinGW target
450 class LLVM_LIBRARY_VISIBILITY MinGWX86_32TargetInfo
451 : public WindowsX86_32TargetInfo {
453 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
454 : WindowsX86_32TargetInfo(Triple, Opts) {
458 void getTargetDefines(const LangOptions &Opts,
459 MacroBuilder &Builder) const override {
460 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
461 Builder.defineMacro("_X86_");
465 // x86-32 Cygwin target
466 class LLVM_LIBRARY_VISIBILITY CygwinX86_32TargetInfo : public X86_32TargetInfo {
468 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
469 : X86_32TargetInfo(Triple, Opts) {
470 this->WCharType = TargetInfo::UnsignedShort;
471 DoubleAlign = LongLongAlign = 64;
472 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
475 void getTargetDefines(const LangOptions &Opts,
476 MacroBuilder &Builder) const override {
477 X86_32TargetInfo::getTargetDefines(Opts, Builder);
478 Builder.defineMacro("_X86_");
479 Builder.defineMacro("__CYGWIN__");
480 Builder.defineMacro("__CYGWIN32__");
481 addCygMingDefines(Opts, Builder);
482 DefineStd(Builder, "unix", Opts);
484 Builder.defineMacro("_GNU_SOURCE");
488 // x86-32 Haiku target
489 class LLVM_LIBRARY_VISIBILITY HaikuX86_32TargetInfo
490 : public HaikuTargetInfo<X86_32TargetInfo> {
492 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
493 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
495 void getTargetDefines(const LangOptions &Opts,
496 MacroBuilder &Builder) const override {
497 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
498 Builder.defineMacro("__INTEL__");
503 class LLVM_LIBRARY_VISIBILITY MCUX86_32TargetInfo : public X86_32TargetInfo {
505 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
506 : X86_32TargetInfo(Triple, Opts) {
507 LongDoubleWidth = 64;
508 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
509 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
510 WIntType = UnsignedInt;
513 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
514 // On MCU we support only C calling convention.
515 return CC == CC_C ? CCCR_OK : CCCR_Warning;
518 void getTargetDefines(const LangOptions &Opts,
519 MacroBuilder &Builder) const override {
520 X86_32TargetInfo::getTargetDefines(Opts, Builder);
521 Builder.defineMacro("__iamcu");
522 Builder.defineMacro("__iamcu__");
525 bool allowsLargerPreferedTypeAlignment() const override { return false; }
528 // x86-32 RTEMS target
529 class LLVM_LIBRARY_VISIBILITY RTEMSX86_32TargetInfo : public X86_32TargetInfo {
531 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
532 : X86_32TargetInfo(Triple, Opts) {
533 SizeType = UnsignedLong;
534 IntPtrType = SignedLong;
535 PtrDiffType = SignedLong;
538 void getTargetDefines(const LangOptions &Opts,
539 MacroBuilder &Builder) const override {
540 X86_32TargetInfo::getTargetDefines(Opts, Builder);
541 Builder.defineMacro("__INTEL__");
542 Builder.defineMacro("__rtems__");
546 // x86-64 generic target
547 class LLVM_LIBRARY_VISIBILITY X86_64TargetInfo : public X86TargetInfo {
549 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
550 : X86TargetInfo(Triple, Opts) {
551 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
553 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
554 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
555 LongDoubleWidth = 128;
556 LongDoubleAlign = 128;
557 LargeArrayMinWidth = 128;
558 LargeArrayAlign = 128;
560 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
561 PtrDiffType = IsX32 ? SignedInt : SignedLong;
562 IntPtrType = IsX32 ? SignedInt : SignedLong;
563 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
564 Int64Type = IsX32 ? SignedLongLong : SignedLong;
567 // Pointers are 32-bit in x32.
568 resetDataLayout(IsX32
569 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
570 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
571 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
573 // Use fpret only for long double.
574 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
576 // Use fp2ret for _Complex long double.
577 ComplexLongDoubleUsesFP2Ret = true;
579 // Make __builtin_ms_va_list available.
580 HasBuiltinMSVaList = true;
582 // x86-64 has atomics up to 16 bytes.
583 MaxAtomicPromoteWidth = 128;
584 MaxAtomicInlineWidth = 64;
587 BuiltinVaListKind getBuiltinVaListKind() const override {
588 return TargetInfo::X86_64ABIBuiltinVaList;
591 int getEHDataRegisterNumber(unsigned RegNo) const override {
599 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
603 case CC_X86VectorCall:
604 case CC_IntelOclBicc:
606 case CC_PreserveMost:
609 case CC_OpenCLKernel:
616 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
620 // for x32 we need it here explicitly
621 bool hasInt128Type() const override { return true; }
623 unsigned getUnwindWordWidth() const override { return 64; }
625 unsigned getRegisterWidth() const override { return 64; }
627 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
628 bool &HasSizeMismatch) const override {
629 // rsp and rbp are the only 64-bit registers the x86 backend can currently
631 if (RegName.equals("rsp") || RegName.equals("rbp")) {
632 // Check that the register size is 64-bit.
633 HasSizeMismatch = RegSize != 64;
637 // Check if the register is a 32-bit register the backend can handle.
638 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
642 void setMaxAtomicWidth() override {
643 if (hasFeature("cx16"))
644 MaxAtomicInlineWidth = 128;
647 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
650 // x86-64 Windows target
651 class LLVM_LIBRARY_VISIBILITY WindowsX86_64TargetInfo
652 : public WindowsTargetInfo<X86_64TargetInfo> {
654 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
655 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
656 LongWidth = LongAlign = 32;
657 DoubleAlign = LongLongAlign = 64;
658 IntMaxType = SignedLongLong;
659 Int64Type = SignedLongLong;
660 SizeType = UnsignedLongLong;
661 PtrDiffType = SignedLongLong;
662 IntPtrType = SignedLongLong;
665 BuiltinVaListKind getBuiltinVaListKind() const override {
666 return TargetInfo::CharPtrBuiltinVaList;
669 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
676 case CC_X86VectorCall:
677 case CC_IntelOclBicc:
678 case CC_PreserveMost:
683 case CC_OpenCLKernel:
691 // x86-64 Windows Visual Studio target
692 class LLVM_LIBRARY_VISIBILITY MicrosoftX86_64TargetInfo
693 : public WindowsX86_64TargetInfo {
695 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
696 const TargetOptions &Opts)
697 : WindowsX86_64TargetInfo(Triple, Opts) {
698 LongDoubleWidth = LongDoubleAlign = 64;
699 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
702 void getTargetDefines(const LangOptions &Opts,
703 MacroBuilder &Builder) const override {
704 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
705 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
706 Builder.defineMacro("_M_X64", "100");
707 Builder.defineMacro("_M_AMD64", "100");
711 // x86-64 MinGW target
712 class LLVM_LIBRARY_VISIBILITY MinGWX86_64TargetInfo
713 : public WindowsX86_64TargetInfo {
715 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
716 : WindowsX86_64TargetInfo(Triple, Opts) {
717 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
718 // with x86 FP ops. Weird.
719 LongDoubleWidth = LongDoubleAlign = 128;
720 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
725 // x86-64 Cygwin target
726 class LLVM_LIBRARY_VISIBILITY CygwinX86_64TargetInfo : public X86_64TargetInfo {
728 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
729 : X86_64TargetInfo(Triple, Opts) {
730 this->WCharType = TargetInfo::UnsignedShort;
731 TLSSupported = false;
734 void getTargetDefines(const LangOptions &Opts,
735 MacroBuilder &Builder) const override {
736 X86_64TargetInfo::getTargetDefines(Opts, Builder);
737 Builder.defineMacro("__x86_64__");
738 Builder.defineMacro("__CYGWIN__");
739 Builder.defineMacro("__CYGWIN64__");
740 addCygMingDefines(Opts, Builder);
741 DefineStd(Builder, "unix", Opts);
743 Builder.defineMacro("_GNU_SOURCE");
747 class LLVM_LIBRARY_VISIBILITY DarwinX86_64TargetInfo
748 : public DarwinTargetInfo<X86_64TargetInfo> {
750 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
751 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
752 Int64Type = SignedLongLong;
753 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
754 llvm::Triple T = llvm::Triple(Triple);
756 UseSignedCharForObjCBool = false;
757 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
760 bool handleTargetFeatures(std::vector<std::string> &Features,
761 DiagnosticsEngine &Diags) override {
762 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
765 // We now know the features we have: we can decide how to align vectors.
767 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
772 class LLVM_LIBRARY_VISIBILITY OpenBSDX86_64TargetInfo
773 : public OpenBSDTargetInfo<X86_64TargetInfo> {
775 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
776 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
777 IntMaxType = SignedLongLong;
778 Int64Type = SignedLongLong;
782 // x86_32 Android target
783 class LLVM_LIBRARY_VISIBILITY AndroidX86_32TargetInfo
784 : public LinuxTargetInfo<X86_32TargetInfo> {
786 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
787 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
789 LongDoubleWidth = 64;
790 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
794 // x86_64 Android target
795 class LLVM_LIBRARY_VISIBILITY AndroidX86_64TargetInfo
796 : public LinuxTargetInfo<X86_64TargetInfo> {
798 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
799 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
800 LongDoubleFormat = &llvm::APFloat::IEEEquad();
803 bool useFloat128ManglingForLongDouble() const override { return true; }
805 } // namespace targets
807 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_X86_H