1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Cuda.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetInfo.h"
22 #include "clang/Basic/TargetOptions.h"
23 #include "clang/Basic/Version.h"
24 #include "clang/Frontend/CodeGenOptions.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/TargetParser.h"
37 using namespace clang;
39 //===----------------------------------------------------------------------===//
40 // Common code shared among targets.
41 //===----------------------------------------------------------------------===//
43 /// DefineStd - Define a macro name and standard variants. For example if
44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
47 const LangOptions &Opts) {
48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
51 // in the user's namespace.
53 Builder.defineMacro(MacroName);
56 Builder.defineMacro("__" + MacroName);
59 Builder.defineMacro("__" + MacroName + "__");
62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
64 Builder.defineMacro("__" + CPUName);
65 Builder.defineMacro("__" + CPUName + "__");
67 Builder.defineMacro("__tune_" + CPUName + "__");
70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
71 const TargetOptions &Opts);
73 //===----------------------------------------------------------------------===//
74 // Defines specific to certain operating systems.
75 //===----------------------------------------------------------------------===//
78 template<typename TgtInfo>
79 class OSTargetInfo : public TgtInfo {
81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
82 MacroBuilder &Builder) const=0;
84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
85 : TgtInfo(Triple, Opts) {}
86 void getTargetDefines(const LangOptions &Opts,
87 MacroBuilder &Builder) const override {
88 TgtInfo::getTargetDefines(Opts, Builder);
89 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
95 template <typename Target>
96 class CloudABITargetInfo : public OSTargetInfo<Target> {
98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
99 MacroBuilder &Builder) const override {
100 Builder.defineMacro("__CloudABI__");
101 Builder.defineMacro("__ELF__");
103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
104 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
105 Builder.defineMacro("__STDC_UTF_16__");
106 Builder.defineMacro("__STDC_UTF_32__");
110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
111 : OSTargetInfo<Target>(Triple, Opts) {}
115 template<typename Target>
116 class AnanasTargetInfo : public OSTargetInfo<Target> {
118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
119 MacroBuilder &Builder) const override {
121 Builder.defineMacro("__Ananas__");
122 Builder.defineMacro("__ELF__");
125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
126 : OSTargetInfo<Target>(Triple, Opts) {}
129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
130 const llvm::Triple &Triple,
131 StringRef &PlatformName,
132 VersionTuple &PlatformMinVersion) {
133 Builder.defineMacro("__APPLE_CC__", "6000");
134 Builder.defineMacro("__APPLE__");
135 Builder.defineMacro("__STDC_NO_THREADS__");
136 Builder.defineMacro("OBJC_NEW_PROPERTIES");
137 // AddressSanitizer doesn't play well with source fortification, which is on
138 // by default on Darwin.
139 if (Opts.Sanitize.has(SanitizerKind::Address))
140 Builder.defineMacro("_FORTIFY_SOURCE", "0");
142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
144 // __weak is always defined, for use in blocks and with objc pointers.
145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
146 Builder.defineMacro("__strong", "");
147 Builder.defineMacro("__unsafe_unretained", "");
151 Builder.defineMacro("__STATIC__");
153 Builder.defineMacro("__DYNAMIC__");
155 if (Opts.POSIXThreads)
156 Builder.defineMacro("_REENTRANT");
158 // Get the platform type and version number from the triple.
159 unsigned Maj, Min, Rev;
160 if (Triple.isMacOSX()) {
161 Triple.getMacOSXVersion(Maj, Min, Rev);
162 PlatformName = "macos";
164 Triple.getOSVersion(Maj, Min, Rev);
165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
168 // If -target arch-pc-win32-macho option specified, we're
169 // generating code for Win32 ABI. No need to emit
170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
171 if (PlatformName == "win32") {
172 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
176 // Set the appropriate OS version define.
177 if (Triple.isiOS()) {
178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
182 Str[1] = '0' + (Min / 10);
183 Str[2] = '0' + (Min % 10);
184 Str[3] = '0' + (Rev / 10);
185 Str[4] = '0' + (Rev % 10);
188 // Handle versions >= 10.
189 Str[0] = '0' + (Maj / 10);
190 Str[1] = '0' + (Maj % 10);
191 Str[2] = '0' + (Min / 10);
192 Str[3] = '0' + (Min % 10);
193 Str[4] = '0' + (Rev / 10);
194 Str[5] = '0' + (Rev % 10);
198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
203 } else if (Triple.isWatchOS()) {
204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
207 Str[1] = '0' + (Min / 10);
208 Str[2] = '0' + (Min % 10);
209 Str[3] = '0' + (Rev / 10);
210 Str[4] = '0' + (Rev % 10);
212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
213 } else if (Triple.isMacOSX()) {
214 // Note that the Driver allows versions which aren't representable in the
215 // define (because we only get a single digit for the minor and micro
216 // revision numbers). So, we limit them to the maximum representable
218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
220 if (Maj < 10 || (Maj == 10 && Min < 10)) {
221 Str[0] = '0' + (Maj / 10);
222 Str[1] = '0' + (Maj % 10);
223 Str[2] = '0' + std::min(Min, 9U);
224 Str[3] = '0' + std::min(Rev, 9U);
227 // Handle versions > 10.9.
228 Str[0] = '0' + (Maj / 10);
229 Str[1] = '0' + (Maj % 10);
230 Str[2] = '0' + (Min / 10);
231 Str[3] = '0' + (Min % 10);
232 Str[4] = '0' + (Rev / 10);
233 Str[5] = '0' + (Rev % 10);
236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
239 // Tell users about the kernel if there is one.
240 if (Triple.isOSDarwin())
241 Builder.defineMacro("__MACH__");
243 // The Watch ABI uses Dwarf EH.
244 if(Triple.isWatchABI())
245 Builder.defineMacro("__ARM_DWARF_EH__");
247 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
250 template<typename Target>
251 class DarwinTargetInfo : public OSTargetInfo<Target> {
253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
254 MacroBuilder &Builder) const override {
255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
256 this->PlatformMinVersion);
260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
261 : OSTargetInfo<Target>(Triple, Opts) {
262 // By default, no TLS, and we whitelist permitted architecture/OS
264 this->TLSSupported = false;
266 if (Triple.isMacOSX())
267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
268 else if (Triple.isiOS()) {
269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
270 if (Triple.getArch() == llvm::Triple::x86_64 ||
271 Triple.getArch() == llvm::Triple::aarch64)
272 this->TLSSupported = !Triple.isOSVersionLT(8);
273 else if (Triple.getArch() == llvm::Triple::x86 ||
274 Triple.getArch() == llvm::Triple::arm ||
275 Triple.getArch() == llvm::Triple::thumb)
276 this->TLSSupported = !Triple.isOSVersionLT(9);
277 } else if (Triple.isWatchOS())
278 this->TLSSupported = !Triple.isOSVersionLT(2);
280 this->MCountName = "\01mcount";
283 std::string isValidSectionSpecifier(StringRef SR) const override {
284 // Let MCSectionMachO validate this.
285 StringRef Segment, Section;
286 unsigned TAA, StubSize;
288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
289 TAA, HasTAA, StubSize);
292 const char *getStaticInitSectionSpecifier() const override {
293 // FIXME: We should return 0 when building kexts.
294 return "__TEXT,__StaticInit,regular,pure_instructions";
297 /// Darwin does not support protected visibility. Darwin's "default"
298 /// is very similar to ELF's "protected"; Darwin requires a "weak"
299 /// attribute on declarations that can be dynamically replaced.
300 bool hasProtectedVisibility() const override {
304 unsigned getExnObjectAlignment() const override {
305 // The alignment of an exception object is 8-bytes for darwin since
306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned))
307 // and therefore doesn't guarantee 16-byte alignment.
313 // DragonFlyBSD Target
314 template<typename Target>
315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
318 MacroBuilder &Builder) const override {
319 // DragonFly defines; list based off of gcc output
320 Builder.defineMacro("__DragonFly__");
321 Builder.defineMacro("__DragonFly_cc_version", "100001");
322 Builder.defineMacro("__ELF__");
323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
324 Builder.defineMacro("__tune_i386__");
325 DefineStd(Builder, "unix", Opts);
328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
329 : OSTargetInfo<Target>(Triple, Opts) {
330 switch (Triple.getArch()) {
332 case llvm::Triple::x86:
333 case llvm::Triple::x86_64:
334 this->MCountName = ".mcount";
340 #ifndef FREEBSD_CC_VERSION
341 #define FREEBSD_CC_VERSION 0U
345 template<typename Target>
346 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
349 MacroBuilder &Builder) const override {
350 // FreeBSD defines; list based off of gcc output
352 unsigned Release = Triple.getOSMajorVersion();
355 unsigned CCVersion = FREEBSD_CC_VERSION;
357 CCVersion = Release * 100000U + 1U;
359 Builder.defineMacro("__FreeBSD__", Twine(Release));
360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
362 DefineStd(Builder, "unix", Opts);
363 Builder.defineMacro("__ELF__");
365 // On FreeBSD, wchar_t contains the number of the code point as
366 // used by the character set of the locale. These character sets are
367 // not necessarily a superset of ASCII.
369 // FIXME: This is wrong; the macro refers to the numerical values
370 // of wchar_t *literals*, which are not locale-dependent. However,
371 // FreeBSD systems apparently depend on us getting this wrong, and
372 // setting this to 1 is conforming even if all the basic source
373 // character literals have the same encoding as char and wchar_t.
374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
378 : OSTargetInfo<Target>(Triple, Opts) {
379 switch (Triple.getArch()) {
381 case llvm::Triple::x86:
382 case llvm::Triple::x86_64:
383 this->MCountName = ".mcount";
385 case llvm::Triple::mips:
386 case llvm::Triple::mipsel:
387 case llvm::Triple::ppc:
388 case llvm::Triple::ppc64:
389 case llvm::Triple::ppc64le:
390 this->MCountName = "_mcount";
392 case llvm::Triple::arm:
393 this->MCountName = "__mcount";
399 // GNU/kFreeBSD Target
400 template<typename Target>
401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
404 MacroBuilder &Builder) const override {
405 // GNU/kFreeBSD defines; list based off of gcc output
407 DefineStd(Builder, "unix", Opts);
408 Builder.defineMacro("__FreeBSD_kernel__");
409 Builder.defineMacro("__GLIBC__");
410 Builder.defineMacro("__ELF__");
411 if (Opts.POSIXThreads)
412 Builder.defineMacro("_REENTRANT");
414 Builder.defineMacro("_GNU_SOURCE");
417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
418 : OSTargetInfo<Target>(Triple, Opts) {}
422 template<typename Target>
423 class HaikuTargetInfo : public OSTargetInfo<Target> {
425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
426 MacroBuilder &Builder) const override {
427 // Haiku defines; list based off of gcc output
428 Builder.defineMacro("__HAIKU__");
429 Builder.defineMacro("__ELF__");
430 DefineStd(Builder, "unix", Opts);
433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
434 : OSTargetInfo<Target>(Triple, Opts) {
435 this->SizeType = TargetInfo::UnsignedLong;
436 this->IntPtrType = TargetInfo::SignedLong;
437 this->PtrDiffType = TargetInfo::SignedLong;
438 this->ProcessIDType = TargetInfo::SignedLong;
439 this->TLSSupported = false;
445 template<typename Target>
446 class MinixTargetInfo : public OSTargetInfo<Target> {
448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
449 MacroBuilder &Builder) const override {
452 Builder.defineMacro("__minix", "3");
453 Builder.defineMacro("_EM_WSIZE", "4");
454 Builder.defineMacro("_EM_PSIZE", "4");
455 Builder.defineMacro("_EM_SSIZE", "2");
456 Builder.defineMacro("_EM_LSIZE", "4");
457 Builder.defineMacro("_EM_FSIZE", "4");
458 Builder.defineMacro("_EM_DSIZE", "8");
459 Builder.defineMacro("__ELF__");
460 DefineStd(Builder, "unix", Opts);
463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
464 : OSTargetInfo<Target>(Triple, Opts) {}
468 template<typename Target>
469 class LinuxTargetInfo : public OSTargetInfo<Target> {
471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
472 MacroBuilder &Builder) const override {
473 // Linux defines; list based off of gcc output
474 DefineStd(Builder, "unix", Opts);
475 DefineStd(Builder, "linux", Opts);
476 Builder.defineMacro("__gnu_linux__");
477 Builder.defineMacro("__ELF__");
478 if (Triple.isAndroid()) {
479 Builder.defineMacro("__ANDROID__", "1");
480 unsigned Maj, Min, Rev;
481 Triple.getEnvironmentVersion(Maj, Min, Rev);
482 this->PlatformName = "android";
483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
485 Builder.defineMacro("__ANDROID_API__", Twine(Maj));
487 if (Opts.POSIXThreads)
488 Builder.defineMacro("_REENTRANT");
490 Builder.defineMacro("_GNU_SOURCE");
491 if (this->HasFloat128)
492 Builder.defineMacro("__FLOAT128__");
495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
496 : OSTargetInfo<Target>(Triple, Opts) {
497 this->WIntType = TargetInfo::UnsignedInt;
499 switch (Triple.getArch()) {
502 case llvm::Triple::ppc:
503 case llvm::Triple::ppc64:
504 case llvm::Triple::ppc64le:
505 this->MCountName = "_mcount";
507 case llvm::Triple::x86:
508 case llvm::Triple::x86_64:
509 case llvm::Triple::systemz:
510 this->HasFloat128 = true;
515 const char *getStaticInitSectionSpecifier() const override {
516 return ".text.startup";
521 template<typename Target>
522 class NetBSDTargetInfo : public OSTargetInfo<Target> {
524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525 MacroBuilder &Builder) const override {
526 // NetBSD defines; list based off of gcc output
527 Builder.defineMacro("__NetBSD__");
528 Builder.defineMacro("__unix__");
529 Builder.defineMacro("__ELF__");
530 if (Opts.POSIXThreads)
531 Builder.defineMacro("_REENTRANT");
533 switch (Triple.getArch()) {
536 case llvm::Triple::arm:
537 case llvm::Triple::armeb:
538 case llvm::Triple::thumb:
539 case llvm::Triple::thumbeb:
540 Builder.defineMacro("__ARM_DWARF_EH__");
545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
546 : OSTargetInfo<Target>(Triple, Opts) {
547 this->MCountName = "_mcount";
552 template<typename Target>
553 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
556 MacroBuilder &Builder) const override {
557 // OpenBSD defines; list based off of gcc output
559 Builder.defineMacro("__OpenBSD__");
560 DefineStd(Builder, "unix", Opts);
561 Builder.defineMacro("__ELF__");
562 if (Opts.POSIXThreads)
563 Builder.defineMacro("_REENTRANT");
564 if (this->HasFloat128)
565 Builder.defineMacro("__FLOAT128__");
568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
569 : OSTargetInfo<Target>(Triple, Opts) {
570 this->TLSSupported = false;
572 switch (Triple.getArch()) {
573 case llvm::Triple::x86:
574 case llvm::Triple::x86_64:
575 this->HasFloat128 = true;
578 this->MCountName = "__mcount";
580 case llvm::Triple::mips64:
581 case llvm::Triple::mips64el:
582 case llvm::Triple::ppc:
583 case llvm::Triple::sparcv9:
584 this->MCountName = "_mcount";
591 template<typename Target>
592 class BitrigTargetInfo : public OSTargetInfo<Target> {
594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
595 MacroBuilder &Builder) const override {
596 // Bitrig defines; list based off of gcc output
598 Builder.defineMacro("__Bitrig__");
599 DefineStd(Builder, "unix", Opts);
600 Builder.defineMacro("__ELF__");
601 if (Opts.POSIXThreads)
602 Builder.defineMacro("_REENTRANT");
604 switch (Triple.getArch()) {
607 case llvm::Triple::arm:
608 case llvm::Triple::armeb:
609 case llvm::Triple::thumb:
610 case llvm::Triple::thumbeb:
611 Builder.defineMacro("__ARM_DWARF_EH__");
616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
617 : OSTargetInfo<Target>(Triple, Opts) {
618 this->MCountName = "__mcount";
623 template<typename Target>
624 class PSPTargetInfo : public OSTargetInfo<Target> {
626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
627 MacroBuilder &Builder) const override {
628 // PSP defines; list based on the output of the pspdev gcc toolchain.
629 Builder.defineMacro("PSP");
630 Builder.defineMacro("_PSP");
631 Builder.defineMacro("__psp__");
632 Builder.defineMacro("__ELF__");
635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {}
639 template<typename Target>
640 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
643 MacroBuilder &Builder) const override {
645 Builder.defineMacro("__PPC__");
646 Builder.defineMacro("__PPU__");
647 Builder.defineMacro("__CELLOS_LV2__");
648 Builder.defineMacro("__ELF__");
649 Builder.defineMacro("__LP32__");
650 Builder.defineMacro("_ARCH_PPC64");
651 Builder.defineMacro("__powerpc64__");
654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
655 : OSTargetInfo<Target>(Triple, Opts) {
656 this->LongWidth = this->LongAlign = 32;
657 this->PointerWidth = this->PointerAlign = 32;
658 this->IntMaxType = TargetInfo::SignedLongLong;
659 this->Int64Type = TargetInfo::SignedLongLong;
660 this->SizeType = TargetInfo::UnsignedInt;
661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64");
665 template <typename Target>
666 class PS4OSTargetInfo : public OSTargetInfo<Target> {
668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
669 MacroBuilder &Builder) const override {
670 Builder.defineMacro("__FreeBSD__", "9");
671 Builder.defineMacro("__FreeBSD_cc_version", "900001");
672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
673 DefineStd(Builder, "unix", Opts);
674 Builder.defineMacro("__ELF__");
675 Builder.defineMacro("__ORBIS__");
678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
679 : OSTargetInfo<Target>(Triple, Opts) {
680 this->WCharType = this->UnsignedShort;
682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
683 this->MaxTLSAlign = 256;
685 // On PS4, do not honor explicit bit field alignment,
686 // as in "__attribute__((aligned(2))) int b : 1;".
687 this->UseExplicitBitFieldAlignment = false;
689 switch (Triple.getArch()) {
691 case llvm::Triple::x86_64:
692 this->MCountName = ".mcount";
699 template<typename Target>
700 class SolarisTargetInfo : public OSTargetInfo<Target> {
702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
703 MacroBuilder &Builder) const override {
704 DefineStd(Builder, "sun", Opts);
705 DefineStd(Builder, "unix", Opts);
706 Builder.defineMacro("__ELF__");
707 Builder.defineMacro("__svr4__");
708 Builder.defineMacro("__SVR4");
709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
710 // newer, but to 500 for everything else. feature_test.h has a check to
711 // ensure that you are not using C99 with an old version of X/Open or C89
712 // with a new version.
714 Builder.defineMacro("_XOPEN_SOURCE", "600");
716 Builder.defineMacro("_XOPEN_SOURCE", "500");
718 Builder.defineMacro("__C99FEATURES__");
719 Builder.defineMacro("_LARGEFILE_SOURCE");
720 Builder.defineMacro("_LARGEFILE64_SOURCE");
721 Builder.defineMacro("__EXTENSIONS__");
722 Builder.defineMacro("_REENTRANT");
725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
726 : OSTargetInfo<Target>(Triple, Opts) {
727 this->WCharType = this->SignedInt;
728 // FIXME: WIntType should be SignedLong
733 template<typename Target>
734 class WindowsTargetInfo : public OSTargetInfo<Target> {
736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
737 MacroBuilder &Builder) const override {
738 Builder.defineMacro("_WIN32");
740 void getVisualStudioDefines(const LangOptions &Opts,
741 MacroBuilder &Builder) const {
742 if (Opts.CPlusPlus) {
744 Builder.defineMacro("_CPPRTTI");
746 if (Opts.CXXExceptions)
747 Builder.defineMacro("_CPPUNWIND");
751 Builder.defineMacro("__BOOL_DEFINED");
753 if (!Opts.CharIsSigned)
754 Builder.defineMacro("_CHAR_UNSIGNED");
756 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
757 // but it works for now.
758 if (Opts.POSIXThreads)
759 Builder.defineMacro("_MT");
761 if (Opts.MSCompatibilityVersion) {
762 Builder.defineMacro("_MSC_VER",
763 Twine(Opts.MSCompatibilityVersion / 100000));
764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
765 // FIXME We cannot encode the revision information into 32-bits
766 Builder.defineMacro("_MSC_BUILD", Twine(1));
768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
772 if (Opts.CPlusPlus1z)
773 Builder.defineMacro("_MSVC_LANG", "201403L");
774 else if (Opts.CPlusPlus14)
775 Builder.defineMacro("_MSVC_LANG", "201402L");
779 if (Opts.MicrosoftExt) {
780 Builder.defineMacro("_MSC_EXTENSIONS");
782 if (Opts.CPlusPlus11) {
783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
794 : OSTargetInfo<Target>(Triple, Opts) {}
797 template <typename Target>
798 class NaClTargetInfo : public OSTargetInfo<Target> {
800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
801 MacroBuilder &Builder) const override {
802 if (Opts.POSIXThreads)
803 Builder.defineMacro("_REENTRANT");
805 Builder.defineMacro("_GNU_SOURCE");
807 DefineStd(Builder, "unix", Opts);
808 Builder.defineMacro("__ELF__");
809 Builder.defineMacro("__native_client__");
813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
814 : OSTargetInfo<Target>(Triple, Opts) {
815 this->LongAlign = 32;
816 this->LongWidth = 32;
817 this->PointerAlign = 32;
818 this->PointerWidth = 32;
819 this->IntMaxType = TargetInfo::SignedLongLong;
820 this->Int64Type = TargetInfo::SignedLongLong;
821 this->DoubleAlign = 64;
822 this->LongDoubleWidth = 64;
823 this->LongDoubleAlign = 64;
824 this->LongLongWidth = 64;
825 this->LongLongAlign = 64;
826 this->SizeType = TargetInfo::UnsignedInt;
827 this->PtrDiffType = TargetInfo::SignedInt;
828 this->IntPtrType = TargetInfo::SignedInt;
829 // RegParmMax is inherited from the underlying architecture.
830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
831 if (Triple.getArch() == llvm::Triple::arm) {
832 // Handled in ARM's setABI().
833 } else if (Triple.getArch() == llvm::Triple::x86) {
834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128");
835 } else if (Triple.getArch() == llvm::Triple::x86_64) {
836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128");
837 } else if (Triple.getArch() == llvm::Triple::mipsel) {
838 // Handled on mips' setDataLayout.
840 assert(Triple.getArch() == llvm::Triple::le32);
841 this->resetDataLayout("e-p:32:32-i64:64");
847 template<typename Target>
848 class FuchsiaTargetInfo : public OSTargetInfo<Target> {
850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
851 MacroBuilder &Builder) const override {
852 Builder.defineMacro("__Fuchsia__");
853 Builder.defineMacro("__ELF__");
854 if (Opts.POSIXThreads)
855 Builder.defineMacro("_REENTRANT");
856 // Required by the libc++ locale support.
858 Builder.defineMacro("_GNU_SOURCE");
861 FuchsiaTargetInfo(const llvm::Triple &Triple,
862 const TargetOptions &Opts)
863 : OSTargetInfo<Target>(Triple, Opts) {
864 this->MCountName = "__mcount";
868 // WebAssembly target
869 template <typename Target>
870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
872 MacroBuilder &Builder) const final {
873 // A common platform macro.
874 if (Opts.POSIXThreads)
875 Builder.defineMacro("_REENTRANT");
876 // Follow g++ convention and predefine _GNU_SOURCE for C++.
878 Builder.defineMacro("_GNU_SOURCE");
881 // As an optimization, group static init code together in a section.
882 const char *getStaticInitSectionSpecifier() const final {
883 return ".text.__startup";
887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple,
888 const TargetOptions &Opts)
889 : OSTargetInfo<Target>(Triple, Opts) {
890 this->MCountName = "__mcount";
891 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
895 //===----------------------------------------------------------------------===//
896 // Specific target implementations.
897 //===----------------------------------------------------------------------===//
899 // PPC abstract base class
900 class PPCTargetInfo : public TargetInfo {
901 static const Builtin::Info BuiltinInfo[];
902 static const char * const GCCRegNames[];
903 static const TargetInfo::GCCRegAlias GCCRegAliases[];
906 // Target cpu features.
922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false),
924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
927 SimdDefaultAlign = 128;
928 LongDoubleWidth = LongDoubleAlign = 128;
929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
932 /// \brief Flags for architecture specific defines.
935 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
936 ArchDefinePpcgr = 1 << 1,
937 ArchDefinePpcsq = 1 << 2,
938 ArchDefine440 = 1 << 3,
939 ArchDefine603 = 1 << 4,
940 ArchDefine604 = 1 << 5,
941 ArchDefinePwr4 = 1 << 6,
942 ArchDefinePwr5 = 1 << 7,
943 ArchDefinePwr5x = 1 << 8,
944 ArchDefinePwr6 = 1 << 9,
945 ArchDefinePwr6x = 1 << 10,
946 ArchDefinePwr7 = 1 << 11,
947 ArchDefinePwr8 = 1 << 12,
948 ArchDefinePwr9 = 1 << 13,
949 ArchDefineA2 = 1 << 14,
950 ArchDefineA2q = 1 << 15
953 // Set the language option for altivec based on our value.
954 void adjust(LangOptions &Opts) override {
957 TargetInfo::adjust(Opts);
960 // Note: GCC recognizes the following additional cpus:
961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
964 bool setCPU(const std::string &Name) override {
965 bool CPUKnown = llvm::StringSwitch<bool>(Name)
966 .Case("generic", true)
988 .Case("e500mc", true)
990 .Case("power3", true)
992 .Case("power4", true)
994 .Case("power5", true)
996 .Case("power5x", true)
998 .Case("power6", true)
1000 .Case("power6x", true)
1001 .Case("pwr6x", true)
1002 .Case("power7", true)
1004 .Case("power8", true)
1006 .Case("power9", true)
1008 .Case("powerpc", true)
1010 .Case("powerpc64", true)
1011 .Case("ppc64", true)
1012 .Case("powerpc64le", true)
1013 .Case("ppc64le", true)
1023 StringRef getABI() const override { return ABI; }
1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1026 return llvm::makeArrayRef(BuiltinInfo,
1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
1030 bool isCLZForZeroUndef() const override { return false; }
1032 void getTargetDefines(const LangOptions &Opts,
1033 MacroBuilder &Builder) const override;
1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1038 const std::vector<std::string> &FeaturesVec) const override;
1040 bool handleTargetFeatures(std::vector<std::string> &Features,
1041 DiagnosticsEngine &Diags) override;
1042 bool hasFeature(StringRef Feature) const override;
1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
1044 bool Enabled) const override;
1046 ArrayRef<const char *> getGCCRegNames() const override;
1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
1048 bool validateAsmConstraint(const char *&Name,
1049 TargetInfo::ConstraintInfo &Info) const override {
1051 default: return false;
1054 case 'b': // Base register
1055 case 'f': // Floating point register
1056 Info.setAllowsRegister();
1058 // FIXME: The following are added to allow parsing.
1059 // I just took a guess at what the actions should be.
1060 // Also, is more specific checking needed? I.e. specific registers?
1061 case 'd': // Floating point register (containing 64-bit value)
1062 case 'v': // Altivec vector register
1063 Info.setAllowsRegister();
1067 case 'd':// VSX vector register to hold vector double data
1068 case 'f':// VSX vector register to hold vector float data
1069 case 's':// VSX vector register to hold scalar float data
1070 case 'a':// Any VSX register
1071 case 'c':// An individual CR bit
1076 Info.setAllowsRegister();
1077 Name++; // Skip over 'w'.
1079 case 'h': // `MQ', `CTR', or `LINK' register
1080 case 'q': // `MQ' register
1081 case 'c': // `CTR' register
1082 case 'l': // `LINK' register
1083 case 'x': // `CR' register (condition register) number 0
1084 case 'y': // `CR' register (condition register)
1085 case 'z': // `XER[CA]' carry bit (part of the XER register)
1086 Info.setAllowsRegister();
1088 case 'I': // Signed 16-bit constant
1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits
1090 // (use `L' instead for SImode constants)
1091 case 'K': // Unsigned 16-bit constant
1092 case 'L': // Signed 16-bit constant shifted left 16 bits
1093 case 'M': // Constant larger than 31
1094 case 'N': // Exact power of 2
1095 case 'P': // Constant whose negation is a signed 16-bit constant
1096 case 'G': // Floating point constant that can be loaded into a
1097 // register with one instruction per word
1098 case 'H': // Integer/Floating point constant that can be loaded
1099 // into a register using three instructions
1101 case 'm': // Memory operand. Note that on PowerPC targets, m can
1102 // include addresses that update the base register. It
1103 // is therefore only safe to use `m' in an asm statement
1104 // if that asm statement accesses the operand exactly once.
1105 // The asm statement must also use `%U<opno>' as a
1106 // placeholder for the "update" flag in the corresponding
1107 // load or store instruction. For example:
1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
1111 // is not. Use es rather than m if you don't want the base
1112 // register to be updated.
1116 // es: A "stable" memory operand; that is, one which does not
1117 // include any automodification of the base register. Unlike
1118 // `m', this constraint can be used in asm statements that
1119 // might access the operand several times, or that might not
1120 // access it at all.
1121 Info.setAllowsMemory();
1122 Name++; // Skip over 'e'.
1124 case 'Q': // Memory operand that is an offset from a register (it is
1125 // usually better to use `m' or `es' in asm statements)
1126 case 'Z': // Memory operand that is an indexed or indirect from a
1127 // register (it is usually better to use `m' or `es' in
1129 Info.setAllowsMemory();
1130 Info.setAllowsRegister();
1132 case 'R': // AIX TOC entry
1133 case 'a': // Address operand that is an indexed or indirect from a
1134 // register (`p' is preferable for asm statements)
1135 case 'S': // Constant suitable as a 64-bit mask operand
1136 case 'T': // Constant suitable as a 32-bit mask operand
1137 case 'U': // System V Release 4 small data area reference
1138 case 't': // AND masks that can be performed by two rldic{l, r}
1140 case 'W': // Vector constant that does not require memory
1141 case 'j': // Vector constant that is all zeros.
1147 std::string convertConstraint(const char *&Constraint) const override {
1149 switch (*Constraint) {
1152 // Two-character constraint; add "^" hint for later parsing.
1153 R = std::string("^") + std::string(Constraint, 2);
1157 return TargetInfo::convertConstraint(Constraint);
1161 const char *getClobbers() const override {
1164 int getEHDataRegisterNumber(unsigned RegNo) const override {
1165 if (RegNo == 0) return 3;
1166 if (RegNo == 1) return 4;
1170 bool hasSjLjLowering() const override {
1174 bool useFloat128ManglingForLongDouble() const override {
1175 return LongDoubleWidth == 128 &&
1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
1177 getTriple().isOSBinFormatELF();
1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1182 #define BUILTIN(ID, TYPE, ATTRS) \
1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1186 #include "clang/Basic/BuiltinsPPC.def"
1189 /// handleTargetFeatures - Perform initialization based on the user
1190 /// configured set of features.
1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1192 DiagnosticsEngine &Diags) {
1193 for (const auto &Feature : Features) {
1194 if (Feature == "+altivec") {
1196 } else if (Feature == "+vsx") {
1198 } else if (Feature == "+bpermd") {
1200 } else if (Feature == "+extdiv") {
1202 } else if (Feature == "+power8-vector") {
1204 } else if (Feature == "+crypto") {
1206 } else if (Feature == "+direct-move") {
1207 HasDirectMove = true;
1208 } else if (Feature == "+qpx") {
1210 } else if (Feature == "+htm") {
1212 } else if (Feature == "+float128") {
1214 } else if (Feature == "+power9-vector") {
1217 // TODO: Finish this list and add an assert that we've handled them
1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1225 /// #defines that are not tied to a specific subtarget.
1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1227 MacroBuilder &Builder) const {
1228 // Target identification.
1229 Builder.defineMacro("__ppc__");
1230 Builder.defineMacro("__PPC__");
1231 Builder.defineMacro("_ARCH_PPC");
1232 Builder.defineMacro("__powerpc__");
1233 Builder.defineMacro("__POWERPC__");
1234 if (PointerWidth == 64) {
1235 Builder.defineMacro("_ARCH_PPC64");
1236 Builder.defineMacro("__powerpc64__");
1237 Builder.defineMacro("__ppc64__");
1238 Builder.defineMacro("__PPC64__");
1241 // Target properties.
1242 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1243 Builder.defineMacro("_LITTLE_ENDIAN");
1245 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1246 getTriple().getOS() != llvm::Triple::OpenBSD)
1247 Builder.defineMacro("_BIG_ENDIAN");
1251 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1252 Builder.defineMacro("_CALL_ELF", "1");
1254 Builder.defineMacro("_CALL_ELF", "2");
1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
1257 // our suppport post-dates this and it should work on all 64-bit ppc linux
1258 // platforms. It is guaranteed to work on all elfv2 platforms.
1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
1260 Builder.defineMacro("_CALL_LINUX", "1");
1262 // Subtarget options.
1263 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1264 Builder.defineMacro("__REGISTER_PREFIX__", "");
1266 // FIXME: Should be controlled by command line option.
1267 if (LongDoubleWidth == 128) {
1268 Builder.defineMacro("__LONG_DOUBLE_128__");
1269 Builder.defineMacro("__LONGDOUBLE128");
1272 // Define this for elfv2 (64-bit only) or 64-bit darwin.
1273 if (ABI == "elfv2" ||
1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
1277 // CPU identification.
1278 ArchDefineTypes defs =
1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1280 .Case("440", ArchDefineName)
1281 .Case("450", ArchDefineName | ArchDefine440)
1282 .Case("601", ArchDefineName)
1283 .Case("602", ArchDefineName | ArchDefinePpcgr)
1284 .Case("603", ArchDefineName | ArchDefinePpcgr)
1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1287 .Case("604", ArchDefineName | ArchDefinePpcgr)
1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1289 .Case("620", ArchDefineName | ArchDefinePpcgr)
1290 .Case("630", ArchDefineName | ArchDefinePpcgr)
1291 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1292 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1293 .Case("750", ArchDefineName | ArchDefinePpcgr)
1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1296 .Case("a2", ArchDefineA2)
1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1298 .Case("pwr3", ArchDefinePpcgr)
1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 |
1303 ArchDefinePpcgr | ArchDefinePpcsq)
1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 |
1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x |
1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 |
1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1311 ArchDefinePpcgr | ArchDefinePpcsq)
1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x |
1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 |
1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1319 .Case("power3", ArchDefinePpcgr)
1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
1324 ArchDefinePpcgr | ArchDefinePpcsq)
1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
1326 ArchDefinePwr4 | ArchDefinePpcgr |
1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
1329 ArchDefinePwr5 | ArchDefinePwr4 |
1330 ArchDefinePpcgr | ArchDefinePpcsq)
1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
1332 ArchDefinePwr5x | ArchDefinePwr5 |
1333 ArchDefinePwr4 | ArchDefinePpcgr |
1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1336 ArchDefinePwr6 | ArchDefinePwr5x |
1337 ArchDefinePwr5 | ArchDefinePwr4 |
1338 ArchDefinePpcgr | ArchDefinePpcsq)
1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
1340 ArchDefinePwr6x | ArchDefinePwr6 |
1341 ArchDefinePwr5x | ArchDefinePwr5 |
1342 ArchDefinePwr4 | ArchDefinePpcgr |
1344 // powerpc64le automatically defaults to at least power8.
1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
1346 ArchDefinePwr6 | ArchDefinePwr5x |
1347 ArchDefinePwr5 | ArchDefinePwr4 |
1348 ArchDefinePpcgr | ArchDefinePpcsq)
1349 .Default(ArchDefineNone);
1351 if (defs & ArchDefineName)
1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1353 if (defs & ArchDefinePpcgr)
1354 Builder.defineMacro("_ARCH_PPCGR");
1355 if (defs & ArchDefinePpcsq)
1356 Builder.defineMacro("_ARCH_PPCSQ");
1357 if (defs & ArchDefine440)
1358 Builder.defineMacro("_ARCH_440");
1359 if (defs & ArchDefine603)
1360 Builder.defineMacro("_ARCH_603");
1361 if (defs & ArchDefine604)
1362 Builder.defineMacro("_ARCH_604");
1363 if (defs & ArchDefinePwr4)
1364 Builder.defineMacro("_ARCH_PWR4");
1365 if (defs & ArchDefinePwr5)
1366 Builder.defineMacro("_ARCH_PWR5");
1367 if (defs & ArchDefinePwr5x)
1368 Builder.defineMacro("_ARCH_PWR5X");
1369 if (defs & ArchDefinePwr6)
1370 Builder.defineMacro("_ARCH_PWR6");
1371 if (defs & ArchDefinePwr6x)
1372 Builder.defineMacro("_ARCH_PWR6X");
1373 if (defs & ArchDefinePwr7)
1374 Builder.defineMacro("_ARCH_PWR7");
1375 if (defs & ArchDefinePwr8)
1376 Builder.defineMacro("_ARCH_PWR8");
1377 if (defs & ArchDefinePwr9)
1378 Builder.defineMacro("_ARCH_PWR9");
1379 if (defs & ArchDefineA2)
1380 Builder.defineMacro("_ARCH_A2");
1381 if (defs & ArchDefineA2q) {
1382 Builder.defineMacro("_ARCH_A2Q");
1383 Builder.defineMacro("_ARCH_QP");
1386 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1387 Builder.defineMacro("__bg__");
1388 Builder.defineMacro("__THW_BLUEGENE__");
1389 Builder.defineMacro("__bgq__");
1390 Builder.defineMacro("__TOS_BGQ__");
1394 Builder.defineMacro("__VEC__", "10206");
1395 Builder.defineMacro("__ALTIVEC__");
1398 Builder.defineMacro("__VSX__");
1400 Builder.defineMacro("__POWER8_VECTOR__");
1402 Builder.defineMacro("__CRYPTO__");
1404 Builder.defineMacro("__HTM__");
1406 Builder.defineMacro("__FLOAT128__");
1408 Builder.defineMacro("__POWER9_VECTOR__");
1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1413 if (PointerWidth == 64)
1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1416 // We have support for the bswap intrinsics so we can define this.
1417 Builder.defineMacro("__HAVE_BSWAP__", "1");
1419 // FIXME: The following are not yet generated here by Clang, but are
1420 // generated by GCC:
1423 // __RECIP_PRECISION__
1424 // __APPLE_ALTIVEC__
1431 // __CMODEL_MEDIUM__
1438 // Handle explicit options being passed to the compiler here: if we've
1439 // explicitly turned off vsx and turned on any of:
1444 // then go ahead and error since the customer has expressed an incompatible
1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1447 const std::vector<std::string> &FeaturesVec) {
1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1450 FeaturesVec.end()) {
1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1452 FeaturesVec.end()) {
1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1459 FeaturesVec.end()) {
1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
1466 FeaturesVec.end()) {
1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
1473 FeaturesVec.end()) {
1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
1483 bool PPCTargetInfo::initFeatureMap(
1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1485 const std::vector<std::string> &FeaturesVec) const {
1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1497 .Case("ppc64", true)
1498 .Case("ppc64le", true)
1501 Features["qpx"] = (CPU == "a2q");
1502 Features["power9-vector"] = (CPU == "pwr9");
1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1504 .Case("ppc64le", true)
1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1509 .Case("ppc64le", true)
1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1514 .Case("ppc64le", true)
1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1520 .Case("ppc64le", true)
1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1526 .Case("ppc64le", true)
1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1531 .Case("ppc64le", true)
1536 Features["htm"] = llvm::StringSwitch<bool>(CPU)
1537 .Case("ppc64le", true)
1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1549 return llvm::StringSwitch<bool>(Feature)
1550 .Case("powerpc", true)
1551 .Case("altivec", HasAltivec)
1552 .Case("vsx", HasVSX)
1553 .Case("power8-vector", HasP8Vector)
1554 .Case("crypto", HasP8Crypto)
1555 .Case("direct-move", HasDirectMove)
1556 .Case("qpx", HasQPX)
1557 .Case("htm", HasHTM)
1558 .Case("bpermd", HasBPERMD)
1559 .Case("extdiv", HasExtDiv)
1560 .Case("float128", HasFloat128)
1561 .Case("power9-vector", HasP9Vector)
1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1566 StringRef Name, bool Enabled) const {
1568 // If we're enabling any of the vsx based features then enable vsx and
1569 // altivec. We'll diagnose any problems later.
1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
1572 .Case("direct-move", true)
1573 .Case("power8-vector", true)
1574 .Case("power9-vector", true)
1575 .Case("float128", true)
1578 Features["vsx"] = Features["altivec"] = true;
1579 if (Name == "power9-vector")
1580 Features["power8-vector"] = true;
1581 Features[Name] = true;
1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx
1585 if ((Name == "altivec") || (Name == "vsx"))
1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
1587 Features["float128"] = Features["power9-vector"] = false;
1588 if (Name == "power8-vector")
1589 Features["power9-vector"] = false;
1590 Features[Name] = false;
1594 const char * const PPCTargetInfo::GCCRegNames[] = {
1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1603 "mq", "lr", "ctr", "ap",
1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1611 "spe_acc", "spefscr",
1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1616 return llvm::makeArrayRef(GCCRegNames);
1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1620 // While some of these aliases do map to different registers
1621 // they still share the same register name.
1632 { { "10" }, "r10" },
1633 { { "11" }, "r11" },
1634 { { "12" }, "r12" },
1635 { { "13" }, "r13" },
1636 { { "14" }, "r14" },
1637 { { "15" }, "r15" },
1638 { { "16" }, "r16" },
1639 { { "17" }, "r17" },
1640 { { "18" }, "r18" },
1641 { { "19" }, "r19" },
1642 { { "20" }, "r20" },
1643 { { "21" }, "r21" },
1644 { { "22" }, "r22" },
1645 { { "23" }, "r23" },
1646 { { "24" }, "r24" },
1647 { { "25" }, "r25" },
1648 { { "26" }, "r26" },
1649 { { "27" }, "r27" },
1650 { { "28" }, "r28" },
1651 { { "29" }, "r29" },
1652 { { "30" }, "r30" },
1653 { { "31" }, "r31" },
1654 { { "fr0" }, "f0" },
1655 { { "fr1" }, "f1" },
1656 { { "fr2" }, "f2" },
1657 { { "fr3" }, "f3" },
1658 { { "fr4" }, "f4" },
1659 { { "fr5" }, "f5" },
1660 { { "fr6" }, "f6" },
1661 { { "fr7" }, "f7" },
1662 { { "fr8" }, "f8" },
1663 { { "fr9" }, "f9" },
1664 { { "fr10" }, "f10" },
1665 { { "fr11" }, "f11" },
1666 { { "fr12" }, "f12" },
1667 { { "fr13" }, "f13" },
1668 { { "fr14" }, "f14" },
1669 { { "fr15" }, "f15" },
1670 { { "fr16" }, "f16" },
1671 { { "fr17" }, "f17" },
1672 { { "fr18" }, "f18" },
1673 { { "fr19" }, "f19" },
1674 { { "fr20" }, "f20" },
1675 { { "fr21" }, "f21" },
1676 { { "fr22" }, "f22" },
1677 { { "fr23" }, "f23" },
1678 { { "fr24" }, "f24" },
1679 { { "fr25" }, "f25" },
1680 { { "fr26" }, "f26" },
1681 { { "fr27" }, "f27" },
1682 { { "fr28" }, "f28" },
1683 { { "fr29" }, "f29" },
1684 { { "fr30" }, "f30" },
1685 { { "fr31" }, "f31" },
1686 { { "cc" }, "cr0" },
1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1690 return llvm::makeArrayRef(GCCRegAliases);
1693 class PPC32TargetInfo : public PPCTargetInfo {
1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1696 : PPCTargetInfo(Triple, Opts) {
1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
1699 switch (getTriple().getOS()) {
1700 case llvm::Triple::Linux:
1701 case llvm::Triple::FreeBSD:
1702 case llvm::Triple::NetBSD:
1703 SizeType = UnsignedInt;
1704 PtrDiffType = SignedInt;
1705 IntPtrType = SignedInt;
1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1712 LongDoubleWidth = LongDoubleAlign = 64;
1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1716 // PPC32 supports atomics up to 4 bytes.
1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1720 BuiltinVaListKind getBuiltinVaListKind() const override {
1721 // This is the ELF definition, and is overridden by the Darwin sub-target
1722 return TargetInfo::PowerABIBuiltinVaList;
1726 // Note: ABI differences may eventually require us to have a separate
1727 // TargetInfo for little endian.
1728 class PPC64TargetInfo : public PPCTargetInfo {
1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1731 : PPCTargetInfo(Triple, Opts) {
1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1733 IntMaxType = SignedLong;
1734 Int64Type = SignedLong;
1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1737 resetDataLayout("e-m:e-i64:64-n32:64");
1740 resetDataLayout("E-m:e-i64:64-n32:64");
1744 switch (getTriple().getOS()) {
1745 case llvm::Triple::FreeBSD:
1746 LongDoubleWidth = LongDoubleAlign = 64;
1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1749 case llvm::Triple::NetBSD:
1750 IntMaxType = SignedLongLong;
1751 Int64Type = SignedLongLong;
1757 // PPC64 supports atomics up to 8 bytes.
1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1760 BuiltinVaListKind getBuiltinVaListKind() const override {
1761 return TargetInfo::CharPtrBuiltinVaList;
1763 // PPC64 Linux-specific ABI options.
1764 bool setABI(const std::string &Name) override {
1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> {
1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
1777 HasAlignMac68kSupport = true;
1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
1783 BuiltinVaListKind getBuiltinVaListKind() const override {
1784 return TargetInfo::CharPtrBuiltinVaList;
1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> {
1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
1792 HasAlignMac68kSupport = true;
1793 resetDataLayout("E-m:o-i64:64-n32:64");
1797 static const unsigned NVPTXAddrSpaceMap[] = {
1801 4, // opencl_constant
1802 // FIXME: generic has to be added to the target
1803 0, // opencl_generic
1809 class NVPTXTargetInfo : public TargetInfo {
1810 static const char *const GCCRegNames[];
1811 static const Builtin::Info BuiltinInfo[];
1813 std::unique_ptr<TargetInfo> HostTarget;
1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
1817 unsigned TargetPointerWidth)
1818 : TargetInfo(Triple) {
1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
1820 "NVPTX only supports 32- and 64-bit modes.");
1822 TLSSupported = false;
1823 AddrSpaceMap = &NVPTXAddrSpaceMap;
1824 UseAddrSpaceMapMangling = true;
1826 // Define available target features
1827 // These must be defined in sorted order!
1828 NoAsmVariants = true;
1829 GPU = CudaArch::SM_20;
1831 if (TargetPointerWidth == 32)
1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64");
1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64");
1836 // If possible, get a TargetInfo for our host triple, so we can match its
1838 llvm::Triple HostTriple(Opts.HostTriple);
1839 if (!HostTriple.isNVPTX())
1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
1842 // If no host target, make some guesses about the data layout and return.
1844 LongWidth = LongAlign = TargetPointerWidth;
1845 PointerWidth = PointerAlign = TargetPointerWidth;
1846 switch (TargetPointerWidth) {
1848 SizeType = TargetInfo::UnsignedInt;
1849 PtrDiffType = TargetInfo::SignedInt;
1850 IntPtrType = TargetInfo::SignedInt;
1853 SizeType = TargetInfo::UnsignedLong;
1854 PtrDiffType = TargetInfo::SignedLong;
1855 IntPtrType = TargetInfo::SignedLong;
1858 llvm_unreachable("TargetPointerWidth must be 32 or 64");
1863 // Copy properties from host target.
1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
1866 BoolWidth = HostTarget->getBoolWidth();
1867 BoolAlign = HostTarget->getBoolAlign();
1868 IntWidth = HostTarget->getIntWidth();
1869 IntAlign = HostTarget->getIntAlign();
1870 HalfWidth = HostTarget->getHalfWidth();
1871 HalfAlign = HostTarget->getHalfAlign();
1872 FloatWidth = HostTarget->getFloatWidth();
1873 FloatAlign = HostTarget->getFloatAlign();
1874 DoubleWidth = HostTarget->getDoubleWidth();
1875 DoubleAlign = HostTarget->getDoubleAlign();
1876 LongWidth = HostTarget->getLongWidth();
1877 LongAlign = HostTarget->getLongAlign();
1878 LongLongWidth = HostTarget->getLongLongWidth();
1879 LongLongAlign = HostTarget->getLongLongAlign();
1880 MinGlobalAlign = HostTarget->getMinGlobalAlign();
1881 NewAlign = HostTarget->getNewAlign();
1882 DefaultAlignForAttributeAligned =
1883 HostTarget->getDefaultAlignForAttributeAligned();
1884 SizeType = HostTarget->getSizeType();
1885 IntMaxType = HostTarget->getIntMaxType();
1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
1887 IntPtrType = HostTarget->getIntPtrType();
1888 WCharType = HostTarget->getWCharType();
1889 WIntType = HostTarget->getWIntType();
1890 Char16Type = HostTarget->getChar16Type();
1891 Char32Type = HostTarget->getChar32Type();
1892 Int64Type = HostTarget->getInt64Type();
1893 SigAtomicType = HostTarget->getSigAtomicType();
1894 ProcessIDType = HostTarget->getProcessIDType();
1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
1897 UseZeroLengthBitfieldAlignment =
1898 HostTarget->useZeroLengthBitfieldAlignment();
1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
1903 // we need those macros to be identical on host and device, because (among
1904 // other things) they affect which standard library classes are defined, and
1905 // we need all classes to be defined on both the host and device.
1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
1908 // Properties intentionally not copied from host:
1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
1910 // host/device boundary.
1911 // - SuitableAlign: Not visible across the host/device boundary, and may
1912 // correctly be different on host/device, e.g. if host has wider vector
1913 // types than device.
1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
1915 // as its double type, but that's not necessarily true on the host.
1916 // TODO: nvcc emits a warning when using long double on device; we should
1919 void getTargetDefines(const LangOptions &Opts,
1920 MacroBuilder &Builder) const override {
1921 Builder.defineMacro("__PTX__");
1922 Builder.defineMacro("__NVPTX__");
1923 if (Opts.CUDAIsDevice) {
1924 // Set __CUDA_ARCH__ for the GPU specified.
1925 std::string CUDAArchCode = [this] {
1927 case CudaArch::UNKNOWN:
1928 assert(false && "No GPU arch when compiling CUDA device code.");
1930 case CudaArch::SM_20:
1932 case CudaArch::SM_21:
1934 case CudaArch::SM_30:
1936 case CudaArch::SM_32:
1938 case CudaArch::SM_35:
1940 case CudaArch::SM_37:
1942 case CudaArch::SM_50:
1944 case CudaArch::SM_52:
1946 case CudaArch::SM_53:
1948 case CudaArch::SM_60:
1950 case CudaArch::SM_61:
1952 case CudaArch::SM_62:
1955 llvm_unreachable("unhandled CudaArch");
1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1961 return llvm::makeArrayRef(BuiltinInfo,
1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
1967 const std::vector<std::string> &FeaturesVec) const override {
1968 Features["satom"] = GPU >= CudaArch::SM_60;
1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1972 bool hasFeature(StringRef Feature) const override {
1973 return llvm::StringSwitch<bool>(Feature)
1974 .Cases("ptx", "nvptx", true)
1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope.
1979 ArrayRef<const char *> getGCCRegNames() const override;
1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1984 bool validateAsmConstraint(const char *&Name,
1985 TargetInfo::ConstraintInfo &Info) const override {
1995 Info.setAllowsRegister();
1999 const char *getClobbers() const override {
2000 // FIXME: Is this really right?
2003 BuiltinVaListKind getBuiltinVaListKind() const override {
2005 return TargetInfo::CharPtrBuiltinVaList;
2007 bool setCPU(const std::string &Name) override {
2008 GPU = StringToCudaArch(Name);
2009 return GPU != CudaArch::UNKNOWN;
2011 void setSupportedOpenCLOpts() override {
2012 auto &Opts = getSupportedOpenCLOpts();
2013 Opts.support("cl_clang_storage_class_specifiers");
2014 Opts.support("cl_khr_gl_sharing");
2015 Opts.support("cl_khr_icd");
2017 Opts.support("cl_khr_fp64");
2018 Opts.support("cl_khr_byte_addressable_store");
2019 Opts.support("cl_khr_global_int32_base_atomics");
2020 Opts.support("cl_khr_global_int32_extended_atomics");
2021 Opts.support("cl_khr_local_int32_base_atomics");
2022 Opts.support("cl_khr_local_int32_extended_atomics");
2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2026 // CUDA compilations support all of the host's calling conventions.
2028 // TODO: We should warn if you apply a non-default CC to anything other than
2031 return HostTarget->checkCallingConvention(CC);
2032 return CCCR_Warning;
2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
2037 #define BUILTIN(ID, TYPE, ATTRS) \
2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2043 #include "clang/Basic/BuiltinsNVPTX.def"
2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
2049 return llvm::makeArrayRef(GCCRegNames);
2052 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = {
2056 2, // opencl_constant
2057 4, // opencl_generic
2062 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = {
2066 2, // opencl_constant
2067 0, // opencl_generic
2072 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = {
2076 2, // opencl_constant
2077 4, // opencl_generic
2082 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = {
2086 2, // opencl_constant
2087 0, // opencl_generic
2093 // If you edit the description strings, make sure you update
2094 // getPointerWidthV().
2096 static const char *const DataLayoutStringR600 =
2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2100 static const char *const DataLayoutStringSIPrivateIsZero =
2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
2105 static const char *const DataLayoutStringSIGenericIsZero =
2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
2110 class AMDGPUTargetInfo final : public TargetInfo {
2111 static const Builtin::Info BuiltinInfo[];
2112 static const char * const GCCRegNames[];
2115 unsigned Generic, Global, Local, Constant, Private;
2116 AddrSpace(bool IsGenericZero_ = false){
2117 if (IsGenericZero_) {
2133 /// \brief The GPU profiles supported by the AMDGPU target.
2141 GK_EVERGREEN_DOUBLE_OPS,
2142 GK_NORTHERN_ISLANDS,
2155 static bool hasFullSpeedFMAF32(StringRef GPUName) {
2156 return parseAMDGCNName(GPUName) >= GK_GFX9;
2159 static bool isAMDGCN(const llvm::Triple &TT) {
2160 return TT.getArch() == llvm::Triple::amdgcn;
2163 static bool isGenericZero(const llvm::Triple &TT) {
2164 return TT.getEnvironmentName() == "amdgiz" ||
2165 TT.getEnvironmentName() == "amdgizcl";
2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
2169 : TargetInfo(Triple) ,
2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
2174 AS(isGenericZero(Triple)){
2175 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2180 auto IsGenericZero = isGenericZero(Triple);
2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero :
2183 DataLayoutStringSIPrivateIsZero)
2184 : DataLayoutStringR600);
2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private);
2187 UseAddrSpaceMapMangling = true;
2190 void adjust(LangOptions &Opts) override {
2191 TargetInfo::adjust(Opts);
2192 if (isGenericZero(getTriple())) {
2193 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap
2194 : &AMDGPUNonOpenCLGenericIsZeroMap;
2196 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap
2197 : &AMDGPUNonOpenCLPrivateIsZeroMap;
2201 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
2202 if (GPU <= GK_CAYMAN)
2205 if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
2211 uint64_t getMaxPointerWidth() const override {
2212 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
2215 const char * getClobbers() const override {
2219 ArrayRef<const char *> getGCCRegNames() const override;
2221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2225 bool validateAsmConstraint(const char *&Name,
2226 TargetInfo::ConstraintInfo &Info) const override {
2231 Info.setAllowsRegister();
2237 bool initFeatureMap(llvm::StringMap<bool> &Features,
2238 DiagnosticsEngine &Diags, StringRef CPU,
2239 const std::vector<std::string> &FeatureVec) const override;
2241 void adjustTargetOptions(const CodeGenOptions &CGOpts,
2242 TargetOptions &TargetOpts) const override {
2243 bool hasFP32Denormals = false;
2244 bool hasFP64Denormals = false;
2245 for (auto &I : TargetOpts.FeaturesAsWritten) {
2246 if (I == "+fp32-denormals" || I == "-fp32-denormals")
2247 hasFP32Denormals = true;
2248 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
2249 hasFP64Denormals = true;
2251 if (!hasFP32Denormals)
2252 TargetOpts.Features.push_back(
2253 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
2254 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
2255 // Always do not flush fp64 or fp16 denorms.
2256 if (!hasFP64Denormals && hasFP64)
2257 TargetOpts.Features.push_back("+fp64-fp16-denormals");
2260 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2261 return llvm::makeArrayRef(BuiltinInfo,
2262 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
2265 void getTargetDefines(const LangOptions &Opts,
2266 MacroBuilder &Builder) const override {
2267 if (getTriple().getArch() == llvm::Triple::amdgcn)
2268 Builder.defineMacro("__AMDGCN__");
2270 Builder.defineMacro("__R600__");
2273 Builder.defineMacro("__HAS_FMAF__");
2275 Builder.defineMacro("__HAS_LDEXPF__");
2277 Builder.defineMacro("__HAS_FP64__");
2280 BuiltinVaListKind getBuiltinVaListKind() const override {
2281 return TargetInfo::CharPtrBuiltinVaList;
2284 static GPUKind parseR600Name(StringRef Name) {
2285 return llvm::StringSwitch<GPUKind>(Name)
2286 .Case("r600" , GK_R600)
2287 .Case("rv610", GK_R600)
2288 .Case("rv620", GK_R600)
2289 .Case("rv630", GK_R600)
2290 .Case("rv635", GK_R600)
2291 .Case("rs780", GK_R600)
2292 .Case("rs880", GK_R600)
2293 .Case("rv670", GK_R600_DOUBLE_OPS)
2294 .Case("rv710", GK_R700)
2295 .Case("rv730", GK_R700)
2296 .Case("rv740", GK_R700_DOUBLE_OPS)
2297 .Case("rv770", GK_R700_DOUBLE_OPS)
2298 .Case("palm", GK_EVERGREEN)
2299 .Case("cedar", GK_EVERGREEN)
2300 .Case("sumo", GK_EVERGREEN)
2301 .Case("sumo2", GK_EVERGREEN)
2302 .Case("redwood", GK_EVERGREEN)
2303 .Case("juniper", GK_EVERGREEN)
2304 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
2305 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
2306 .Case("barts", GK_NORTHERN_ISLANDS)
2307 .Case("turks", GK_NORTHERN_ISLANDS)
2308 .Case("caicos", GK_NORTHERN_ISLANDS)
2309 .Case("cayman", GK_CAYMAN)
2310 .Case("aruba", GK_CAYMAN)
2314 static GPUKind parseAMDGCNName(StringRef Name) {
2315 return llvm::StringSwitch<GPUKind>(Name)
2316 .Case("tahiti", GK_GFX6)
2317 .Case("pitcairn", GK_GFX6)
2318 .Case("verde", GK_GFX6)
2319 .Case("oland", GK_GFX6)
2320 .Case("hainan", GK_GFX6)
2321 .Case("bonaire", GK_GFX7)
2322 .Case("kabini", GK_GFX7)
2323 .Case("kaveri", GK_GFX7)
2324 .Case("hawaii", GK_GFX7)
2325 .Case("mullins", GK_GFX7)
2326 .Case("gfx700", GK_GFX7)
2327 .Case("gfx701", GK_GFX7)
2328 .Case("gfx702", GK_GFX7)
2329 .Case("tonga", GK_GFX8)
2330 .Case("iceland", GK_GFX8)
2331 .Case("carrizo", GK_GFX8)
2332 .Case("fiji", GK_GFX8)
2333 .Case("stoney", GK_GFX8)
2334 .Case("polaris10", GK_GFX8)
2335 .Case("polaris11", GK_GFX8)
2336 .Case("gfx800", GK_GFX8)
2337 .Case("gfx801", GK_GFX8)
2338 .Case("gfx802", GK_GFX8)
2339 .Case("gfx803", GK_GFX8)
2340 .Case("gfx804", GK_GFX8)
2341 .Case("gfx810", GK_GFX8)
2342 .Case("gfx900", GK_GFX9)
2343 .Case("gfx901", GK_GFX9)
2347 bool setCPU(const std::string &Name) override {
2348 if (getTriple().getArch() == llvm::Triple::amdgcn)
2349 GPU = parseAMDGCNName(Name);
2351 GPU = parseR600Name(Name);
2353 return GPU != GK_NONE;
2356 void setSupportedOpenCLOpts() override {
2357 auto &Opts = getSupportedOpenCLOpts();
2358 Opts.support("cl_clang_storage_class_specifiers");
2359 Opts.support("cl_khr_icd");
2362 Opts.support("cl_khr_fp64");
2363 if (GPU >= GK_EVERGREEN) {
2364 Opts.support("cl_khr_byte_addressable_store");
2365 Opts.support("cl_khr_global_int32_base_atomics");
2366 Opts.support("cl_khr_global_int32_extended_atomics");
2367 Opts.support("cl_khr_local_int32_base_atomics");
2368 Opts.support("cl_khr_local_int32_extended_atomics");
2370 if (GPU >= GK_GFX6) {
2371 Opts.support("cl_khr_fp16");
2372 Opts.support("cl_khr_int64_base_atomics");
2373 Opts.support("cl_khr_int64_extended_atomics");
2374 Opts.support("cl_khr_mipmap_image");
2375 Opts.support("cl_khr_subgroups");
2376 Opts.support("cl_khr_3d_image_writes");
2377 Opts.support("cl_amd_media_ops");
2378 Opts.support("cl_amd_media_ops2");
2382 LangAS::ID getOpenCLImageAddrSpace() const override {
2383 return LangAS::opencl_constant;
2386 /// \returns Target specific vtbl ptr address space.
2387 unsigned getVtblPtrAddressSpace() const override {
2388 // \todo: We currently have address spaces defined in AMDGPU Backend. It
2389 // would be nice if we could use it here instead of using bare numbers (same
2390 // applies to getDWARFAddressSpace).
2391 return 2; // constant.
2394 /// \returns If a target requires an address within a target specific address
2395 /// space \p AddressSpace to be converted in order to be used, then return the
2396 /// corresponding target specific DWARF address space.
2398 /// \returns Otherwise return None and no conversion will be emitted in the
2400 Optional<unsigned> getDWARFAddressSpace(
2401 unsigned AddressSpace) const override {
2402 const unsigned DWARF_Private = 1;
2403 const unsigned DWARF_Local = 2;
2404 if (AddressSpace == AS.Private) {
2405 return DWARF_Private;
2406 } else if (AddressSpace == AS.Local) {
2413 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2416 return CCCR_Warning;
2418 case CC_OpenCLKernel:
2423 // In amdgcn target the null pointer in global, constant, and generic
2424 // address space has value 0 but in private and local address space has
2426 uint64_t getNullPointerValue(unsigned AS) const override {
2427 return AS == LangAS::opencl_local ? ~0 : 0;
2431 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
2432 #define BUILTIN(ID, TYPE, ATTRS) \
2433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2434 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2435 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2436 #include "clang/Basic/BuiltinsAMDGPU.def"
2438 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
2439 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2440 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2441 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2442 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
2443 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
2444 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
2445 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
2446 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
2447 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
2448 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
2449 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
2450 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
2451 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
2452 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
2453 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
2454 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
2455 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
2456 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
2457 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
2458 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2459 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2460 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2461 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2462 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2463 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2464 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2465 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2466 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2467 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2468 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2469 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2470 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2472 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2473 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2474 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2475 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2476 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2477 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2478 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2479 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2480 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2481 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2482 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2483 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2484 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2485 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2486 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2487 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi",
2488 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi"
2491 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2492 return llvm::makeArrayRef(GCCRegNames);
2495 bool AMDGPUTargetInfo::initFeatureMap(
2496 llvm::StringMap<bool> &Features,
2497 DiagnosticsEngine &Diags, StringRef CPU,
2498 const std::vector<std::string> &FeatureVec) const {
2500 // XXX - What does the member GPU mean if device name string passed here?
2501 if (getTriple().getArch() == llvm::Triple::amdgcn) {
2505 switch (parseAMDGCNName(CPU)) {
2511 Features["gfx9-insts"] = true;
2514 Features["s-memrealtime"] = true;
2515 Features["16-bit-insts"] = true;
2516 Features["dpp"] = true;
2522 llvm_unreachable("unhandled subtarget");
2528 switch (parseR600Name(CPU)) {
2532 case GK_NORTHERN_ISLANDS:
2534 case GK_R600_DOUBLE_OPS:
2535 case GK_R700_DOUBLE_OPS:
2536 case GK_EVERGREEN_DOUBLE_OPS:
2538 Features["fp64"] = true;
2543 llvm_unreachable("unhandled subtarget");
2547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
2550 const Builtin::Info BuiltinInfoX86[] = {
2551 #define BUILTIN(ID, TYPE, ATTRS) \
2552 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2553 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2554 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2555 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2556 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2557 #include "clang/Basic/BuiltinsX86.def"
2559 #define BUILTIN(ID, TYPE, ATTRS) \
2560 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2561 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2562 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2563 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
2564 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
2565 #include "clang/Basic/BuiltinsX86_64.def"
2569 static const char* const GCCRegNames[] = {
2570 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2571 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2572 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2573 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2574 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2575 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2576 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2577 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2578 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2579 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23",
2580 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31",
2581 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23",
2582 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31",
2583 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7",
2584 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
2585 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
2586 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
2587 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
2590 const TargetInfo::AddlRegName AddlRegNames[] = {
2591 { { "al", "ah", "eax", "rax" }, 0 },
2592 { { "bl", "bh", "ebx", "rbx" }, 3 },
2593 { { "cl", "ch", "ecx", "rcx" }, 2 },
2594 { { "dl", "dh", "edx", "rdx" }, 1 },
2595 { { "esi", "rsi" }, 4 },
2596 { { "edi", "rdi" }, 5 },
2597 { { "esp", "rsp" }, 7 },
2598 { { "ebp", "rbp" }, 6 },
2599 { { "r8d", "r8w", "r8b" }, 38 },
2600 { { "r9d", "r9w", "r9b" }, 39 },
2601 { { "r10d", "r10w", "r10b" }, 40 },
2602 { { "r11d", "r11w", "r11b" }, 41 },
2603 { { "r12d", "r12w", "r12b" }, 42 },
2604 { { "r13d", "r13w", "r13b" }, 43 },
2605 { { "r14d", "r14w", "r14b" }, 44 },
2606 { { "r15d", "r15w", "r15b" }, 45 },
2609 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2610 // most of the implementation can be shared.
2611 class X86TargetInfo : public TargetInfo {
2613 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2616 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2617 } MMX3DNowLevel = NoMMX3DNow;
2625 bool HasAES = false;
2626 bool HasPCLMUL = false;
2627 bool HasLZCNT = false;
2628 bool HasRDRND = false;
2629 bool HasFSGSBASE = false;
2630 bool HasBMI = false;
2631 bool HasBMI2 = false;
2632 bool HasPOPCNT = false;
2633 bool HasRTM = false;
2634 bool HasPRFCHW = false;
2635 bool HasRDSEED = false;
2636 bool HasADX = false;
2637 bool HasTBM = false;
2638 bool HasLWP = false;
2639 bool HasFMA = false;
2640 bool HasF16C = false;
2641 bool HasAVX512CD = false;
2642 bool HasAVX512VPOPCNTDQ = false;
2643 bool HasAVX512ER = false;
2644 bool HasAVX512PF = false;
2645 bool HasAVX512DQ = false;
2646 bool HasAVX512BW = false;
2647 bool HasAVX512VL = false;
2648 bool HasAVX512VBMI = false;
2649 bool HasAVX512IFMA = false;
2650 bool HasSHA = false;
2651 bool HasMPX = false;
2652 bool HasSGX = false;
2653 bool HasCX16 = false;
2654 bool HasFXSR = false;
2655 bool HasXSAVE = false;
2656 bool HasXSAVEOPT = false;
2657 bool HasXSAVEC = false;
2658 bool HasXSAVES = false;
2659 bool HasMWAITX = false;
2660 bool HasCLZERO = false;
2661 bool HasPKU = false;
2662 bool HasCLFLUSHOPT = false;
2663 bool HasCLWB = false;
2664 bool HasMOVBE = false;
2665 bool HasPREFETCHWT1 = false;
2667 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2669 /// Each enumeration represents a particular CPU supported by Clang. These
2670 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2675 /// i386-generation processors.
2681 /// i486-generation processors.
2690 /// i586-generation processors, P5 microarchitecture based.
2698 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2708 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2709 /// Clang however has some logic to support this.
2710 // FIXME: Warn, deprecate, and potentially remove this.
2715 /// Netburst microarchitecture based processors.
2724 /// Core microarchitecture based processors.
2728 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2729 /// codename which GCC no longer accepts as an option to -march, but Clang
2730 /// has some logic for recognizing it.
2731 // FIXME: Warn, deprecate, and potentially remove this.
2744 /// Nehalem microarchitecture based processors.
2748 /// Westmere microarchitecture based processors.
2751 /// \name Sandy Bridge
2752 /// Sandy Bridge microarchitecture based processors.
2755 /// \name Ivy Bridge
2756 /// Ivy Bridge microarchitecture based processors.
2760 /// Haswell microarchitecture based processors.
2764 /// Broadwell microarchitecture based processors.
2767 /// \name Skylake Client
2768 /// Skylake client microarchitecture based processors.
2771 /// \name Skylake Server
2772 /// Skylake server microarchitecture based processors.
2775 /// \name Cannonlake Client
2776 /// Cannonlake client microarchitecture based processors.
2779 /// \name Knights Landing
2780 /// Knights Landing processor.
2784 /// Lakemont microarchitecture based processors.
2788 /// K6 architecture processors.
2796 /// K7 architecture processors.
2799 CK_AthlonThunderbird,
2806 /// K8 architecture processors.
2819 /// Bobcat architecture processors.
2826 /// Bulldozer architecture processors.
2835 /// Zen architecture processors.
2840 /// This specification is deprecated and will be removed in the future.
2841 /// Users should prefer \see CK_K8.
2842 // FIXME: Warn on this when the CPU is set to it.
2848 /// Geode processors.
2854 CPUKind getCPUKind(StringRef CPU) const {
2855 return llvm::StringSwitch<CPUKind>(CPU)
2856 .Case("i386", CK_i386)
2857 .Case("i486", CK_i486)
2858 .Case("winchip-c6", CK_WinChipC6)
2859 .Case("winchip2", CK_WinChip2)
2861 .Case("i586", CK_i586)
2862 .Case("pentium", CK_Pentium)
2863 .Case("pentium-mmx", CK_PentiumMMX)
2864 .Case("i686", CK_i686)
2865 .Case("pentiumpro", CK_PentiumPro)
2866 .Case("pentium2", CK_Pentium2)
2867 .Case("pentium3", CK_Pentium3)
2868 .Case("pentium3m", CK_Pentium3M)
2869 .Case("pentium-m", CK_PentiumM)
2870 .Case("c3-2", CK_C3_2)
2871 .Case("yonah", CK_Yonah)
2872 .Case("pentium4", CK_Pentium4)
2873 .Case("pentium4m", CK_Pentium4M)
2874 .Case("prescott", CK_Prescott)
2875 .Case("nocona", CK_Nocona)
2876 .Case("core2", CK_Core2)
2877 .Case("penryn", CK_Penryn)
2878 .Case("bonnell", CK_Bonnell)
2879 .Case("atom", CK_Bonnell) // Legacy name.
2880 .Case("silvermont", CK_Silvermont)
2881 .Case("slm", CK_Silvermont) // Legacy name.
2882 .Case("goldmont", CK_Goldmont)
2883 .Case("nehalem", CK_Nehalem)
2884 .Case("corei7", CK_Nehalem) // Legacy name.
2885 .Case("westmere", CK_Westmere)
2886 .Case("sandybridge", CK_SandyBridge)
2887 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2888 .Case("ivybridge", CK_IvyBridge)
2889 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2890 .Case("haswell", CK_Haswell)
2891 .Case("core-avx2", CK_Haswell) // Legacy name.
2892 .Case("broadwell", CK_Broadwell)
2893 .Case("skylake", CK_SkylakeClient)
2894 .Case("skylake-avx512", CK_SkylakeServer)
2895 .Case("skx", CK_SkylakeServer) // Legacy name.
2896 .Case("cannonlake", CK_Cannonlake)
2897 .Case("knl", CK_KNL)
2898 .Case("lakemont", CK_Lakemont)
2900 .Case("k6-2", CK_K6_2)
2901 .Case("k6-3", CK_K6_3)
2902 .Case("athlon", CK_Athlon)
2903 .Case("athlon-tbird", CK_AthlonThunderbird)
2904 .Case("athlon-4", CK_Athlon4)
2905 .Case("athlon-xp", CK_AthlonXP)
2906 .Case("athlon-mp", CK_AthlonMP)
2907 .Case("athlon64", CK_Athlon64)
2908 .Case("athlon64-sse3", CK_Athlon64SSE3)
2909 .Case("athlon-fx", CK_AthlonFX)
2911 .Case("k8-sse3", CK_K8SSE3)
2912 .Case("opteron", CK_Opteron)
2913 .Case("opteron-sse3", CK_OpteronSSE3)
2914 .Case("barcelona", CK_AMDFAM10)
2915 .Case("amdfam10", CK_AMDFAM10)
2916 .Case("btver1", CK_BTVER1)
2917 .Case("btver2", CK_BTVER2)
2918 .Case("bdver1", CK_BDVER1)
2919 .Case("bdver2", CK_BDVER2)
2920 .Case("bdver3", CK_BDVER3)
2921 .Case("bdver4", CK_BDVER4)
2922 .Case("znver1", CK_ZNVER1)
2923 .Case("x86-64", CK_x86_64)
2924 .Case("geode", CK_Geode)
2925 .Default(CK_Generic);
2932 } FPMath = FP_Default;
2935 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
2936 : TargetInfo(Triple) {
2937 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
2939 unsigned getFloatEvalMethod() const override {
2940 // X87 evaluates with 80 bits "long double" precision.
2941 return SSELevel == NoSSE ? 2 : 0;
2943 ArrayRef<const char *> getGCCRegNames() const override {
2944 return llvm::makeArrayRef(GCCRegNames);
2946 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2949 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2950 return llvm::makeArrayRef(AddlRegNames);
2952 bool validateCpuSupports(StringRef Name) const override;
2953 bool validateAsmConstraint(const char *&Name,
2954 TargetInfo::ConstraintInfo &info) const override;
2956 bool validateGlobalRegisterVariable(StringRef RegName,
2958 bool &HasSizeMismatch) const override {
2959 // esp and ebp are the only 32-bit registers the x86 backend can currently
2961 if (RegName.equals("esp") || RegName.equals("ebp")) {
2962 // Check that the register size is 32-bit.
2963 HasSizeMismatch = RegSize != 32;
2970 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2972 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2974 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2976 std::string convertConstraint(const char *&Constraint) const override;
2977 const char *getClobbers() const override {
2978 return "~{dirflag},~{fpsr},~{flags}";
2981 StringRef getConstraintRegister(const StringRef &Constraint,
2982 const StringRef &Expression) const override {
2983 StringRef::iterator I, E;
2984 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
2991 // For the register constraints, return the matching register name
3004 // In case the constraint is 'r' we need to return Expression
3008 // Default value if there is no constraint for the register
3014 void getTargetDefines(const LangOptions &Opts,
3015 MacroBuilder &Builder) const override;
3016 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
3018 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
3020 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3022 void setFeatureEnabled(llvm::StringMap<bool> &Features,
3023 StringRef Name, bool Enabled) const override {
3024 setFeatureEnabledImpl(Features, Name, Enabled);
3026 // This exists purely to cut down on the number of virtual calls in
3027 // initFeatureMap which calls this repeatedly.
3028 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3029 StringRef Name, bool Enabled);
3031 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
3033 const std::vector<std::string> &FeaturesVec) const override;
3034 bool hasFeature(StringRef Feature) const override;
3035 bool handleTargetFeatures(std::vector<std::string> &Features,
3036 DiagnosticsEngine &Diags) override;
3037 StringRef getABI() const override {
3038 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
3040 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
3042 if (getTriple().getArch() == llvm::Triple::x86 &&
3043 MMX3DNowLevel == NoMMX3DNow)
3047 bool setCPU(const std::string &Name) override {
3048 CPU = getCPUKind(Name);
3050 // Perform any per-CPU checks necessary to determine if this CPU is
3052 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
3053 // invalid without explaining *why*.
3056 // No processor selected!
3083 case CK_AthlonThunderbird:
3088 // Only accept certain architectures when compiling in 32-bit mode.
3089 if (getTriple().getArch() != llvm::Triple::x86)
3101 case CK_SandyBridge:
3105 case CK_SkylakeClient:
3106 case CK_SkylakeServer:
3110 case CK_Athlon64SSE3:
3115 case CK_OpteronSSE3:
3127 llvm_unreachable("Unhandled CPU kind");
3130 bool setFPMath(StringRef Name) override;
3132 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3133 // Most of the non-ARM calling conventions are i386 conventions.
3135 case CC_X86ThisCall:
3136 case CC_X86FastCall:
3138 case CC_X86VectorCall:
3143 case CC_IntelOclBicc:
3144 case CC_OpenCLKernel:
3147 return CCCR_Warning;
3151 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3152 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
3155 bool hasSjLjLowering() const override {
3159 void setSupportedOpenCLOpts() override {
3160 getSupportedOpenCLOpts().supportAll();
3164 bool X86TargetInfo::setFPMath(StringRef Name) {
3165 if (Name == "387") {
3169 if (Name == "sse") {
3176 bool X86TargetInfo::initFeatureMap(
3177 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
3178 const std::vector<std::string> &FeaturesVec) const {
3179 // FIXME: This *really* should not be here.
3180 // X86_64 always has SSE2.
3181 if (getTriple().getArch() == llvm::Triple::x86_64)
3182 setFeatureEnabledImpl(Features, "sse2", true);
3184 const CPUKind Kind = getCPUKind(CPU);
3186 // Enable X87 for all X86 processors but Lakemont.
3187 if (Kind != CK_Lakemont)
3188 setFeatureEnabledImpl(Features, "x87", true);
3204 setFeatureEnabledImpl(Features, "mmx", true);
3209 setFeatureEnabledImpl(Features, "sse", true);
3210 setFeatureEnabledImpl(Features, "fxsr", true);
3216 setFeatureEnabledImpl(Features, "sse2", true);
3217 setFeatureEnabledImpl(Features, "fxsr", true);
3222 setFeatureEnabledImpl(Features, "sse3", true);
3223 setFeatureEnabledImpl(Features, "fxsr", true);
3224 setFeatureEnabledImpl(Features, "cx16", true);
3227 setFeatureEnabledImpl(Features, "ssse3", true);
3228 setFeatureEnabledImpl(Features, "fxsr", true);
3229 setFeatureEnabledImpl(Features, "cx16", true);
3232 setFeatureEnabledImpl(Features, "sse4.1", true);
3233 setFeatureEnabledImpl(Features, "fxsr", true);
3234 setFeatureEnabledImpl(Features, "cx16", true);
3237 setFeatureEnabledImpl(Features, "avx512ifma", true);
3238 setFeatureEnabledImpl(Features, "avx512vbmi", true);
3239 setFeatureEnabledImpl(Features, "sha", true);
3241 case CK_SkylakeServer:
3242 setFeatureEnabledImpl(Features, "avx512f", true);
3243 setFeatureEnabledImpl(Features, "avx512cd", true);
3244 setFeatureEnabledImpl(Features, "avx512dq", true);
3245 setFeatureEnabledImpl(Features, "avx512bw", true);
3246 setFeatureEnabledImpl(Features, "avx512vl", true);
3247 setFeatureEnabledImpl(Features, "pku", true);
3248 setFeatureEnabledImpl(Features, "clwb", true);
3250 case CK_SkylakeClient:
3251 setFeatureEnabledImpl(Features, "xsavec", true);
3252 setFeatureEnabledImpl(Features, "xsaves", true);
3253 setFeatureEnabledImpl(Features, "mpx", true);
3254 setFeatureEnabledImpl(Features, "sgx", true);
3255 setFeatureEnabledImpl(Features, "clflushopt", true);
3256 setFeatureEnabledImpl(Features, "rtm", true);
3259 setFeatureEnabledImpl(Features, "rdseed", true);
3260 setFeatureEnabledImpl(Features, "adx", true);
3263 setFeatureEnabledImpl(Features, "avx2", true);
3264 setFeatureEnabledImpl(Features, "lzcnt", true);
3265 setFeatureEnabledImpl(Features, "bmi", true);
3266 setFeatureEnabledImpl(Features, "bmi2", true);
3267 setFeatureEnabledImpl(Features, "fma", true);
3268 setFeatureEnabledImpl(Features, "movbe", true);
3271 setFeatureEnabledImpl(Features, "rdrnd", true);
3272 setFeatureEnabledImpl(Features, "f16c", true);
3273 setFeatureEnabledImpl(Features, "fsgsbase", true);
3275 case CK_SandyBridge:
3276 setFeatureEnabledImpl(Features, "avx", true);
3277 setFeatureEnabledImpl(Features, "xsave", true);
3278 setFeatureEnabledImpl(Features, "xsaveopt", true);
3281 setFeatureEnabledImpl(Features, "aes", true);
3282 setFeatureEnabledImpl(Features, "pclmul", true);
3285 setFeatureEnabledImpl(Features, "sse4.2", true);
3286 setFeatureEnabledImpl(Features, "fxsr", true);
3287 setFeatureEnabledImpl(Features, "cx16", true);
3290 setFeatureEnabledImpl(Features, "sha", true);
3291 setFeatureEnabledImpl(Features, "rdrnd", true);
3292 setFeatureEnabledImpl(Features, "rdseed", true);
3293 setFeatureEnabledImpl(Features, "xsave", true);
3294 setFeatureEnabledImpl(Features, "xsaveopt", true);
3295 setFeatureEnabledImpl(Features, "xsavec", true);
3296 setFeatureEnabledImpl(Features, "xsaves", true);
3297 setFeatureEnabledImpl(Features, "clflushopt", true);
3298 setFeatureEnabledImpl(Features, "mpx", true);
3301 setFeatureEnabledImpl(Features, "aes", true);
3302 setFeatureEnabledImpl(Features, "pclmul", true);
3303 setFeatureEnabledImpl(Features, "sse4.2", true);
3306 setFeatureEnabledImpl(Features, "movbe", true);
3307 setFeatureEnabledImpl(Features, "ssse3", true);
3308 setFeatureEnabledImpl(Features, "fxsr", true);
3309 setFeatureEnabledImpl(Features, "cx16", true);
3312 setFeatureEnabledImpl(Features, "avx512f", true);
3313 setFeatureEnabledImpl(Features, "avx512cd", true);
3314 setFeatureEnabledImpl(Features, "avx512er", true);
3315 setFeatureEnabledImpl(Features, "avx512pf", true);
3316 setFeatureEnabledImpl(Features, "prefetchwt1", true);
3317 setFeatureEnabledImpl(Features, "fxsr", true);
3318 setFeatureEnabledImpl(Features, "rdseed", true);
3319 setFeatureEnabledImpl(Features, "adx", true);
3320 setFeatureEnabledImpl(Features, "lzcnt", true);
3321 setFeatureEnabledImpl(Features, "bmi", true);
3322 setFeatureEnabledImpl(Features, "bmi2", true);
3323 setFeatureEnabledImpl(Features, "rtm", true);
3324 setFeatureEnabledImpl(Features, "fma", true);
3325 setFeatureEnabledImpl(Features, "rdrnd", true);
3326 setFeatureEnabledImpl(Features, "f16c", true);
3327 setFeatureEnabledImpl(Features, "fsgsbase", true);
3328 setFeatureEnabledImpl(Features, "aes", true);
3329 setFeatureEnabledImpl(Features, "pclmul", true);
3330 setFeatureEnabledImpl(Features, "cx16", true);
3331 setFeatureEnabledImpl(Features, "xsaveopt", true);
3332 setFeatureEnabledImpl(Features, "xsave", true);
3333 setFeatureEnabledImpl(Features, "movbe", true);
3339 setFeatureEnabledImpl(Features, "3dnow", true);
3342 case CK_AthlonThunderbird:
3344 setFeatureEnabledImpl(Features, "3dnowa", true);
3349 setFeatureEnabledImpl(Features, "sse", true);
3350 setFeatureEnabledImpl(Features, "3dnowa", true);
3351 setFeatureEnabledImpl(Features, "fxsr", true);
3357 setFeatureEnabledImpl(Features, "sse2", true);
3358 setFeatureEnabledImpl(Features, "3dnowa", true);
3359 setFeatureEnabledImpl(Features, "fxsr", true);
3362 setFeatureEnabledImpl(Features, "sse4a", true);
3363 setFeatureEnabledImpl(Features, "lzcnt", true);
3364 setFeatureEnabledImpl(Features, "popcnt", true);
3367 case CK_OpteronSSE3:
3368 case CK_Athlon64SSE3:
3369 setFeatureEnabledImpl(Features, "sse3", true);
3370 setFeatureEnabledImpl(Features, "3dnowa", true);
3371 setFeatureEnabledImpl(Features, "fxsr", true);
3374 setFeatureEnabledImpl(Features, "avx", true);
3375 setFeatureEnabledImpl(Features, "aes", true);
3376 setFeatureEnabledImpl(Features, "pclmul", true);
3377 setFeatureEnabledImpl(Features, "bmi", true);
3378 setFeatureEnabledImpl(Features, "f16c", true);
3379 setFeatureEnabledImpl(Features, "xsaveopt", true);
3382 setFeatureEnabledImpl(Features, "ssse3", true);
3383 setFeatureEnabledImpl(Features, "sse4a", true);
3384 setFeatureEnabledImpl(Features, "lzcnt", true);
3385 setFeatureEnabledImpl(Features, "popcnt", true);
3386 setFeatureEnabledImpl(Features, "prfchw", true);
3387 setFeatureEnabledImpl(Features, "cx16", true);
3388 setFeatureEnabledImpl(Features, "fxsr", true);
3391 setFeatureEnabledImpl(Features, "adx", true);
3392 setFeatureEnabledImpl(Features, "aes", true);
3393 setFeatureEnabledImpl(Features, "avx2", true);
3394 setFeatureEnabledImpl(Features, "bmi", true);
3395 setFeatureEnabledImpl(Features, "bmi2", true);
3396 setFeatureEnabledImpl(Features, "clflushopt", true);
3397 setFeatureEnabledImpl(Features, "clzero", true);
3398 setFeatureEnabledImpl(Features, "cx16", true);
3399 setFeatureEnabledImpl(Features, "f16c", true);
3400 setFeatureEnabledImpl(Features, "fma", true);
3401 setFeatureEnabledImpl(Features, "fsgsbase", true);
3402 setFeatureEnabledImpl(Features, "fxsr", true);
3403 setFeatureEnabledImpl(Features, "lzcnt", true);
3404 setFeatureEnabledImpl(Features, "mwaitx", true);
3405 setFeatureEnabledImpl(Features, "movbe", true);
3406 setFeatureEnabledImpl(Features, "pclmul", true);
3407 setFeatureEnabledImpl(Features, "popcnt", true);
3408 setFeatureEnabledImpl(Features, "prfchw", true);
3409 setFeatureEnabledImpl(Features, "rdrnd", true);
3410 setFeatureEnabledImpl(Features, "rdseed", true);
3411 setFeatureEnabledImpl(Features, "sha", true);
3412 setFeatureEnabledImpl(Features, "sse4a", true);
3413 setFeatureEnabledImpl(Features, "xsave", true);
3414 setFeatureEnabledImpl(Features, "xsavec", true);
3415 setFeatureEnabledImpl(Features, "xsaveopt", true);
3416 setFeatureEnabledImpl(Features, "xsaves", true);
3419 setFeatureEnabledImpl(Features, "avx2", true);
3420 setFeatureEnabledImpl(Features, "bmi2", true);
3421 setFeatureEnabledImpl(Features, "mwaitx", true);
3424 setFeatureEnabledImpl(Features, "fsgsbase", true);
3425 setFeatureEnabledImpl(Features, "xsaveopt", true);
3428 setFeatureEnabledImpl(Features, "bmi", true);
3429 setFeatureEnabledImpl(Features, "fma", true);
3430 setFeatureEnabledImpl(Features, "f16c", true);
3431 setFeatureEnabledImpl(Features, "tbm", true);
3434 // xop implies avx, sse4a and fma4.
3435 setFeatureEnabledImpl(Features, "xop", true);
3436 setFeatureEnabledImpl(Features, "lwp", true);
3437 setFeatureEnabledImpl(Features, "lzcnt", true);
3438 setFeatureEnabledImpl(Features, "aes", true);
3439 setFeatureEnabledImpl(Features, "pclmul", true);
3440 setFeatureEnabledImpl(Features, "prfchw", true);
3441 setFeatureEnabledImpl(Features, "cx16", true);
3442 setFeatureEnabledImpl(Features, "fxsr", true);
3443 setFeatureEnabledImpl(Features, "xsave", true);
3446 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
3449 // Can't do this earlier because we need to be able to explicitly enable
3450 // or disable these features and the things that they depend upon.
3452 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3453 auto I = Features.find("sse4.2");
3454 if (I != Features.end() && I->getValue() &&
3455 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
3457 Features["popcnt"] = true;
3459 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3460 I = Features.find("3dnow");
3461 if (I != Features.end() && I->getValue() &&
3462 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
3464 Features["prfchw"] = true;
3466 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3468 I = Features.find("sse");
3469 if (I != Features.end() && I->getValue() &&
3470 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
3472 Features["mmx"] = true;
3477 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
3478 X86SSEEnum Level, bool Enabled) {
3482 Features["avx512f"] = true;
3485 Features["avx2"] = true;
3488 Features["avx"] = true;
3489 Features["xsave"] = true;
3492 Features["sse4.2"] = true;
3495 Features["sse4.1"] = true;
3498 Features["ssse3"] = true;
3501 Features["sse3"] = true;
3504 Features["sse2"] = true;
3507 Features["sse"] = true;
3518 Features["sse"] = false;
3521 Features["sse2"] = Features["pclmul"] = Features["aes"] =
3522 Features["sha"] = false;
3525 Features["sse3"] = false;
3526 setXOPLevel(Features, NoXOP, false);
3529 Features["ssse3"] = false;
3532 Features["sse4.1"] = false;
3535 Features["sse4.2"] = false;
3538 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
3539 Features["xsaveopt"] = false;
3540 setXOPLevel(Features, FMA4, false);
3543 Features["avx2"] = false;
3546 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
3547 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
3548 Features["avx512vl"] = Features["avx512vbmi"] =
3549 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
3554 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
3555 MMX3DNowEnum Level, bool Enabled) {
3558 case AMD3DNowAthlon:
3559 Features["3dnowa"] = true;
3562 Features["3dnow"] = true;
3565 Features["mmx"] = true;
3576 Features["mmx"] = false;
3579 Features["3dnow"] = false;
3581 case AMD3DNowAthlon:
3582 Features["3dnowa"] = false;
3587 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
3592 Features["xop"] = true;
3595 Features["fma4"] = true;
3596 setSSELevel(Features, AVX, true);
3599 Features["sse4a"] = true;
3600 setSSELevel(Features, SSE3, true);
3611 Features["sse4a"] = false;
3614 Features["fma4"] = false;
3617 Features["xop"] = false;
3622 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
3623 StringRef Name, bool Enabled) {
3624 // This is a bit of a hack to deal with the sse4 target feature when used
3625 // as part of the target attribute. We handle sse4 correctly everywhere
3626 // else. See below for more information on how we handle the sse4 options.
3628 Features[Name] = Enabled;
3630 if (Name == "mmx") {
3631 setMMXLevel(Features, MMX, Enabled);
3632 } else if (Name == "sse") {
3633 setSSELevel(Features, SSE1, Enabled);
3634 } else if (Name == "sse2") {
3635 setSSELevel(Features, SSE2, Enabled);
3636 } else if (Name == "sse3") {
3637 setSSELevel(Features, SSE3, Enabled);
3638 } else if (Name == "ssse3") {
3639 setSSELevel(Features, SSSE3, Enabled);
3640 } else if (Name == "sse4.2") {
3641 setSSELevel(Features, SSE42, Enabled);
3642 } else if (Name == "sse4.1") {
3643 setSSELevel(Features, SSE41, Enabled);
3644 } else if (Name == "3dnow") {
3645 setMMXLevel(Features, AMD3DNow, Enabled);
3646 } else if (Name == "3dnowa") {
3647 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
3648 } else if (Name == "aes") {
3650 setSSELevel(Features, SSE2, Enabled);
3651 } else if (Name == "pclmul") {
3653 setSSELevel(Features, SSE2, Enabled);
3654 } else if (Name == "avx") {
3655 setSSELevel(Features, AVX, Enabled);
3656 } else if (Name == "avx2") {
3657 setSSELevel(Features, AVX2, Enabled);
3658 } else if (Name == "avx512f") {
3659 setSSELevel(Features, AVX512F, Enabled);
3660 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
3661 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
3662 Name == "avx512vbmi" || Name == "avx512ifma" ||
3663 Name == "avx512vpopcntdq") {
3665 setSSELevel(Features, AVX512F, Enabled);
3666 // Enable BWI instruction if VBMI is being enabled.
3667 if (Name == "avx512vbmi" && Enabled)
3668 Features["avx512bw"] = true;
3669 // Also disable VBMI if BWI is being disabled.
3670 if (Name == "avx512bw" && !Enabled)
3671 Features["avx512vbmi"] = false;
3672 } else if (Name == "fma") {
3674 setSSELevel(Features, AVX, Enabled);
3675 } else if (Name == "fma4") {
3676 setXOPLevel(Features, FMA4, Enabled);
3677 } else if (Name == "xop") {
3678 setXOPLevel(Features, XOP, Enabled);
3679 } else if (Name == "sse4a") {
3680 setXOPLevel(Features, SSE4A, Enabled);
3681 } else if (Name == "f16c") {
3683 setSSELevel(Features, AVX, Enabled);
3684 } else if (Name == "sha") {
3686 setSSELevel(Features, SSE2, Enabled);
3687 } else if (Name == "sse4") {
3688 // We can get here via the __target__ attribute since that's not controlled
3689 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
3690 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
3693 setSSELevel(Features, SSE42, Enabled);
3695 setSSELevel(Features, SSE41, Enabled);
3696 } else if (Name == "xsave") {
3698 Features["xsaveopt"] = false;
3699 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
3701 Features["xsave"] = true;
3705 /// handleTargetFeatures - Perform initialization based on the user
3706 /// configured set of features.
3707 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
3708 DiagnosticsEngine &Diags) {
3709 for (const auto &Feature : Features) {
3710 if (Feature[0] != '+')
3713 if (Feature == "+aes") {
3715 } else if (Feature == "+pclmul") {
3717 } else if (Feature == "+lzcnt") {
3719 } else if (Feature == "+rdrnd") {
3721 } else if (Feature == "+fsgsbase") {
3723 } else if (Feature == "+bmi") {
3725 } else if (Feature == "+bmi2") {
3727 } else if (Feature == "+popcnt") {
3729 } else if (Feature == "+rtm") {
3731 } else if (Feature == "+prfchw") {
3733 } else if (Feature == "+rdseed") {
3735 } else if (Feature == "+adx") {
3737 } else if (Feature == "+tbm") {
3739 } else if (Feature == "+lwp") {
3741 } else if (Feature == "+fma") {
3743 } else if (Feature == "+f16c") {
3745 } else if (Feature == "+avx512cd") {
3747 } else if (Feature == "+avx512vpopcntdq") {
3748 HasAVX512VPOPCNTDQ = true;
3749 } else if (Feature == "+avx512er") {
3751 } else if (Feature == "+avx512pf") {
3753 } else if (Feature == "+avx512dq") {
3755 } else if (Feature == "+avx512bw") {
3757 } else if (Feature == "+avx512vl") {
3759 } else if (Feature == "+avx512vbmi") {
3760 HasAVX512VBMI = true;
3761 } else if (Feature == "+avx512ifma") {
3762 HasAVX512IFMA = true;
3763 } else if (Feature == "+sha") {
3765 } else if (Feature == "+mpx") {
3767 } else if (Feature == "+movbe") {
3769 } else if (Feature == "+sgx") {
3771 } else if (Feature == "+cx16") {
3773 } else if (Feature == "+fxsr") {
3775 } else if (Feature == "+xsave") {
3777 } else if (Feature == "+xsaveopt") {
3779 } else if (Feature == "+xsavec") {
3781 } else if (Feature == "+xsaves") {
3783 } else if (Feature == "+mwaitx") {
3785 } else if (Feature == "+pku") {
3787 } else if (Feature == "+clflushopt") {
3788 HasCLFLUSHOPT = true;
3789 } else if (Feature == "+clwb") {
3791 } else if (Feature == "+prefetchwt1") {
3792 HasPREFETCHWT1 = true;
3793 } else if (Feature == "+clzero") {
3797 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3798 .Case("+avx512f", AVX512F)
3799 .Case("+avx2", AVX2)
3801 .Case("+sse4.2", SSE42)
3802 .Case("+sse4.1", SSE41)
3803 .Case("+ssse3", SSSE3)
3804 .Case("+sse3", SSE3)
3805 .Case("+sse2", SSE2)
3808 SSELevel = std::max(SSELevel, Level);
3810 MMX3DNowEnum ThreeDNowLevel =
3811 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3812 .Case("+3dnowa", AMD3DNowAthlon)
3813 .Case("+3dnow", AMD3DNow)
3815 .Default(NoMMX3DNow);
3816 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3818 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3820 .Case("+fma4", FMA4)
3821 .Case("+sse4a", SSE4A)
3823 XOPLevel = std::max(XOPLevel, XLevel);
3826 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3827 // matches the selected sse level.
3828 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3829 (FPMath == FP_387 && SSELevel >= SSE1)) {
3830 Diags.Report(diag::err_target_unsupported_fpmath) <<
3831 (FPMath == FP_SSE ? "sse" : "387");
3836 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3840 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3841 /// definitions for this particular subtarget.
3842 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3843 MacroBuilder &Builder) const {
3844 // Target identification.
3845 if (getTriple().getArch() == llvm::Triple::x86_64) {
3846 Builder.defineMacro("__amd64__");
3847 Builder.defineMacro("__amd64");
3848 Builder.defineMacro("__x86_64");
3849 Builder.defineMacro("__x86_64__");
3850 if (getTriple().getArchName() == "x86_64h") {
3851 Builder.defineMacro("__x86_64h");
3852 Builder.defineMacro("__x86_64h__");
3855 DefineStd(Builder, "i386", Opts);
3858 // Subtarget options.
3859 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3860 // truly should be based on -mtune options.
3865 // The rest are coming from the i386 define above.
3866 Builder.defineMacro("__tune_i386__");
3872 defineCPUMacros(Builder, "i486");
3875 Builder.defineMacro("__pentium_mmx__");
3876 Builder.defineMacro("__tune_pentium_mmx__");
3880 defineCPUMacros(Builder, "i586");
3881 defineCPUMacros(Builder, "pentium");
3886 Builder.defineMacro("__tune_pentium3__");
3890 Builder.defineMacro("__tune_pentium2__");
3893 Builder.defineMacro("__tune_i686__");
3894 Builder.defineMacro("__tune_pentiumpro__");
3897 Builder.defineMacro("__i686");
3898 Builder.defineMacro("__i686__");
3899 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3900 Builder.defineMacro("__pentiumpro");
3901 Builder.defineMacro("__pentiumpro__");
3905 defineCPUMacros(Builder, "pentium4");
3910 defineCPUMacros(Builder, "nocona");
3914 defineCPUMacros(Builder, "core2");
3917 defineCPUMacros(Builder, "atom");
3920 defineCPUMacros(Builder, "slm");
3923 defineCPUMacros(Builder, "goldmont");
3927 case CK_SandyBridge:
3931 case CK_SkylakeClient:
3932 // FIXME: Historically, we defined this legacy name, it would be nice to
3933 // remove it at some point. We've never exposed fine-grained names for
3934 // recent primary x86 CPUs, and we should keep it that way.
3935 defineCPUMacros(Builder, "corei7");
3937 case CK_SkylakeServer:
3938 defineCPUMacros(Builder, "skx");
3943 defineCPUMacros(Builder, "knl");
3946 Builder.defineMacro("__tune_lakemont__");
3949 Builder.defineMacro("__k6_2__");
3950 Builder.defineMacro("__tune_k6_2__");
3953 if (CPU != CK_K6_2) { // In case of fallthrough
3954 // FIXME: GCC may be enabling these in cases where some other k6
3955 // architecture is specified but -m3dnow is explicitly provided. The
3956 // exact semantics need to be determined and emulated here.
3957 Builder.defineMacro("__k6_3__");
3958 Builder.defineMacro("__tune_k6_3__");
3962 defineCPUMacros(Builder, "k6");
3965 case CK_AthlonThunderbird:
3969 defineCPUMacros(Builder, "athlon");
3970 if (SSELevel != NoSSE) {
3971 Builder.defineMacro("__athlon_sse__");
3972 Builder.defineMacro("__tune_athlon_sse__");
3979 case CK_OpteronSSE3:
3981 case CK_Athlon64SSE3:
3983 defineCPUMacros(Builder, "k8");
3986 defineCPUMacros(Builder, "amdfam10");
3989 defineCPUMacros(Builder, "btver1");
3992 defineCPUMacros(Builder, "btver2");
3995 defineCPUMacros(Builder, "bdver1");
3998 defineCPUMacros(Builder, "bdver2");
4001 defineCPUMacros(Builder, "bdver3");
4004 defineCPUMacros(Builder, "bdver4");
4007 defineCPUMacros(Builder, "znver1");
4010 defineCPUMacros(Builder, "geode");
4014 // Target properties.
4015 Builder.defineMacro("__REGISTER_PREFIX__", "");
4017 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
4018 // functions in glibc header files that use FP Stack inline asm which the
4019 // backend can't deal with (PR879).
4020 Builder.defineMacro("__NO_MATH_INLINES");
4023 Builder.defineMacro("__AES__");
4026 Builder.defineMacro("__PCLMUL__");
4029 Builder.defineMacro("__LZCNT__");
4032 Builder.defineMacro("__RDRND__");
4035 Builder.defineMacro("__FSGSBASE__");
4038 Builder.defineMacro("__BMI__");
4041 Builder.defineMacro("__BMI2__");
4044 Builder.defineMacro("__POPCNT__");
4047 Builder.defineMacro("__RTM__");
4050 Builder.defineMacro("__PRFCHW__");
4053 Builder.defineMacro("__RDSEED__");
4056 Builder.defineMacro("__ADX__");
4059 Builder.defineMacro("__TBM__");
4062 Builder.defineMacro("__LWP__");
4065 Builder.defineMacro("__MWAITX__");
4069 Builder.defineMacro("__XOP__");
4072 Builder.defineMacro("__FMA4__");
4075 Builder.defineMacro("__SSE4A__");
4082 Builder.defineMacro("__FMA__");
4085 Builder.defineMacro("__F16C__");
4088 Builder.defineMacro("__AVX512CD__");
4089 if (HasAVX512VPOPCNTDQ)
4090 Builder.defineMacro("__AVX512VPOPCNTDQ__");
4092 Builder.defineMacro("__AVX512ER__");
4094 Builder.defineMacro("__AVX512PF__");
4096 Builder.defineMacro("__AVX512DQ__");
4098 Builder.defineMacro("__AVX512BW__");
4100 Builder.defineMacro("__AVX512VL__");
4102 Builder.defineMacro("__AVX512VBMI__");
4104 Builder.defineMacro("__AVX512IFMA__");
4107 Builder.defineMacro("__SHA__");
4110 Builder.defineMacro("__FXSR__");
4112 Builder.defineMacro("__XSAVE__");
4114 Builder.defineMacro("__XSAVEOPT__");
4116 Builder.defineMacro("__XSAVEC__");
4118 Builder.defineMacro("__XSAVES__");
4120 Builder.defineMacro("__PKU__");
4122 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
4124 Builder.defineMacro("__CLFLUSHOPT__");
4126 Builder.defineMacro("__CLWB__");
4128 Builder.defineMacro("__MPX__");
4130 Builder.defineMacro("__SGX__");
4132 Builder.defineMacro("__PREFETCHWT1__");
4134 Builder.defineMacro("__CLZERO__");
4136 // Each case falls through to the previous one here.
4139 Builder.defineMacro("__AVX512F__");
4142 Builder.defineMacro("__AVX2__");
4145 Builder.defineMacro("__AVX__");
4148 Builder.defineMacro("__SSE4_2__");
4151 Builder.defineMacro("__SSE4_1__");
4154 Builder.defineMacro("__SSSE3__");
4157 Builder.defineMacro("__SSE3__");
4160 Builder.defineMacro("__SSE2__");
4161 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
4164 Builder.defineMacro("__SSE__");
4165 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
4171 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
4181 Builder.defineMacro("_M_IX86_FP", Twine(2));
4184 Builder.defineMacro("_M_IX86_FP", Twine(1));
4187 Builder.defineMacro("_M_IX86_FP", Twine(0));
4192 // Each case falls through to the previous one here.
4193 switch (MMX3DNowLevel) {
4194 case AMD3DNowAthlon:
4195 Builder.defineMacro("__3dNOW_A__");
4198 Builder.defineMacro("__3dNOW__");
4201 Builder.defineMacro("__MMX__");
4207 if (CPU >= CK_i486) {
4208 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4209 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4210 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4213 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4216 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
4219 bool X86TargetInfo::hasFeature(StringRef Feature) const {
4220 return llvm::StringSwitch<bool>(Feature)
4221 .Case("aes", HasAES)
4222 .Case("avx", SSELevel >= AVX)
4223 .Case("avx2", SSELevel >= AVX2)
4224 .Case("avx512f", SSELevel >= AVX512F)
4225 .Case("avx512cd", HasAVX512CD)
4226 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
4227 .Case("avx512er", HasAVX512ER)
4228 .Case("avx512pf", HasAVX512PF)
4229 .Case("avx512dq", HasAVX512DQ)
4230 .Case("avx512bw", HasAVX512BW)
4231 .Case("avx512vl", HasAVX512VL)
4232 .Case("avx512vbmi", HasAVX512VBMI)
4233 .Case("avx512ifma", HasAVX512IFMA)
4234 .Case("bmi", HasBMI)
4235 .Case("bmi2", HasBMI2)
4236 .Case("clflushopt", HasCLFLUSHOPT)
4237 .Case("clwb", HasCLWB)
4238 .Case("clzero", HasCLZERO)
4239 .Case("cx16", HasCX16)
4240 .Case("f16c", HasF16C)
4241 .Case("fma", HasFMA)
4242 .Case("fma4", XOPLevel >= FMA4)
4243 .Case("fsgsbase", HasFSGSBASE)
4244 .Case("fxsr", HasFXSR)
4245 .Case("lzcnt", HasLZCNT)
4246 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
4247 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
4248 .Case("mmx", MMX3DNowLevel >= MMX)
4249 .Case("movbe", HasMOVBE)
4250 .Case("mpx", HasMPX)
4251 .Case("pclmul", HasPCLMUL)
4252 .Case("pku", HasPKU)
4253 .Case("popcnt", HasPOPCNT)
4254 .Case("prefetchwt1", HasPREFETCHWT1)
4255 .Case("prfchw", HasPRFCHW)
4256 .Case("rdrnd", HasRDRND)
4257 .Case("rdseed", HasRDSEED)
4258 .Case("rtm", HasRTM)
4259 .Case("sgx", HasSGX)
4260 .Case("sha", HasSHA)
4261 .Case("sse", SSELevel >= SSE1)
4262 .Case("sse2", SSELevel >= SSE2)
4263 .Case("sse3", SSELevel >= SSE3)
4264 .Case("ssse3", SSELevel >= SSSE3)
4265 .Case("sse4.1", SSELevel >= SSE41)
4266 .Case("sse4.2", SSELevel >= SSE42)
4267 .Case("sse4a", XOPLevel >= SSE4A)
4268 .Case("tbm", HasTBM)
4269 .Case("lwp", HasLWP)
4271 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
4272 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
4273 .Case("xop", XOPLevel >= XOP)
4274 .Case("xsave", HasXSAVE)
4275 .Case("xsavec", HasXSAVEC)
4276 .Case("xsaves", HasXSAVES)
4277 .Case("xsaveopt", HasXSAVEOPT)
4281 // We can't use a generic validation scheme for the features accepted here
4282 // versus subtarget features accepted in the target attribute because the
4283 // bitfield structure that's initialized in the runtime only supports the
4284 // below currently rather than the full range of subtarget features. (See
4285 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
4286 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
4287 return llvm::StringSwitch<bool>(FeatureStr)
4290 .Case("popcnt", true)
4294 .Case("ssse3", true)
4295 .Case("sse4.1", true)
4296 .Case("sse4.2", true)
4299 .Case("sse4a", true)
4303 .Case("avx512f", true)
4307 .Case("pclmul", true)
4308 .Case("avx512vl", true)
4309 .Case("avx512bw", true)
4310 .Case("avx512dq", true)
4311 .Case("avx512cd", true)
4312 .Case("avx512vpopcntdq", true)
4313 .Case("avx512er", true)
4314 .Case("avx512pf", true)
4315 .Case("avx512vbmi", true)
4316 .Case("avx512ifma", true)
4321 X86TargetInfo::validateAsmConstraint(const char *&Name,
4322 TargetInfo::ConstraintInfo &Info) const {
4324 default: return false;
4325 // Constant constraints.
4326 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
4328 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
4329 // x86_64 instructions.
4331 Info.setRequiresImmediate();
4334 Info.setRequiresImmediate(0, 31);
4337 Info.setRequiresImmediate(0, 63);
4340 Info.setRequiresImmediate(-128, 127);
4343 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
4346 Info.setRequiresImmediate(0, 3);
4349 Info.setRequiresImmediate(0, 255);
4352 Info.setRequiresImmediate(0, 127);
4354 // Register constraints.
4355 case 'Y': // 'Y' is the first character for several 2-character constraints.
4356 // Shift the pointer to the second character of the constraint.
4361 case '0': // First SSE register.
4362 case 't': // Any SSE register, when SSE2 is enabled.
4363 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
4364 case 'm': // Any MMX register, when inter-unit moves enabled.
4365 case 'k': // AVX512 arch mask registers: k1-k7.
4366 Info.setAllowsRegister();
4369 case 'f': // Any x87 floating point stack register.
4370 // Constraint 'f' cannot be used for output operands.
4371 if (Info.ConstraintStr[0] == '=')
4373 Info.setAllowsRegister();
4381 case 'A': // edx:eax.
4382 case 't': // Top of floating point stack.
4383 case 'u': // Second from top of floating point stack.
4384 case 'q': // Any register accessible as [r]l: a, b, c, and d.
4385 case 'y': // Any MMX register.
4386 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
4387 case 'x': // Any SSE register.
4388 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
4389 // for intermideate k reg operations).
4390 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
4391 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
4392 case 'l': // "Index" registers: any general register that can be used as an
4393 // index in a base+index memory access.
4394 Info.setAllowsRegister();
4396 // Floating point constant constraints.
4397 case 'C': // SSE floating point constant.
4398 case 'G': // x87 floating point constant.
4403 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
4404 unsigned Size) const {
4405 // Strip off constraint modifiers.
4406 while (Constraint[0] == '=' ||
4407 Constraint[0] == '+' ||
4408 Constraint[0] == '&')
4409 Constraint = Constraint.substr(1);
4411 return validateOperandSize(Constraint, Size);
4414 bool X86TargetInfo::validateInputSize(StringRef Constraint,
4415 unsigned Size) const {
4416 return validateOperandSize(Constraint, Size);
4419 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
4420 unsigned Size) const {
4421 switch (Constraint[0]) {
4424 // Registers k0-k7 (AVX512) size limit is 64 bit.
4433 if (SSELevel >= AVX512F)
4434 // 512-bit zmm registers can be used if target supports AVX512F.
4435 return Size <= 512U;
4436 else if (SSELevel >= AVX)
4437 // 256-bit ymm registers can be used if target supports AVX.
4438 return Size <= 256U;
4439 return Size <= 128U;
4441 // 'Y' is the first character for several 2-character constraints.
4442 switch (Constraint[1]) {
4445 // 'Ym' is synonymous with 'y'.
4450 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
4451 if (SSELevel >= AVX512F)
4452 return Size <= 512U;
4453 else if (SSELevel >= AVX)
4454 return Size <= 256U;
4455 return SSELevel >= SSE2 && Size <= 128U;
4464 X86TargetInfo::convertConstraint(const char *&Constraint) const {
4465 switch (*Constraint) {
4466 case 'a': return std::string("{ax}");
4467 case 'b': return std::string("{bx}");
4468 case 'c': return std::string("{cx}");
4469 case 'd': return std::string("{dx}");
4470 case 'S': return std::string("{si}");
4471 case 'D': return std::string("{di}");
4472 case 'p': // address
4473 return std::string("im");
4474 case 't': // top of floating point stack.
4475 return std::string("{st}");
4476 case 'u': // second from top of floating point stack.
4477 return std::string("{st(1)}"); // second from top of floating point stack.
4479 switch (Constraint[1]) {
4481 // Break from inner switch and fall through (copy single char),
4482 // continue parsing after copying the current constraint into
4483 // the return string.
4486 // "^" hints llvm that this is a 2 letter constraint.
4487 // "Constraint++" is used to promote the string iterator
4488 // to the next constraint.
4489 return std::string("^") + std::string(Constraint++, 2);
4493 return std::string(1, *Constraint);
4497 // X86-32 generic target
4498 class X86_32TargetInfo : public X86TargetInfo {
4500 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4501 : X86TargetInfo(Triple, Opts) {
4502 DoubleAlign = LongLongAlign = 32;
4503 LongDoubleWidth = 96;
4504 LongDoubleAlign = 32;
4505 SuitableAlign = 128;
4506 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128");
4507 SizeType = UnsignedInt;
4508 PtrDiffType = SignedInt;
4509 IntPtrType = SignedInt;
4512 // Use fpret for all types.
4513 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
4514 (1 << TargetInfo::Double) |
4515 (1 << TargetInfo::LongDouble));
4517 // x86-32 has atomics up to 8 bytes
4518 // FIXME: Check that we actually have cmpxchg8b before setting
4519 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
4520 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4522 BuiltinVaListKind getBuiltinVaListKind() const override {
4523 return TargetInfo::CharPtrBuiltinVaList;
4526 int getEHDataRegisterNumber(unsigned RegNo) const override {
4527 if (RegNo == 0) return 0;
4528 if (RegNo == 1) return 2;
4531 bool validateOperandSize(StringRef Constraint,
4532 unsigned Size) const override {
4533 switch (Constraint[0]) {
4549 return X86TargetInfo::validateOperandSize(Constraint, Size);
4551 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4552 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
4553 Builtin::FirstTSBuiltin + 1);
4557 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
4559 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4560 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
4562 unsigned getFloatEvalMethod() const override {
4563 unsigned Major, Minor, Micro;
4564 getTriple().getOSVersion(Major, Minor, Micro);
4565 // New NetBSD uses the default rounding mode.
4566 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
4567 return X86_32TargetInfo::getFloatEvalMethod();
4568 // NetBSD before 6.99.26 defaults to "double" rounding.
4573 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
4575 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4576 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4577 SizeType = UnsignedLong;
4578 IntPtrType = SignedLong;
4579 PtrDiffType = SignedLong;
4583 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
4585 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4586 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4587 SizeType = UnsignedLong;
4588 IntPtrType = SignedLong;
4589 PtrDiffType = SignedLong;
4593 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
4595 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4596 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4597 LongDoubleWidth = 128;
4598 LongDoubleAlign = 128;
4599 SuitableAlign = 128;
4600 MaxVectorAlign = 256;
4601 // The watchOS simulator uses the builtin bool type for Objective-C.
4602 llvm::Triple T = llvm::Triple(Triple);
4604 UseSignedCharForObjCBool = false;
4605 SizeType = UnsignedLong;
4606 IntPtrType = SignedLong;
4607 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128");
4608 HasAlignMac68kSupport = true;
4611 bool handleTargetFeatures(std::vector<std::string> &Features,
4612 DiagnosticsEngine &Diags) override {
4613 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
4616 // We now know the features we have: we can decide how to align vectors.
4618 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4623 // x86-32 Windows target
4624 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
4626 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4627 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4628 WCharType = UnsignedShort;
4629 DoubleAlign = LongLongAlign = 64;
4631 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4632 resetDataLayout(IsWinCOFF
4633 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
4634 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4636 void getTargetDefines(const LangOptions &Opts,
4637 MacroBuilder &Builder) const override {
4638 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4642 // x86-32 Windows Visual Studio target
4643 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
4645 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
4646 const TargetOptions &Opts)
4647 : WindowsX86_32TargetInfo(Triple, Opts) {
4648 LongDoubleWidth = LongDoubleAlign = 64;
4649 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4651 void getTargetDefines(const LangOptions &Opts,
4652 MacroBuilder &Builder) const override {
4653 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4654 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
4655 // The value of the following reflects processor type.
4656 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
4657 // We lost the original triple, so we use the default.
4658 Builder.defineMacro("_M_IX86", "600");
4662 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4663 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
4664 // supports __declspec natively under -fms-extensions, but we define a no-op
4665 // __declspec macro anyway for pre-processor compatibility.
4666 if (Opts.MicrosoftExt)
4667 Builder.defineMacro("__declspec", "__declspec");
4669 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
4671 if (!Opts.MicrosoftExt) {
4672 // Provide macros for all the calling convention keywords. Provide both
4673 // single and double underscore prefixed variants. These are available on
4674 // x64 as well as x86, even though they have no effect.
4675 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
4676 for (const char *CC : CCs) {
4677 std::string GCCSpelling = "__attribute__((__";
4679 GCCSpelling += "__))";
4680 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
4681 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
4686 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
4687 Builder.defineMacro("__MSVCRT__");
4688 Builder.defineMacro("__MINGW32__");
4689 addCygMingDefines(Opts, Builder);
4692 // x86-32 MinGW target
4693 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
4695 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4696 : WindowsX86_32TargetInfo(Triple, Opts) {
4699 void getTargetDefines(const LangOptions &Opts,
4700 MacroBuilder &Builder) const override {
4701 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
4702 DefineStd(Builder, "WIN32", Opts);
4703 DefineStd(Builder, "WINNT", Opts);
4704 Builder.defineMacro("_X86_");
4705 addMinGWDefines(Opts, Builder);
4709 // x86-32 Cygwin target
4710 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
4712 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4713 : X86_32TargetInfo(Triple, Opts) {
4714 WCharType = UnsignedShort;
4715 DoubleAlign = LongLongAlign = 64;
4716 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32");
4718 void getTargetDefines(const LangOptions &Opts,
4719 MacroBuilder &Builder) const override {
4720 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4721 Builder.defineMacro("_X86_");
4722 Builder.defineMacro("__CYGWIN__");
4723 Builder.defineMacro("__CYGWIN32__");
4724 addCygMingDefines(Opts, Builder);
4725 DefineStd(Builder, "unix", Opts);
4727 Builder.defineMacro("_GNU_SOURCE");
4731 // x86-32 Haiku target
4732 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> {
4734 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4735 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {
4737 void getTargetDefines(const LangOptions &Opts,
4738 MacroBuilder &Builder) const override {
4739 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
4740 Builder.defineMacro("__INTEL__");
4744 // X86-32 MCU target
4745 class MCUX86_32TargetInfo : public X86_32TargetInfo {
4747 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4748 : X86_32TargetInfo(Triple, Opts) {
4749 LongDoubleWidth = 64;
4750 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4751 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32");
4752 WIntType = UnsignedInt;
4755 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4756 // On MCU we support only C calling convention.
4757 return CC == CC_C ? CCCR_OK : CCCR_Warning;
4760 void getTargetDefines(const LangOptions &Opts,
4761 MacroBuilder &Builder) const override {
4762 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4763 Builder.defineMacro("__iamcu");
4764 Builder.defineMacro("__iamcu__");
4767 bool allowsLargerPreferedTypeAlignment() const override {
4773 template<typename Target>
4774 class RTEMSTargetInfo : public OSTargetInfo<Target> {
4776 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4777 MacroBuilder &Builder) const override {
4778 // RTEMS defines; list based off of gcc output
4780 Builder.defineMacro("__rtems__");
4781 Builder.defineMacro("__ELF__");
4785 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4786 : OSTargetInfo<Target>(Triple, Opts) {
4787 switch (Triple.getArch()) {
4789 case llvm::Triple::x86:
4790 // this->MCountName = ".mcount";
4792 case llvm::Triple::mips:
4793 case llvm::Triple::mipsel:
4794 case llvm::Triple::ppc:
4795 case llvm::Triple::ppc64:
4796 case llvm::Triple::ppc64le:
4797 // this->MCountName = "_mcount";
4799 case llvm::Triple::arm:
4800 // this->MCountName = "__mcount";
4806 // x86-32 RTEMS target
4807 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
4809 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4810 : X86_32TargetInfo(Triple, Opts) {
4811 SizeType = UnsignedLong;
4812 IntPtrType = SignedLong;
4813 PtrDiffType = SignedLong;
4815 void getTargetDefines(const LangOptions &Opts,
4816 MacroBuilder &Builder) const override {
4817 X86_32TargetInfo::getTargetDefines(Opts, Builder);
4818 Builder.defineMacro("__INTEL__");
4819 Builder.defineMacro("__rtems__");
4823 // x86-64 generic target
4824 class X86_64TargetInfo : public X86TargetInfo {
4826 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4827 : X86TargetInfo(Triple, Opts) {
4828 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
4830 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
4831 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
4832 LongDoubleWidth = 128;
4833 LongDoubleAlign = 128;
4834 LargeArrayMinWidth = 128;
4835 LargeArrayAlign = 128;
4836 SuitableAlign = 128;
4837 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
4838 PtrDiffType = IsX32 ? SignedInt : SignedLong;
4839 IntPtrType = IsX32 ? SignedInt : SignedLong;
4840 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
4841 Int64Type = IsX32 ? SignedLongLong : SignedLong;
4844 // Pointers are 32-bit in x32.
4845 resetDataLayout(IsX32
4846 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
4847 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4848 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128");
4850 // Use fpret only for long double.
4851 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4853 // Use fp2ret for _Complex long double.
4854 ComplexLongDoubleUsesFP2Ret = true;
4856 // Make __builtin_ms_va_list available.
4857 HasBuiltinMSVaList = true;
4859 // x86-64 has atomics up to 16 bytes.
4860 MaxAtomicPromoteWidth = 128;
4861 MaxAtomicInlineWidth = 128;
4863 BuiltinVaListKind getBuiltinVaListKind() const override {
4864 return TargetInfo::X86_64ABIBuiltinVaList;
4867 int getEHDataRegisterNumber(unsigned RegNo) const override {
4868 if (RegNo == 0) return 0;
4869 if (RegNo == 1) return 1;
4873 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4877 case CC_X86VectorCall:
4878 case CC_IntelOclBicc:
4879 case CC_X86_64Win64:
4880 case CC_PreserveMost:
4881 case CC_PreserveAll:
4883 case CC_OpenCLKernel:
4886 return CCCR_Warning;
4890 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4894 // for x32 we need it here explicitly
4895 bool hasInt128Type() const override { return true; }
4896 unsigned getUnwindWordWidth() const override { return 64; }
4897 unsigned getRegisterWidth() const override { return 64; }
4899 bool validateGlobalRegisterVariable(StringRef RegName,
4901 bool &HasSizeMismatch) const override {
4902 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4904 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4905 // Check that the register size is 64-bit.
4906 HasSizeMismatch = RegSize != 64;
4910 // Check if the register is a 32-bit register the backend can handle.
4911 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4914 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4915 return llvm::makeArrayRef(BuiltinInfoX86,
4916 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
4920 // x86-64 Windows target
4921 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4923 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4924 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
4925 WCharType = UnsignedShort;
4926 LongWidth = LongAlign = 32;
4927 DoubleAlign = LongLongAlign = 64;
4928 IntMaxType = SignedLongLong;
4929 Int64Type = SignedLongLong;
4930 SizeType = UnsignedLongLong;
4931 PtrDiffType = SignedLongLong;
4932 IntPtrType = SignedLongLong;
4935 void getTargetDefines(const LangOptions &Opts,
4936 MacroBuilder &Builder) const override {
4937 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4938 Builder.defineMacro("_WIN64");
4941 BuiltinVaListKind getBuiltinVaListKind() const override {
4942 return TargetInfo::CharPtrBuiltinVaList;
4945 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4948 case CC_X86ThisCall:
4949 case CC_X86FastCall:
4952 case CC_X86VectorCall:
4953 case CC_IntelOclBicc:
4957 case CC_OpenCLKernel:
4960 return CCCR_Warning;
4965 // x86-64 Windows Visual Studio target
4966 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4968 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
4969 const TargetOptions &Opts)
4970 : WindowsX86_64TargetInfo(Triple, Opts) {
4971 LongDoubleWidth = LongDoubleAlign = 64;
4972 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
4974 void getTargetDefines(const LangOptions &Opts,
4975 MacroBuilder &Builder) const override {
4976 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4977 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4978 Builder.defineMacro("_M_X64", "100");
4979 Builder.defineMacro("_M_AMD64", "100");
4983 // x86-64 MinGW target
4984 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4986 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
4987 : WindowsX86_64TargetInfo(Triple, Opts) {
4988 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4989 // with x86 FP ops. Weird.
4990 LongDoubleWidth = LongDoubleAlign = 128;
4991 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
4995 void getTargetDefines(const LangOptions &Opts,
4996 MacroBuilder &Builder) const override {
4997 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4998 DefineStd(Builder, "WIN64", Opts);
4999 Builder.defineMacro("__MINGW64__");
5000 addMinGWDefines(Opts, Builder);
5002 // GCC defines this macro when it is using __gxx_personality_seh0.
5003 if (!Opts.SjLjExceptions)
5004 Builder.defineMacro("__SEH__");
5008 // x86-64 Cygwin target
5009 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
5011 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5012 : X86_64TargetInfo(Triple, Opts) {
5013 TLSSupported = false;
5014 WCharType = UnsignedShort;
5016 void getTargetDefines(const LangOptions &Opts,
5017 MacroBuilder &Builder) const override {
5018 X86_64TargetInfo::getTargetDefines(Opts, Builder);
5019 Builder.defineMacro("__x86_64__");
5020 Builder.defineMacro("__CYGWIN__");
5021 Builder.defineMacro("__CYGWIN64__");
5022 addCygMingDefines(Opts, Builder);
5023 DefineStd(Builder, "unix", Opts);
5025 Builder.defineMacro("_GNU_SOURCE");
5027 // GCC defines this macro when it is using __gxx_personality_seh0.
5028 if (!Opts.SjLjExceptions)
5029 Builder.defineMacro("__SEH__");
5033 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
5035 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5036 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5037 Int64Type = SignedLongLong;
5038 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
5039 llvm::Triple T = llvm::Triple(Triple);
5041 UseSignedCharForObjCBool = false;
5042 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128");
5045 bool handleTargetFeatures(std::vector<std::string> &Features,
5046 DiagnosticsEngine &Diags) override {
5047 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
5050 // We now know the features we have: we can decide how to align vectors.
5052 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
5057 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
5059 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5060 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5061 IntMaxType = SignedLongLong;
5062 Int64Type = SignedLongLong;
5066 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
5068 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5069 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) {
5070 IntMaxType = SignedLongLong;
5071 Int64Type = SignedLongLong;
5075 class ARMTargetInfo : public TargetInfo {
5076 // Possible FPU choices.
5085 // Possible HWDiv features.
5087 HWDivThumb = (1 << 0),
5091 static bool FPUModeIsVFP(FPUMode Mode) {
5092 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
5095 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5096 static const char * const GCCRegNames[];
5098 std::string ABI, CPU;
5100 StringRef CPUProfile;
5110 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
5111 unsigned ArchProfile;
5112 unsigned ArchVersion;
5116 unsigned IsAAPCS : 1;
5119 // Initialized via features.
5120 unsigned SoftFloat : 1;
5121 unsigned SoftFloatABI : 1;
5124 unsigned Crypto : 1;
5126 unsigned Unaligned : 1;
5129 LDREX_B = (1 << 0), /// byte (8-bit)
5130 LDREX_H = (1 << 1), /// half (16-bit)
5131 LDREX_W = (1 << 2), /// word (32-bit)
5132 LDREX_D = (1 << 3), /// double (64-bit)
5137 // ACLE 6.5.1 Hardware floating point
5139 HW_FP_HP = (1 << 1), /// half (16-bit)
5140 HW_FP_SP = (1 << 2), /// single (32-bit)
5141 HW_FP_DP = (1 << 3), /// double (64-bit)
5145 static const Builtin::Info BuiltinInfo[];
5147 void setABIAAPCS() {
5150 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5151 const llvm::Triple &T = getTriple();
5153 // size_t is unsigned long on MachO-derived environments, NetBSD,
5154 // OpenBSD and Bitrig.
5155 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
5156 T.getOS() == llvm::Triple::OpenBSD ||
5157 T.getOS() == llvm::Triple::Bitrig)
5158 SizeType = UnsignedLong;
5160 SizeType = UnsignedInt;
5162 switch (T.getOS()) {
5163 case llvm::Triple::NetBSD:
5164 case llvm::Triple::OpenBSD:
5165 WCharType = SignedInt;
5167 case llvm::Triple::Win32:
5168 WCharType = UnsignedShort;
5170 case llvm::Triple::Linux:
5172 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
5173 WCharType = UnsignedInt;
5177 UseBitFieldTypeAlignment = true;
5179 ZeroLengthBitfieldBoundary = 0;
5181 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
5182 // so set preferred for small types to 32.
5183 if (T.isOSBinFormatMachO()) {
5184 resetDataLayout(BigEndian
5185 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5186 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5187 } else if (T.isOSWindows()) {
5188 assert(!BigEndian && "Windows on ARM does not support big endian");
5197 } else if (T.isOSNaCl()) {
5198 assert(!BigEndian && "NaCl on ARM does not support big endian");
5199 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
5201 resetDataLayout(BigEndian
5202 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
5203 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
5206 // FIXME: Enumerated types are variable width in straight AAPCS.
5209 void setABIAPCS(bool IsAAPCS16) {
5210 const llvm::Triple &T = getTriple();
5215 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
5217 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
5219 // size_t is unsigned int on FreeBSD.
5220 if (T.getOS() == llvm::Triple::FreeBSD)
5221 SizeType = UnsignedInt;
5223 SizeType = UnsignedLong;
5225 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
5226 WCharType = SignedInt;
5228 // Do not respect the alignment of bit-field types when laying out
5229 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
5230 UseBitFieldTypeAlignment = false;
5232 /// gcc forces the alignment to 4 bytes, regardless of the type of the
5233 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
5235 ZeroLengthBitfieldBoundary = 32;
5237 if (T.isOSBinFormatMachO() && IsAAPCS16) {
5238 assert(!BigEndian && "AAPCS16 does not support big-endian");
5239 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
5240 } else if (T.isOSBinFormatMachO())
5243 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5244 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5248 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
5249 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
5251 // FIXME: Override "preferred align" for double and long long.
5254 void setArchInfo() {
5255 StringRef ArchName = getTriple().getArchName();
5257 ArchISA = llvm::ARM::parseArchISA(ArchName);
5258 CPU = llvm::ARM::getDefaultCPU(ArchName);
5259 unsigned AK = llvm::ARM::parseArch(ArchName);
5260 if (AK != llvm::ARM::AK_INVALID)
5262 setArchInfo(ArchKind);
5265 void setArchInfo(unsigned Kind) {
5268 // cache TargetParser info
5270 SubArch = llvm::ARM::getSubArch(ArchKind);
5271 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
5272 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
5274 // cache CPU related strings
5275 CPUAttr = getCPUAttr();
5276 CPUProfile = getCPUProfile();
5280 // when triple does not specify a sub arch,
5281 // then we are not using inline atomics
5282 bool ShouldUseInlineAtomic =
5283 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
5284 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
5285 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
5286 if (ArchProfile == llvm::ARM::PK_M) {
5287 MaxAtomicPromoteWidth = 32;
5288 if (ShouldUseInlineAtomic)
5289 MaxAtomicInlineWidth = 32;
5292 MaxAtomicPromoteWidth = 64;
5293 if (ShouldUseInlineAtomic)
5294 MaxAtomicInlineWidth = 64;
5298 bool isThumb() const {
5299 return (ArchISA == llvm::ARM::IK_THUMB);
5302 bool supportsThumb() const {
5303 return CPUAttr.count('T') || ArchVersion >= 6;
5306 bool supportsThumb2() const {
5307 return CPUAttr.equals("6T2") ||
5308 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
5311 StringRef getCPUAttr() const {
5312 // For most sub-arches, the build attribute CPU name is enough.
5313 // For Cortex variants, it's slightly different.
5316 return llvm::ARM::getCPUAttr(ArchKind);
5317 case llvm::ARM::AK_ARMV6M:
5319 case llvm::ARM::AK_ARMV7S:
5321 case llvm::ARM::AK_ARMV7A:
5323 case llvm::ARM::AK_ARMV7R:
5325 case llvm::ARM::AK_ARMV7M:
5327 case llvm::ARM::AK_ARMV7EM:
5329 case llvm::ARM::AK_ARMV7VE:
5331 case llvm::ARM::AK_ARMV8A:
5333 case llvm::ARM::AK_ARMV8_1A:
5335 case llvm::ARM::AK_ARMV8_2A:
5337 case llvm::ARM::AK_ARMV8MBaseline:
5339 case llvm::ARM::AK_ARMV8MMainline:
5341 case llvm::ARM::AK_ARMV8R:
5346 StringRef getCPUProfile() const {
5347 switch(ArchProfile) {
5348 case llvm::ARM::PK_A:
5350 case llvm::ARM::PK_R:
5352 case llvm::ARM::PK_M:
5360 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
5361 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
5364 switch (getTriple().getOS()) {
5365 case llvm::Triple::NetBSD:
5366 case llvm::Triple::OpenBSD:
5367 PtrDiffType = SignedLong;
5370 PtrDiffType = SignedInt;
5374 // Cache arch related info.
5377 // {} in inline assembly are neon specifiers, not assembly variant
5379 NoAsmVariants = true;
5381 // FIXME: This duplicates code from the driver that sets the -target-abi
5382 // option - this code is used if -target-abi isn't passed and should
5383 // be unified in some way.
5384 if (Triple.isOSBinFormatMachO()) {
5385 // The backend is hardwired to assume AAPCS for M-class processors, ensure
5386 // the frontend matches that.
5387 if (Triple.getEnvironment() == llvm::Triple::EABI ||
5388 Triple.getOS() == llvm::Triple::UnknownOS ||
5389 ArchProfile == llvm::ARM::PK_M) {
5391 } else if (Triple.isWatchABI()) {
5396 } else if (Triple.isOSWindows()) {
5397 // FIXME: this is invalid for WindowsCE
5400 // Select the default based on the platform.
5401 switch (Triple.getEnvironment()) {
5402 case llvm::Triple::Android:
5403 case llvm::Triple::GNUEABI:
5404 case llvm::Triple::GNUEABIHF:
5405 case llvm::Triple::MuslEABI:
5406 case llvm::Triple::MuslEABIHF:
5407 setABI("aapcs-linux");
5409 case llvm::Triple::EABIHF:
5410 case llvm::Triple::EABI:
5413 case llvm::Triple::GNU:
5417 if (Triple.getOS() == llvm::Triple::NetBSD)
5419 else if (Triple.getOS() == llvm::Triple::OpenBSD)
5420 setABI("aapcs-linux");
5427 // ARM targets default to using the ARM C++ ABI.
5428 TheCXXABI.set(TargetCXXABI::GenericARM);
5430 // ARM has atomics up to 8 bytes
5433 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
5434 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
5435 MaxVectorAlign = 64;
5437 // Do force alignment of members that follow zero length bitfields. If
5438 // the alignment of the zero-length bitfield is greater than the member
5439 // that follows it, `bar', `bar' will be aligned as the type of the
5440 // zero length bitfield.
5441 UseZeroLengthBitfieldAlignment = true;
5443 if (Triple.getOS() == llvm::Triple::Linux ||
5444 Triple.getOS() == llvm::Triple::UnknownOS)
5446 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount";
5449 StringRef getABI() const override { return ABI; }
5451 bool setABI(const std::string &Name) override {
5454 // The defaults (above) are for AAPCS, check if we need to change them.
5456 // FIXME: We need support for -meabi... we could just mangle it into the
5458 if (Name == "apcs-gnu" || Name == "aapcs16") {
5459 setABIAPCS(Name == "aapcs16");
5462 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
5469 // FIXME: This should be based on Arch attributes, not CPU names.
5471 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5473 const std::vector<std::string> &FeaturesVec) const override {
5475 std::vector<StringRef> TargetFeatures;
5476 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
5478 // get default FPU features
5479 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
5480 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
5482 // get default Extension features
5483 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
5484 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
5486 for (auto Feature : TargetFeatures)
5487 if (Feature[0] == '+')
5488 Features[Feature.drop_front(1)] = true;
5490 // Enable or disable thumb-mode explicitly per function to enable mixed
5491 // ARM and Thumb code generation.
5493 Features["thumb-mode"] = true;
5495 Features["thumb-mode"] = false;
5497 // Convert user-provided arm and thumb GNU target attributes to
5498 // [-|+]thumb-mode target features respectively.
5499 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec);
5500 for (auto &Feature : UpdatedFeaturesVec) {
5501 if (Feature.compare("+arm") == 0)
5502 Feature = "-thumb-mode";
5503 else if (Feature.compare("+thumb") == 0)
5504 Feature = "+thumb-mode";
5507 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
5510 bool handleTargetFeatures(std::vector<std::string> &Features,
5511 DiagnosticsEngine &Diags) override {
5517 SoftFloat = SoftFloatABI = false;
5520 // This does not diagnose illegal cases like having both
5521 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
5522 uint32_t HW_FP_remove = 0;
5523 for (const auto &Feature : Features) {
5524 if (Feature == "+soft-float") {
5526 } else if (Feature == "+soft-float-abi") {
5527 SoftFloatABI = true;
5528 } else if (Feature == "+vfp2") {
5530 HW_FP |= HW_FP_SP | HW_FP_DP;
5531 } else if (Feature == "+vfp3") {
5533 HW_FP |= HW_FP_SP | HW_FP_DP;
5534 } else if (Feature == "+vfp4") {
5536 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5537 } else if (Feature == "+fp-armv8") {
5539 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
5540 } else if (Feature == "+neon") {
5542 HW_FP |= HW_FP_SP | HW_FP_DP;
5543 } else if (Feature == "+hwdiv") {
5544 HWDiv |= HWDivThumb;
5545 } else if (Feature == "+hwdiv-arm") {
5547 } else if (Feature == "+crc") {
5549 } else if (Feature == "+crypto") {
5551 } else if (Feature == "+dsp") {
5553 } else if (Feature == "+fp-only-sp") {
5554 HW_FP_remove |= HW_FP_DP;
5555 } else if (Feature == "+strict-align") {
5557 } else if (Feature == "+fp16") {
5561 HW_FP &= ~HW_FP_remove;
5563 switch (ArchVersion) {
5565 if (ArchProfile == llvm::ARM::PK_M)
5567 else if (ArchKind == llvm::ARM::AK_ARMV6K)
5568 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5573 if (ArchProfile == llvm::ARM::PK_M)
5574 LDREX = LDREX_W | LDREX_H | LDREX_B ;
5576 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5579 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
5582 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
5583 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
5587 if (FPMath == FP_Neon)
5588 Features.push_back("+neonfp");
5589 else if (FPMath == FP_VFP)
5590 Features.push_back("-neonfp");
5592 // Remove front-end specific options which the backend handles differently.
5594 std::find(Features.begin(), Features.end(), "+soft-float-abi");
5595 if (Feature != Features.end())
5596 Features.erase(Feature);
5601 bool hasFeature(StringRef Feature) const override {
5602 return llvm::StringSwitch<bool>(Feature)
5604 .Case("aarch32", true)
5605 .Case("softfloat", SoftFloat)
5606 .Case("thumb", isThumb())
5607 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
5608 .Case("vfp", FPU && !SoftFloat)
5609 .Case("hwdiv", HWDiv & HWDivThumb)
5610 .Case("hwdiv-arm", HWDiv & HWDivARM)
5614 bool setCPU(const std::string &Name) override {
5615 if (Name != "generic")
5616 setArchInfo(llvm::ARM::parseCPUArch(Name));
5618 if (ArchKind == llvm::ARM::AK_INVALID)
5625 bool setFPMath(StringRef Name) override;
5627 void getTargetDefinesARMV81A(const LangOptions &Opts,
5628 MacroBuilder &Builder) const {
5629 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5632 void getTargetDefinesARMV82A(const LangOptions &Opts,
5633 MacroBuilder &Builder) const {
5634 // Also include the ARMv8.1-A defines
5635 getTargetDefinesARMV81A(Opts, Builder);
5638 void getTargetDefines(const LangOptions &Opts,
5639 MacroBuilder &Builder) const override {
5640 // Target identification.
5641 Builder.defineMacro("__arm");
5642 Builder.defineMacro("__arm__");
5643 // For bare-metal none-eabi.
5644 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
5645 (getTriple().getEnvironment() == llvm::Triple::EABI ||
5646 getTriple().getEnvironment() == llvm::Triple::EABIHF))
5647 Builder.defineMacro("__ELF__");
5650 // Target properties.
5651 Builder.defineMacro("__REGISTER_PREFIX__", "");
5653 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
5654 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
5655 if (getTriple().isWatchABI())
5656 Builder.defineMacro("__ARM_ARCH_7K__", "2");
5658 if (!CPUAttr.empty())
5659 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
5661 // ACLE 6.4.1 ARM/Thumb instruction set architecture
5662 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
5663 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
5665 if (ArchVersion >= 8) {
5666 // ACLE 6.5.7 Crypto Extension
5668 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5669 // ACLE 6.5.8 CRC32 Extension
5671 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5672 // ACLE 6.5.10 Numeric Maximum and Minimum
5673 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5674 // ACLE 6.5.9 Directed Rounding
5675 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5678 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
5679 // is not defined for the M-profile.
5680 // NOTE that the default profile is assumed to be 'A'
5681 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
5682 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
5684 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
5685 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
5686 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
5687 // v7 and v8 architectures excluding v8-M Baseline.
5688 if (supportsThumb2())
5689 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
5690 else if (supportsThumb())
5691 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
5693 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
5694 // instruction set such as ARM or Thumb.
5695 Builder.defineMacro("__ARM_32BIT_STATE", "1");
5697 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
5699 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
5700 if (!CPUProfile.empty())
5701 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
5703 // ACLE 6.4.3 Unaligned access supported in hardware
5705 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5707 // ACLE 6.4.4 LDREX/STREX
5709 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
5712 if (ArchVersion == 5 ||
5713 (ArchVersion == 6 && CPUProfile != "M") ||
5715 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5717 // ACLE 6.5.1 Hardware Floating Point
5719 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
5722 Builder.defineMacro("__ARM_ACLE", "200");
5724 // FP16 support (we currently only support IEEE format).
5725 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5726 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5728 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
5729 if (ArchVersion >= 7 && (FPU & VFP4FPU))
5730 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5732 // Subtarget options.
5734 // FIXME: It's more complicated than this and we don't really support
5736 // Windows on ARM does not "support" interworking
5737 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
5738 Builder.defineMacro("__THUMB_INTERWORK__");
5740 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
5741 // Embedded targets on Darwin follow AAPCS, but not EABI.
5742 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
5743 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows())
5744 Builder.defineMacro("__ARM_EABI__");
5745 Builder.defineMacro("__ARM_PCS", "1");
5748 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" ||
5750 Builder.defineMacro("__ARM_PCS_VFP", "1");
5753 Builder.defineMacro("__SOFTFP__");
5755 if (ArchKind == llvm::ARM::AK_XSCALE)
5756 Builder.defineMacro("__XSCALE__");
5759 Builder.defineMacro("__THUMBEL__");
5760 Builder.defineMacro("__thumb__");
5761 if (supportsThumb2())
5762 Builder.defineMacro("__thumb2__");
5765 // ACLE 6.4.9 32-bit SIMD instructions
5766 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
5767 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
5769 // ACLE 6.4.10 Hardware Integer Divide
5770 if (((HWDiv & HWDivThumb) && isThumb()) ||
5771 ((HWDiv & HWDivARM) && !isThumb())) {
5772 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
5773 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
5776 // Note, this is always on in gcc, even though it doesn't make sense.
5777 Builder.defineMacro("__APCS_32__");
5779 if (FPUModeIsVFP((FPUMode) FPU)) {
5780 Builder.defineMacro("__VFP_FP__");
5782 Builder.defineMacro("__ARM_VFPV2__");
5784 Builder.defineMacro("__ARM_VFPV3__");
5786 Builder.defineMacro("__ARM_VFPV4__");
5788 Builder.defineMacro("__ARM_FPV5__");
5791 // This only gets set when Neon instructions are actually available, unlike
5792 // the VFP define, hence the soft float and arch check. This is subtly
5793 // different from gcc, we follow the intent which was that it should be set
5794 // when Neon instructions are actually available.
5795 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
5796 Builder.defineMacro("__ARM_NEON", "1");
5797 Builder.defineMacro("__ARM_NEON__");
5798 // current AArch32 NEON implementations do not support double-precision
5799 // floating-point even when it is present in VFP.
5800 Builder.defineMacro("__ARM_NEON_FP",
5801 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
5804 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
5805 Opts.ShortWChar ? "2" : "4");
5807 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5808 Opts.ShortEnums ? "1" : "4");
5810 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
5811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5817 // ACLE 6.4.7 DSP instructions
5819 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
5822 // ACLE 6.4.8 Saturation instructions
5824 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
5825 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
5829 // ACLE 6.4.6 Q (saturation) flag
5831 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
5833 if (Opts.UnsafeFPMath)
5834 Builder.defineMacro("__ARM_FP_FAST", "1");
5838 case llvm::ARM::AK_ARMV8_1A:
5839 getTargetDefinesARMV81A(Opts, Builder);
5841 case llvm::ARM::AK_ARMV8_2A:
5842 getTargetDefinesARMV82A(Opts, Builder);
5847 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5848 return llvm::makeArrayRef(BuiltinInfo,
5849 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
5851 bool isCLZForZeroUndef() const override { return false; }
5852 BuiltinVaListKind getBuiltinVaListKind() const override {
5854 ? AAPCSABIBuiltinVaList
5855 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList
5856 : TargetInfo::VoidPtrBuiltinVaList);
5858 ArrayRef<const char *> getGCCRegNames() const override;
5859 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5860 bool validateAsmConstraint(const char *&Name,
5861 TargetInfo::ConstraintInfo &Info) const override {
5866 case 't': // VFP Floating point register single precision
5867 case 'w': // VFP Floating point register double precision
5868 Info.setAllowsRegister();
5877 case 'Q': // A memory address that is a single base register.
5878 Info.setAllowsMemory();
5880 case 'U': // a memory reference...
5882 case 'q': // ...ARMV4 ldrsb
5883 case 'v': // ...VFP load/store (reg+constant offset)
5884 case 'y': // ...iWMMXt load/store
5885 case 't': // address valid for load/store opaque types wider
5887 case 'n': // valid address for Neon doubleword vector load/store
5888 case 'm': // valid address for Neon element and structure load/store
5889 case 's': // valid address for non-offset loads/stores of quad-word
5890 // values in four ARM registers
5891 Info.setAllowsMemory();
5898 std::string convertConstraint(const char *&Constraint) const override {
5900 switch (*Constraint) {
5901 case 'U': // Two-character constraint; add "^" hint for later parsing.
5902 R = std::string("^") + std::string(Constraint, 2);
5905 case 'p': // 'p' should be translated to 'r' by default.
5906 R = std::string("r");
5909 return std::string(1, *Constraint);
5914 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5915 std::string &SuggestedModifier) const override {
5916 bool isOutput = (Constraint[0] == '=');
5917 bool isInOut = (Constraint[0] == '+');
5919 // Strip off constraint modifiers.
5920 while (Constraint[0] == '=' ||
5921 Constraint[0] == '+' ||
5922 Constraint[0] == '&')
5923 Constraint = Constraint.substr(1);
5925 switch (Constraint[0]) {
5930 return (isInOut || isOutput || Size <= 64);
5932 // A register of size 32 cannot fit a vector type.
5940 const char *getClobbers() const override {
5941 // FIXME: Is this really right?
5945 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5950 case CC_OpenCLKernel:
5953 return CCCR_Warning;
5957 int getEHDataRegisterNumber(unsigned RegNo) const override {
5958 if (RegNo == 0) return 0;
5959 if (RegNo == 1) return 1;
5963 bool hasSjLjLowering() const override {
5968 bool ARMTargetInfo::setFPMath(StringRef Name) {
5969 if (Name == "neon") {
5972 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5980 const char * const ARMTargetInfo::GCCRegNames[] = {
5981 // Integer registers
5982 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5983 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5986 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5987 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5988 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5989 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5992 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5993 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5994 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5995 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5998 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5999 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
6002 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
6003 return llvm::makeArrayRef(GCCRegNames);
6006 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
6016 { { "v6", "rfp" }, "r9" },
6017 { { "sl" }, "r10" },
6018 { { "fp" }, "r11" },
6019 { { "ip" }, "r12" },
6020 { { "r13" }, "sp" },
6021 { { "r14" }, "lr" },
6022 { { "r15" }, "pc" },
6023 // The S, D and Q registers overlap, but aren't really aliases; we
6024 // don't want to substitute one of these for a different-sized one.
6027 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
6028 return llvm::makeArrayRef(GCCRegAliases);
6031 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
6032 #define BUILTIN(ID, TYPE, ATTRS) \
6033 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6034 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6035 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6036 #include "clang/Basic/BuiltinsNEON.def"
6038 #define BUILTIN(ID, TYPE, ATTRS) \
6039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6040 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
6041 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
6042 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6043 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6044 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
6045 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE },
6046 #include "clang/Basic/BuiltinsARM.def"
6049 class ARMleTargetInfo : public ARMTargetInfo {
6051 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6052 : ARMTargetInfo(Triple, Opts) {}
6053 void getTargetDefines(const LangOptions &Opts,
6054 MacroBuilder &Builder) const override {
6055 Builder.defineMacro("__ARMEL__");
6056 ARMTargetInfo::getTargetDefines(Opts, Builder);
6060 class ARMbeTargetInfo : public ARMTargetInfo {
6062 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6063 : ARMTargetInfo(Triple, Opts) {}
6064 void getTargetDefines(const LangOptions &Opts,
6065 MacroBuilder &Builder) const override {
6066 Builder.defineMacro("__ARMEB__");
6067 Builder.defineMacro("__ARM_BIG_ENDIAN");
6068 ARMTargetInfo::getTargetDefines(Opts, Builder);
6072 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
6073 const llvm::Triple Triple;
6075 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6076 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
6077 WCharType = UnsignedShort;
6078 SizeType = UnsignedInt;
6080 void getVisualStudioDefines(const LangOptions &Opts,
6081 MacroBuilder &Builder) const {
6082 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
6084 // FIXME: this is invalid for WindowsCE
6085 Builder.defineMacro("_M_ARM_NT", "1");
6086 Builder.defineMacro("_M_ARMT", "_M_ARM");
6087 Builder.defineMacro("_M_THUMB", "_M_ARM");
6089 assert((Triple.getArch() == llvm::Triple::arm ||
6090 Triple.getArch() == llvm::Triple::thumb) &&
6091 "invalid architecture for Windows ARM target info");
6092 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
6093 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
6095 // TODO map the complete set of values
6096 // 31: VFPv3 40: VFPv4
6097 Builder.defineMacro("_M_ARM_FP", "31");
6099 BuiltinVaListKind getBuiltinVaListKind() const override {
6100 return TargetInfo::CharPtrBuiltinVaList;
6102 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6105 case CC_X86ThisCall:
6106 case CC_X86FastCall:
6107 case CC_X86VectorCall:
6110 case CC_OpenCLKernel:
6113 return CCCR_Warning;
6118 // Windows ARM + Itanium C++ ABI Target
6119 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
6121 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,
6122 const TargetOptions &Opts)
6123 : WindowsARMTargetInfo(Triple, Opts) {
6124 TheCXXABI.set(TargetCXXABI::GenericARM);
6127 void getTargetDefines(const LangOptions &Opts,
6128 MacroBuilder &Builder) const override {
6129 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6131 if (Opts.MSVCCompat)
6132 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6136 // Windows ARM, MS (C++) ABI
6137 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
6139 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
6140 const TargetOptions &Opts)
6141 : WindowsARMTargetInfo(Triple, Opts) {
6142 TheCXXABI.set(TargetCXXABI::Microsoft);
6145 void getTargetDefines(const LangOptions &Opts,
6146 MacroBuilder &Builder) const override {
6147 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6148 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
6153 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
6155 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6156 : WindowsARMTargetInfo(Triple, Opts) {
6157 TheCXXABI.set(TargetCXXABI::GenericARM);
6160 void getTargetDefines(const LangOptions &Opts,
6161 MacroBuilder &Builder) const override {
6162 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
6163 DefineStd(Builder, "WIN32", Opts);
6164 DefineStd(Builder, "WINNT", Opts);
6165 Builder.defineMacro("_ARM_");
6166 addMinGWDefines(Opts, Builder);
6170 // ARM Cygwin target
6171 class CygwinARMTargetInfo : public ARMleTargetInfo {
6173 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6174 : ARMleTargetInfo(Triple, Opts) {
6175 TLSSupported = false;
6176 WCharType = UnsignedShort;
6177 DoubleAlign = LongLongAlign = 64;
6178 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
6180 void getTargetDefines(const LangOptions &Opts,
6181 MacroBuilder &Builder) const override {
6182 ARMleTargetInfo::getTargetDefines(Opts, Builder);
6183 Builder.defineMacro("_ARM_");
6184 Builder.defineMacro("__CYGWIN__");
6185 Builder.defineMacro("__CYGWIN32__");
6186 DefineStd(Builder, "unix", Opts);
6188 Builder.defineMacro("_GNU_SOURCE");
6192 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> {
6194 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6195 MacroBuilder &Builder) const override {
6196 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6200 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6201 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
6202 HasAlignMac68kSupport = true;
6203 // iOS always has 64-bit atomic instructions.
6204 // FIXME: This should be based off of the target features in
6206 MaxAtomicInlineWidth = 64;
6208 if (Triple.isWatchABI()) {
6209 // Darwin on iOS uses a variant of the ARM C++ ABI.
6210 TheCXXABI.set(TargetCXXABI::WatchOS);
6212 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
6213 // size_t is long, it's a bit weird for it to be int.
6214 PtrDiffType = SignedLong;
6216 // BOOL should be a real boolean on the new ABI
6217 UseSignedCharForObjCBool = false;
6219 TheCXXABI.set(TargetCXXABI::iOS);
6223 class AArch64TargetInfo : public TargetInfo {
6224 virtual void setDataLayout() = 0;
6225 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6226 static const char *const GCCRegNames[];
6237 unsigned HasFullFP16;
6238 llvm::AArch64::ArchKind ArchKind;
6240 static const Builtin::Info BuiltinInfo[];
6245 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6246 : TargetInfo(Triple), ABI("aapcs") {
6247 if (getTriple().getOS() == llvm::Triple::NetBSD ||
6248 getTriple().getOS() == llvm::Triple::OpenBSD) {
6249 WCharType = SignedInt;
6251 // NetBSD apparently prefers consistency across ARM targets to consistency
6252 // across 64-bit targets.
6253 Int64Type = SignedLongLong;
6254 IntMaxType = SignedLongLong;
6256 WCharType = UnsignedInt;
6257 Int64Type = SignedLong;
6258 IntMaxType = SignedLong;
6261 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6262 MaxVectorAlign = 128;
6263 MaxAtomicInlineWidth = 128;
6264 MaxAtomicPromoteWidth = 128;
6266 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
6267 LongDoubleFormat = &llvm::APFloat::IEEEquad();
6269 // {} in inline assembly are neon specifiers, not assembly variant
6271 NoAsmVariants = true;
6273 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
6274 // contributes to the alignment of the containing aggregate in the same way
6275 // a plain (non bit-field) member of that type would, without exception for
6276 // zero-sized or anonymous bit-fields."
6277 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
6278 UseZeroLengthBitfieldAlignment = true;
6280 // AArch64 targets default to using the ARM C++ ABI.
6281 TheCXXABI.set(TargetCXXABI::GenericAArch64);
6283 if (Triple.getOS() == llvm::Triple::Linux)
6284 this->MCountName = "\01_mcount";
6285 else if (Triple.getOS() == llvm::Triple::UnknownOS)
6286 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount";
6289 StringRef getABI() const override { return ABI; }
6290 bool setABI(const std::string &Name) override {
6291 if (Name != "aapcs" && Name != "darwinpcs")
6298 bool setCPU(const std::string &Name) override {
6299 return Name == "generic" ||
6300 llvm::AArch64::parseCPUArch(Name) !=
6301 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID);
6304 void getTargetDefinesARMV81A(const LangOptions &Opts,
6305 MacroBuilder &Builder) const {
6306 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
6309 void getTargetDefinesARMV82A(const LangOptions &Opts,
6310 MacroBuilder &Builder) const {
6311 // Also include the ARMv8.1 defines
6312 getTargetDefinesARMV81A(Opts, Builder);
6314 if (FPU == NeonMode && HasFullFP16)
6315 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
6318 void getTargetDefines(const LangOptions &Opts,
6319 MacroBuilder &Builder) const override {
6320 // Target identification.
6321 Builder.defineMacro("__aarch64__");
6322 // For bare-metal none-eabi.
6323 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
6324 (getTriple().getEnvironment() == llvm::Triple::EABI ||
6325 getTriple().getEnvironment() == llvm::Triple::EABIHF))
6326 Builder.defineMacro("__ELF__");
6328 // Target properties.
6329 Builder.defineMacro("_LP64");
6330 Builder.defineMacro("__LP64__");
6332 // ACLE predefines. Many can only have one possible value on v8 AArch64.
6333 Builder.defineMacro("__ARM_ACLE", "200");
6334 Builder.defineMacro("__ARM_ARCH", "8");
6335 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
6337 Builder.defineMacro("__ARM_64BIT_STATE", "1");
6338 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
6339 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
6341 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
6342 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
6343 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
6344 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
6345 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
6346 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
6347 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
6349 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
6351 // 0xe implies support for half, single and double precision operations.
6352 Builder.defineMacro("__ARM_FP", "0xE");
6354 // PCS specifies this for SysV variants, which is all we support. Other ABIs
6355 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
6356 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
6357 Builder.defineMacro("__ARM_FP16_ARGS", "1");
6359 if (Opts.UnsafeFPMath)
6360 Builder.defineMacro("__ARM_FP_FAST", "1");
6362 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
6364 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
6365 Opts.ShortEnums ? "1" : "4");
6367 if (FPU == NeonMode) {
6368 Builder.defineMacro("__ARM_NEON", "1");
6369 // 64-bit NEON supports half, single and double precision operations.
6370 Builder.defineMacro("__ARM_NEON_FP", "0xE");
6374 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
6377 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
6380 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
6384 case llvm::AArch64::ArchKind::AK_ARMV8_1A:
6385 getTargetDefinesARMV81A(Opts, Builder);
6387 case llvm::AArch64::ArchKind::AK_ARMV8_2A:
6388 getTargetDefinesARMV82A(Opts, Builder);
6392 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
6393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6399 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6400 return llvm::makeArrayRef(BuiltinInfo,
6401 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
6404 bool hasFeature(StringRef Feature) const override {
6405 return Feature == "aarch64" ||
6406 Feature == "arm64" ||
6408 (Feature == "neon" && FPU == NeonMode);
6411 bool handleTargetFeatures(std::vector<std::string> &Features,
6412 DiagnosticsEngine &Diags) override {
6418 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A;
6420 for (const auto &Feature : Features) {
6421 if (Feature == "+neon")
6423 if (Feature == "+crc")
6425 if (Feature == "+crypto")
6427 if (Feature == "+strict-align")
6429 if (Feature == "+v8.1a")
6430 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A;
6431 if (Feature == "+v8.2a")
6432 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A;
6433 if (Feature == "+fullfp16")
6442 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6446 case CC_PreserveMost:
6447 case CC_PreserveAll:
6448 case CC_OpenCLKernel:
6451 return CCCR_Warning;
6455 bool isCLZForZeroUndef() const override { return false; }
6457 BuiltinVaListKind getBuiltinVaListKind() const override {
6458 return TargetInfo::AArch64ABIBuiltinVaList;
6461 ArrayRef<const char *> getGCCRegNames() const override;
6462 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6464 bool validateAsmConstraint(const char *&Name,
6465 TargetInfo::ConstraintInfo &Info) const override {
6469 case 'w': // Floating point and SIMD registers (V0-V31)
6470 Info.setAllowsRegister();
6472 case 'I': // Constant that can be used with an ADD instruction
6473 case 'J': // Constant that can be used with a SUB instruction
6474 case 'K': // Constant that can be used with a 32-bit logical instruction
6475 case 'L': // Constant that can be used with a 64-bit logical instruction
6476 case 'M': // Constant that can be used as a 32-bit MOV immediate
6477 case 'N': // Constant that can be used as a 64-bit MOV immediate
6478 case 'Y': // Floating point constant zero
6479 case 'Z': // Integer constant zero
6481 case 'Q': // A memory reference with base register and no offset
6482 Info.setAllowsMemory();
6484 case 'S': // A symbolic address
6485 Info.setAllowsRegister();
6488 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
6489 // Utf: A memory address suitable for ldp/stp in TF mode.
6490 // Usa: An absolute symbolic address.
6491 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
6492 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
6493 case 'z': // Zero register, wzr or xzr
6494 Info.setAllowsRegister();
6496 case 'x': // Floating point and SIMD registers (V0-V15)
6497 Info.setAllowsRegister();
6504 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
6505 std::string &SuggestedModifier) const override {
6506 // Strip off constraint modifiers.
6507 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
6508 Constraint = Constraint.substr(1);
6510 switch (Constraint[0]) {
6518 // For now assume that the person knows what they're
6519 // doing with the modifier.
6522 // By default an 'r' constraint will be in the 'x'
6527 SuggestedModifier = "w";
6534 const char *getClobbers() const override { return ""; }
6536 int getEHDataRegisterNumber(unsigned RegNo) const override {
6545 const char *const AArch64TargetInfo::GCCRegNames[] = {
6546 // 32-bit Integer registers
6547 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
6548 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
6549 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
6551 // 64-bit Integer registers
6552 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
6553 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
6554 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
6556 // 32-bit floating point regsisters
6557 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
6558 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
6559 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6561 // 64-bit floating point regsisters
6562 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
6563 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
6564 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6567 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
6568 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
6569 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
6572 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
6573 return llvm::makeArrayRef(GCCRegNames);
6576 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
6577 { { "w31" }, "wsp" },
6578 { { "x29" }, "fp" },
6579 { { "x30" }, "lr" },
6580 { { "x31" }, "sp" },
6581 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
6582 // don't want to substitute one of these for a different-sized one.
6585 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
6586 return llvm::makeArrayRef(GCCRegAliases);
6589 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
6590 #define BUILTIN(ID, TYPE, ATTRS) \
6591 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6592 #include "clang/Basic/BuiltinsNEON.def"
6594 #define BUILTIN(ID, TYPE, ATTRS) \
6595 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6596 #include "clang/Basic/BuiltinsAArch64.def"
6599 class AArch64leTargetInfo : public AArch64TargetInfo {
6600 void setDataLayout() override {
6601 if (getTriple().isOSBinFormatMachO())
6602 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
6604 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6608 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6609 : AArch64TargetInfo(Triple, Opts) {
6611 void getTargetDefines(const LangOptions &Opts,
6612 MacroBuilder &Builder) const override {
6613 Builder.defineMacro("__AARCH64EL__");
6614 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6618 class MicrosoftARM64TargetInfo
6619 : public WindowsTargetInfo<AArch64leTargetInfo> {
6620 const llvm::Triple Triple;
6623 MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
6624 const TargetOptions &Opts)
6625 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
6626 WCharType = UnsignedShort;
6627 SizeType = UnsignedLongLong;
6628 TheCXXABI.set(TargetCXXABI::Microsoft);
6631 void setDataLayout() override {
6632 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128");
6635 void getVisualStudioDefines(const LangOptions &Opts,
6636 MacroBuilder &Builder) const {
6637 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts,
6639 Builder.defineMacro("_WIN32", "1");
6640 Builder.defineMacro("_WIN64", "1");
6641 Builder.defineMacro("_M_ARM64", "1");
6644 void getTargetDefines(const LangOptions &Opts,
6645 MacroBuilder &Builder) const override {
6646 WindowsTargetInfo::getTargetDefines(Opts, Builder);
6647 getVisualStudioDefines(Opts, Builder);
6650 BuiltinVaListKind getBuiltinVaListKind() const override {
6651 return TargetInfo::CharPtrBuiltinVaList;
6655 class AArch64beTargetInfo : public AArch64TargetInfo {
6656 void setDataLayout() override {
6657 assert(!getTriple().isOSBinFormatMachO());
6658 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
6662 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6663 : AArch64TargetInfo(Triple, Opts) {}
6664 void getTargetDefines(const LangOptions &Opts,
6665 MacroBuilder &Builder) const override {
6666 Builder.defineMacro("__AARCH64EB__");
6667 Builder.defineMacro("__AARCH_BIG_ENDIAN");
6668 Builder.defineMacro("__ARM_BIG_ENDIAN");
6669 AArch64TargetInfo::getTargetDefines(Opts, Builder);
6673 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
6675 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
6676 MacroBuilder &Builder) const override {
6677 Builder.defineMacro("__AARCH64_SIMD__");
6678 Builder.defineMacro("__ARM64_ARCH_8__");
6679 Builder.defineMacro("__ARM_NEON__");
6680 Builder.defineMacro("__LITTLE_ENDIAN__");
6681 Builder.defineMacro("__REGISTER_PREFIX__", "");
6682 Builder.defineMacro("__arm64", "1");
6683 Builder.defineMacro("__arm64__", "1");
6685 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
6689 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
6690 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
6691 Int64Type = SignedLongLong;
6692 WCharType = SignedInt;
6693 UseSignedCharForObjCBool = false;
6695 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
6696 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
6698 TheCXXABI.set(TargetCXXABI::iOS64);
6701 BuiltinVaListKind getBuiltinVaListKind() const override {
6702 return TargetInfo::CharPtrBuiltinVaList;
6706 // Hexagon abstract base class
6707 class HexagonTargetInfo : public TargetInfo {
6708 static const Builtin::Info BuiltinInfo[];
6709 static const char * const GCCRegNames[];
6710 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6712 bool HasHVX, HasHVXDouble;
6716 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6717 : TargetInfo(Triple) {
6718 // Specify the vector alignment explicitly. For v512x1, the calculated
6719 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
6720 // the required minimum of 64 bytes.
6721 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-"
6722 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
6723 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
6724 SizeType = UnsignedInt;
6725 PtrDiffType = SignedInt;
6726 IntPtrType = SignedInt;
6728 // {} in inline assembly are packet specifiers, not assembly variant
6730 NoAsmVariants = true;
6732 LargeArrayMinWidth = 64;
6733 LargeArrayAlign = 64;
6734 UseBitFieldTypeAlignment = true;
6735 ZeroLengthBitfieldBoundary = 32;
6736 HasHVX = HasHVXDouble = false;
6737 UseLongCalls = false;
6740 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6741 return llvm::makeArrayRef(BuiltinInfo,
6742 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
6745 bool validateAsmConstraint(const char *&Name,
6746 TargetInfo::ConstraintInfo &Info) const override {
6751 Info.setAllowsRegister();
6756 // Relocatable constant.
6762 void getTargetDefines(const LangOptions &Opts,
6763 MacroBuilder &Builder) const override;
6765 bool isCLZForZeroUndef() const override { return false; }
6767 bool hasFeature(StringRef Feature) const override {
6768 return llvm::StringSwitch<bool>(Feature)
6769 .Case("hexagon", true)
6770 .Case("hvx", HasHVX)
6771 .Case("hvx-double", HasHVXDouble)
6772 .Case("long-calls", UseLongCalls)
6776 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6777 StringRef CPU, const std::vector<std::string> &FeaturesVec)
6780 bool handleTargetFeatures(std::vector<std::string> &Features,
6781 DiagnosticsEngine &Diags) override;
6783 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
6784 bool Enabled) const override;
6786 BuiltinVaListKind getBuiltinVaListKind() const override {
6787 return TargetInfo::CharPtrBuiltinVaList;
6789 ArrayRef<const char *> getGCCRegNames() const override;
6790 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6791 const char *getClobbers() const override {
6795 static const char *getHexagonCPUSuffix(StringRef Name) {
6796 return llvm::StringSwitch<const char*>(Name)
6797 .Case("hexagonv4", "4")
6798 .Case("hexagonv5", "5")
6799 .Case("hexagonv55", "55")
6800 .Case("hexagonv60", "60")
6801 .Case("hexagonv62", "62")
6805 bool setCPU(const std::string &Name) override {
6806 if (!getHexagonCPUSuffix(Name))
6812 int getEHDataRegisterNumber(unsigned RegNo) const override {
6813 return RegNo < 2 ? RegNo : -1;
6817 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
6818 MacroBuilder &Builder) const {
6819 Builder.defineMacro("__qdsp6__", "1");
6820 Builder.defineMacro("__hexagon__", "1");
6822 if (CPU == "hexagonv4") {
6823 Builder.defineMacro("__HEXAGON_V4__");
6824 Builder.defineMacro("__HEXAGON_ARCH__", "4");
6825 if (Opts.HexagonQdsp6Compat) {
6826 Builder.defineMacro("__QDSP6_V4__");
6827 Builder.defineMacro("__QDSP6_ARCH__", "4");
6829 } else if (CPU == "hexagonv5") {
6830 Builder.defineMacro("__HEXAGON_V5__");
6831 Builder.defineMacro("__HEXAGON_ARCH__", "5");
6832 if(Opts.HexagonQdsp6Compat) {
6833 Builder.defineMacro("__QDSP6_V5__");
6834 Builder.defineMacro("__QDSP6_ARCH__", "5");
6836 } else if (CPU == "hexagonv55") {
6837 Builder.defineMacro("__HEXAGON_V55__");
6838 Builder.defineMacro("__HEXAGON_ARCH__", "55");
6839 Builder.defineMacro("__QDSP6_V55__");
6840 Builder.defineMacro("__QDSP6_ARCH__", "55");
6841 } else if (CPU == "hexagonv60") {
6842 Builder.defineMacro("__HEXAGON_V60__");
6843 Builder.defineMacro("__HEXAGON_ARCH__", "60");
6844 Builder.defineMacro("__QDSP6_V60__");
6845 Builder.defineMacro("__QDSP6_ARCH__", "60");
6846 } else if (CPU == "hexagonv62") {
6847 Builder.defineMacro("__HEXAGON_V62__");
6848 Builder.defineMacro("__HEXAGON_ARCH__", "62");
6851 if (hasFeature("hvx")) {
6852 Builder.defineMacro("__HVX__");
6853 if (hasFeature("hvx-double"))
6854 Builder.defineMacro("__HVXDBL__");
6858 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
6859 DiagnosticsEngine &Diags, StringRef CPU,
6860 const std::vector<std::string> &FeaturesVec) const {
6861 // Default for v60: -hvx, -hvx-double.
6862 Features["hvx"] = false;
6863 Features["hvx-double"] = false;
6864 Features["long-calls"] = false;
6866 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6869 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
6870 DiagnosticsEngine &Diags) {
6871 for (auto &F : Features) {
6874 else if (F == "-hvx")
6875 HasHVX = HasHVXDouble = false;
6876 else if (F == "+hvx-double")
6877 HasHVX = HasHVXDouble = true;
6878 else if (F == "-hvx-double")
6879 HasHVXDouble = false;
6881 if (F == "+long-calls")
6882 UseLongCalls = true;
6883 else if (F == "-long-calls")
6884 UseLongCalls = false;
6889 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
6890 StringRef Name, bool Enabled) const {
6892 if (Name == "hvx-double")
6893 Features["hvx"] = true;
6896 Features["hvx-double"] = false;
6898 Features[Name] = Enabled;
6901 const char *const HexagonTargetInfo::GCCRegNames[] = {
6902 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6903 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6904 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6905 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
6906 "p0", "p1", "p2", "p3",
6907 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
6910 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
6911 return llvm::makeArrayRef(GCCRegNames);
6914 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
6915 { { "sp" }, "r29" },
6916 { { "fp" }, "r30" },
6917 { { "lr" }, "r31" },
6920 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
6921 return llvm::makeArrayRef(GCCRegAliases);
6925 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
6926 #define BUILTIN(ID, TYPE, ATTRS) \
6927 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6928 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6929 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6930 #include "clang/Basic/BuiltinsHexagon.def"
6933 class LanaiTargetInfo : public TargetInfo {
6934 // Class for Lanai (32-bit).
6935 // The CPU profiles supported by the Lanai backend
6941 static const TargetInfo::GCCRegAlias GCCRegAliases[];
6942 static const char *const GCCRegNames[];
6945 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
6946 : TargetInfo(Triple) {
6947 // Description string has to be kept in sync with backend.
6948 resetDataLayout("E" // Big endian
6949 "-m:e" // ELF name manging
6950 "-p:32:32" // 32 bit pointers, 32 bit aligned
6951 "-i64:64" // 64 bit integers, 64 bit aligned
6952 "-a:0:32" // 32 bit alignment of objects of aggregate type
6953 "-n32" // 32 bit native integer width
6954 "-S64" // 64 bit natural stack alignment
6957 // Setting RegParmMax equal to what mregparm was set to in the old
6961 // Set the default CPU to V11
6964 // Temporary approach to make everything at least word-aligned and allow for
6965 // safely casting between pointers with different alignment requirements.
6966 // TODO: Remove this when there are no more cast align warnings on the
6968 MinGlobalAlign = 32;
6971 void getTargetDefines(const LangOptions &Opts,
6972 MacroBuilder &Builder) const override {
6973 // Define __lanai__ when building for target lanai.
6974 Builder.defineMacro("__lanai__");
6976 // Set define for the CPU specified.
6979 Builder.defineMacro("__LANAI_V11__");
6982 llvm_unreachable("Unhandled target CPU");
6986 bool setCPU(const std::string &Name) override {
6987 CPU = llvm::StringSwitch<CPUKind>(Name)
6988 .Case("v11", CK_V11)
6991 return CPU != CK_NONE;
6994 bool hasFeature(StringRef Feature) const override {
6995 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
6998 ArrayRef<const char *> getGCCRegNames() const override;
7000 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7002 BuiltinVaListKind getBuiltinVaListKind() const override {
7003 return TargetInfo::VoidPtrBuiltinVaList;
7006 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7008 bool validateAsmConstraint(const char *&Name,
7009 TargetInfo::ConstraintInfo &info) const override {
7013 const char *getClobbers() const override { return ""; }
7016 const char *const LanaiTargetInfo::GCCRegNames[] = {
7017 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7018 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
7019 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
7021 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
7022 return llvm::makeArrayRef(GCCRegNames);
7025 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
7035 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
7036 return llvm::makeArrayRef(GCCRegAliases);
7039 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
7040 class SparcTargetInfo : public TargetInfo {
7041 static const TargetInfo::GCCRegAlias GCCRegAliases[];
7042 static const char * const GCCRegNames[];
7045 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7046 : TargetInfo(Triple), SoftFloat(false) {}
7048 int getEHDataRegisterNumber(unsigned RegNo) const override {
7049 if (RegNo == 0) return 24;
7050 if (RegNo == 1) return 25;
7054 bool handleTargetFeatures(std::vector<std::string> &Features,
7055 DiagnosticsEngine &Diags) override {
7056 // Check if software floating point is enabled
7057 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
7058 if (Feature != Features.end()) {
7063 void getTargetDefines(const LangOptions &Opts,
7064 MacroBuilder &Builder) const override {
7065 DefineStd(Builder, "sparc", Opts);
7066 Builder.defineMacro("__REGISTER_PREFIX__", "");
7069 Builder.defineMacro("SOFT_FLOAT", "1");
7072 bool hasFeature(StringRef Feature) const override {
7073 return llvm::StringSwitch<bool>(Feature)
7074 .Case("softfloat", SoftFloat)
7075 .Case("sparc", true)
7079 bool hasSjLjLowering() const override {
7083 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7084 // FIXME: Implement!
7087 BuiltinVaListKind getBuiltinVaListKind() const override {
7088 return TargetInfo::VoidPtrBuiltinVaList;
7090 ArrayRef<const char *> getGCCRegNames() const override;
7091 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7092 bool validateAsmConstraint(const char *&Name,
7093 TargetInfo::ConstraintInfo &info) const override {
7094 // FIXME: Implement!
7096 case 'I': // Signed 13-bit constant
7098 case 'K': // 32-bit constant with the low 12 bits clear
7099 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
7100 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
7101 case 'N': // Same as 'K' but zext (required for SIMode)
7102 case 'O': // The constant 4096
7107 info.setAllowsRegister();
7112 const char *getClobbers() const override {
7113 // FIXME: Implement!
7117 // No Sparc V7 for now, the backend doesn't support it anyway.
7148 enum CPUGeneration {
7153 CPUGeneration getCPUGeneration(CPUKind Kind) const {
7161 case CK_SPARCLITE86X:
7168 case CK_LEON2_AT697E:
7169 case CK_LEON2_AT697F:
7171 case CK_LEON3_UT699:
7172 case CK_LEON3_GR712RC:
7174 case CK_LEON4_GR740:
7178 case CK_ULTRASPARC3:
7185 llvm_unreachable("Unexpected CPU kind");
7188 CPUKind getCPUKind(StringRef Name) const {
7189 return llvm::StringSwitch<CPUKind>(Name)
7191 .Case("supersparc", CK_SUPERSPARC)
7192 .Case("sparclite", CK_SPARCLITE)
7193 .Case("f934", CK_F934)
7194 .Case("hypersparc", CK_HYPERSPARC)
7195 .Case("sparclite86x", CK_SPARCLITE86X)
7196 .Case("sparclet", CK_SPARCLET)
7197 .Case("tsc701", CK_TSC701)
7199 .Case("ultrasparc", CK_ULTRASPARC)
7200 .Case("ultrasparc3", CK_ULTRASPARC3)
7201 .Case("niagara", CK_NIAGARA)
7202 .Case("niagara2", CK_NIAGARA2)
7203 .Case("niagara3", CK_NIAGARA3)
7204 .Case("niagara4", CK_NIAGARA4)
7205 .Case("ma2100", CK_MYRIAD2100)
7206 .Case("ma2150", CK_MYRIAD2150)
7207 .Case("ma2450", CK_MYRIAD2450)
7208 // FIXME: the myriad2[.n] spellings are obsolete,
7209 // but a grace period is needed to allow updating dependent builds.
7210 .Case("myriad2", CK_MYRIAD2100)
7211 .Case("myriad2.1", CK_MYRIAD2100)
7212 .Case("myriad2.2", CK_MYRIAD2150)
7213 .Case("leon2", CK_LEON2)
7214 .Case("at697e", CK_LEON2_AT697E)
7215 .Case("at697f", CK_LEON2_AT697F)
7216 .Case("leon3", CK_LEON3)
7217 .Case("ut699", CK_LEON3_UT699)
7218 .Case("gr712rc", CK_LEON3_GR712RC)
7219 .Case("leon4", CK_LEON4)
7220 .Case("gr740", CK_LEON4_GR740)
7221 .Default(CK_GENERIC);
7224 bool setCPU(const std::string &Name) override {
7225 CPU = getCPUKind(Name);
7226 return CPU != CK_GENERIC;
7230 const char * const SparcTargetInfo::GCCRegNames[] = {
7231 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7232 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7233 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7234 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7237 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
7238 return llvm::makeArrayRef(GCCRegNames);
7241 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
7252 { { "o2" }, "r10" },
7253 { { "o3" }, "r11" },
7254 { { "o4" }, "r12" },
7255 { { "o5" }, "r13" },
7256 { { "o6", "sp" }, "r14" },
7257 { { "o7" }, "r15" },
7258 { { "l0" }, "r16" },
7259 { { "l1" }, "r17" },
7260 { { "l2" }, "r18" },
7261 { { "l3" }, "r19" },
7262 { { "l4" }, "r20" },
7263 { { "l5" }, "r21" },
7264 { { "l6" }, "r22" },
7265 { { "l7" }, "r23" },
7266 { { "i0" }, "r24" },
7267 { { "i1" }, "r25" },
7268 { { "i2" }, "r26" },
7269 { { "i3" }, "r27" },
7270 { { "i4" }, "r28" },
7271 { { "i5" }, "r29" },
7272 { { "i6", "fp" }, "r30" },
7273 { { "i7" }, "r31" },
7276 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
7277 return llvm::makeArrayRef(GCCRegAliases);
7280 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
7281 class SparcV8TargetInfo : public SparcTargetInfo {
7283 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7284 : SparcTargetInfo(Triple, Opts) {
7285 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
7286 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
7287 switch (getTriple().getOS()) {
7289 SizeType = UnsignedInt;
7290 IntPtrType = SignedInt;
7291 PtrDiffType = SignedInt;
7293 case llvm::Triple::NetBSD:
7294 case llvm::Triple::OpenBSD:
7295 SizeType = UnsignedLong;
7296 IntPtrType = SignedLong;
7297 PtrDiffType = SignedLong;
7300 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
7301 // on up to 64 bits.
7302 MaxAtomicPromoteWidth = 64;
7303 MaxAtomicInlineWidth = 32;
7306 void getTargetDefines(const LangOptions &Opts,
7307 MacroBuilder &Builder) const override {
7308 SparcTargetInfo::getTargetDefines(Opts, Builder);
7309 switch (getCPUGeneration(CPU)) {
7311 Builder.defineMacro("__sparcv8");
7312 if (getTriple().getOS() != llvm::Triple::Solaris)
7313 Builder.defineMacro("__sparcv8__");
7316 Builder.defineMacro("__sparcv9");
7317 if (getTriple().getOS() != llvm::Triple::Solaris) {
7318 Builder.defineMacro("__sparcv9__");
7319 Builder.defineMacro("__sparc_v9__");
7323 if (getTriple().getVendor() == llvm::Triple::Myriad) {
7324 std::string MyriadArchValue, Myriad2Value;
7325 Builder.defineMacro("__sparc_v8__");
7326 Builder.defineMacro("__leon__");
7329 MyriadArchValue = "__ma2150";
7333 MyriadArchValue = "__ma2450";
7337 MyriadArchValue = "__ma2100";
7341 Builder.defineMacro(MyriadArchValue, "1");
7342 Builder.defineMacro(MyriadArchValue+"__", "1");
7343 Builder.defineMacro("__myriad2__", Myriad2Value);
7344 Builder.defineMacro("__myriad2", Myriad2Value);
7348 bool hasSjLjLowering() const override {
7353 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
7354 class SparcV8elTargetInfo : public SparcV8TargetInfo {
7356 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7357 : SparcV8TargetInfo(Triple, Opts) {
7358 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
7362 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
7363 class SparcV9TargetInfo : public SparcTargetInfo {
7365 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7366 : SparcTargetInfo(Triple, Opts) {
7367 // FIXME: Support Sparc quad-precision long double?
7368 resetDataLayout("E-m:e-i64:64-n32:64-S128");
7369 // This is an LP64 platform.
7370 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7372 // OpenBSD uses long long for int64_t and intmax_t.
7373 if (getTriple().getOS() == llvm::Triple::OpenBSD)
7374 IntMaxType = SignedLongLong;
7376 IntMaxType = SignedLong;
7377 Int64Type = IntMaxType;
7379 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
7380 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
7381 LongDoubleWidth = 128;
7382 LongDoubleAlign = 128;
7383 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7384 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7387 void getTargetDefines(const LangOptions &Opts,
7388 MacroBuilder &Builder) const override {
7389 SparcTargetInfo::getTargetDefines(Opts, Builder);
7390 Builder.defineMacro("__sparcv9");
7391 Builder.defineMacro("__arch64__");
7392 // Solaris doesn't need these variants, but the BSDs do.
7393 if (getTriple().getOS() != llvm::Triple::Solaris) {
7394 Builder.defineMacro("__sparc64__");
7395 Builder.defineMacro("__sparc_v9__");
7396 Builder.defineMacro("__sparcv9__");
7400 bool setCPU(const std::string &Name) override {
7401 if (!SparcTargetInfo::setCPU(Name))
7403 return getCPUGeneration(CPU) == CG_V9;
7407 class SystemZTargetInfo : public TargetInfo {
7408 static const Builtin::Info BuiltinInfo[];
7409 static const char *const GCCRegNames[];
7411 bool HasTransactionalExecution;
7415 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7416 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
7418 IntMaxType = SignedLong;
7419 Int64Type = SignedLong;
7420 TLSSupported = true;
7421 IntWidth = IntAlign = 32;
7422 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
7423 PointerWidth = PointerAlign = 64;
7424 LongDoubleWidth = 128;
7425 LongDoubleAlign = 64;
7426 LongDoubleFormat = &llvm::APFloat::IEEEquad();
7427 DefaultAlignForAttributeAligned = 64;
7428 MinGlobalAlign = 16;
7429 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
7430 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7432 void getTargetDefines(const LangOptions &Opts,
7433 MacroBuilder &Builder) const override {
7434 Builder.defineMacro("__s390__");
7435 Builder.defineMacro("__s390x__");
7436 Builder.defineMacro("__zarch__");
7437 Builder.defineMacro("__LONG_DOUBLE_128__");
7439 const std::string ISARev = llvm::StringSwitch<std::string>(CPU)
7440 .Cases("arch8", "z10", "8")
7441 .Cases("arch9", "z196", "9")
7442 .Cases("arch10", "zEC12", "10")
7443 .Cases("arch11", "z13", "11")
7445 if (!ISARev.empty())
7446 Builder.defineMacro("__ARCH__", ISARev);
7448 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
7449 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
7450 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
7451 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7453 if (HasTransactionalExecution)
7454 Builder.defineMacro("__HTM__");
7456 Builder.defineMacro("__VX__");
7458 Builder.defineMacro("__VEC__", "10301");
7460 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7461 return llvm::makeArrayRef(BuiltinInfo,
7462 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
7465 ArrayRef<const char *> getGCCRegNames() const override;
7466 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7470 bool validateAsmConstraint(const char *&Name,
7471 TargetInfo::ConstraintInfo &info) const override;
7472 const char *getClobbers() const override {
7473 // FIXME: Is this really right?
7476 BuiltinVaListKind getBuiltinVaListKind() const override {
7477 return TargetInfo::SystemZBuiltinVaList;
7479 bool setCPU(const std::string &Name) override {
7481 bool CPUKnown = llvm::StringSwitch<bool>(Name)
7483 .Case("arch8", true)
7485 .Case("arch9", true)
7486 .Case("zEC12", true)
7487 .Case("arch10", true)
7489 .Case("arch11", true)
7495 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7497 const std::vector<std::string> &FeaturesVec) const override {
7498 if (CPU == "zEC12" || CPU == "arch10")
7499 Features["transactional-execution"] = true;
7500 if (CPU == "z13" || CPU == "arch11") {
7501 Features["transactional-execution"] = true;
7502 Features["vector"] = true;
7504 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7507 bool handleTargetFeatures(std::vector<std::string> &Features,
7508 DiagnosticsEngine &Diags) override {
7509 HasTransactionalExecution = false;
7510 for (const auto &Feature : Features) {
7511 if (Feature == "+transactional-execution")
7512 HasTransactionalExecution = true;
7513 else if (Feature == "+vector")
7516 // If we use the vector ABI, vector types are 64-bit aligned.
7518 MaxVectorAlign = 64;
7519 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
7520 "-v128:64-a:8:16-n32:64");
7525 bool hasFeature(StringRef Feature) const override {
7526 return llvm::StringSwitch<bool>(Feature)
7527 .Case("systemz", true)
7528 .Case("htm", HasTransactionalExecution)
7529 .Case("vx", HasVector)
7533 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7537 case CC_OpenCLKernel:
7540 return CCCR_Warning;
7544 StringRef getABI() const override {
7550 bool useFloat128ManglingForLongDouble() const override {
7555 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
7556 #define BUILTIN(ID, TYPE, ATTRS) \
7557 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7558 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7559 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
7560 #include "clang/Basic/BuiltinsSystemZ.def"
7563 const char *const SystemZTargetInfo::GCCRegNames[] = {
7564 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7565 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7566 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
7567 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
7570 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
7571 return llvm::makeArrayRef(GCCRegNames);
7574 bool SystemZTargetInfo::
7575 validateAsmConstraint(const char *&Name,
7576 TargetInfo::ConstraintInfo &Info) const {
7581 case 'a': // Address register
7582 case 'd': // Data register (equivalent to 'r')
7583 case 'f': // Floating-point register
7584 Info.setAllowsRegister();
7587 case 'I': // Unsigned 8-bit constant
7588 case 'J': // Unsigned 12-bit constant
7589 case 'K': // Signed 16-bit constant
7590 case 'L': // Signed 20-bit displacement (on all targets we support)
7591 case 'M': // 0x7fffffff
7594 case 'Q': // Memory with base and unsigned 12-bit displacement
7595 case 'R': // Likewise, plus an index
7596 case 'S': // Memory with base and signed 20-bit displacement
7597 case 'T': // Likewise, plus an index
7598 Info.setAllowsMemory();
7603 class MSP430TargetInfo : public TargetInfo {
7604 static const char *const GCCRegNames[];
7607 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7608 : TargetInfo(Triple) {
7609 TLSSupported = false;
7614 LongAlign = LongLongAlign = 16;
7618 SizeType = UnsignedInt;
7619 IntMaxType = SignedLongLong;
7620 IntPtrType = SignedInt;
7621 PtrDiffType = SignedInt;
7622 SigAtomicType = SignedLong;
7623 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16");
7625 void getTargetDefines(const LangOptions &Opts,
7626 MacroBuilder &Builder) const override {
7627 Builder.defineMacro("MSP430");
7628 Builder.defineMacro("__MSP430__");
7629 // FIXME: defines for different 'flavours' of MCU
7631 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7632 // FIXME: Implement.
7635 bool hasFeature(StringRef Feature) const override {
7636 return Feature == "msp430";
7638 ArrayRef<const char *> getGCCRegNames() const override;
7639 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7643 bool validateAsmConstraint(const char *&Name,
7644 TargetInfo::ConstraintInfo &info) const override {
7647 case 'K': // the constant 1
7648 case 'L': // constant -1^20 .. 1^19
7649 case 'M': // constant 1-4:
7652 // No target constraints for now.
7655 const char *getClobbers() const override {
7656 // FIXME: Is this really right?
7659 BuiltinVaListKind getBuiltinVaListKind() const override {
7661 return TargetInfo::CharPtrBuiltinVaList;
7665 const char *const MSP430TargetInfo::GCCRegNames[] = {
7666 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7667 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
7669 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
7670 return llvm::makeArrayRef(GCCRegNames);
7673 // LLVM and Clang cannot be used directly to output native binaries for
7674 // target, but is used to compile C code to llvm bitcode with correct
7675 // type and alignment information.
7677 // TCE uses the llvm bitcode as input and uses it for generating customized
7678 // target processor and program binary. TCE co-design environment is
7679 // publicly available in http://tce.cs.tut.fi
7681 static const unsigned TCEOpenCLAddrSpaceMap[] = {
7685 5, // opencl_constant
7686 // FIXME: generic has to be added to the target
7687 0, // opencl_generic
7693 class TCETargetInfo : public TargetInfo {
7695 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7696 : TargetInfo(Triple) {
7697 TLSSupported = false;
7699 LongWidth = LongLongWidth = 32;
7702 LongAlign = LongLongAlign = 32;
7705 SizeType = UnsignedInt;
7706 IntMaxType = SignedLong;
7707 IntPtrType = SignedInt;
7708 PtrDiffType = SignedInt;
7713 LongDoubleWidth = 32;
7714 LongDoubleAlign = 32;
7715 FloatFormat = &llvm::APFloat::IEEEsingle();
7716 DoubleFormat = &llvm::APFloat::IEEEsingle();
7717 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
7718 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-"
7719 "i16:16:32-i32:32:32-i64:32:32-"
7720 "f32:32:32-f64:32:32-v64:32:32-"
7721 "v128:32:32-v256:32:32-v512:32:32-"
7722 "v1024:32:32-a0:0:32-n32");
7723 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
7724 UseAddrSpaceMapMangling = true;
7727 void getTargetDefines(const LangOptions &Opts,
7728 MacroBuilder &Builder) const override {
7729 DefineStd(Builder, "tce", Opts);
7730 Builder.defineMacro("__TCE__");
7731 Builder.defineMacro("__TCE_V1__");
7733 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
7735 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7736 const char *getClobbers() const override { return ""; }
7737 BuiltinVaListKind getBuiltinVaListKind() const override {
7738 return TargetInfo::VoidPtrBuiltinVaList;
7740 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7741 bool validateAsmConstraint(const char *&Name,
7742 TargetInfo::ConstraintInfo &info) const override {
7745 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7750 class TCELETargetInfo : public TCETargetInfo {
7752 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
7753 : TCETargetInfo(Triple, Opts) {
7756 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-"
7757 "i16:16:32-i32:32:32-i64:32:32-"
7758 "f32:32:32-f64:32:32-v64:32:32-"
7759 "v128:32:32-v256:32:32-v512:32:32-"
7760 "v1024:32:32-a0:0:32-n32");
7764 virtual void getTargetDefines(const LangOptions &Opts,
7765 MacroBuilder &Builder) const {
7766 DefineStd(Builder, "tcele", Opts);
7767 Builder.defineMacro("__TCE__");
7768 Builder.defineMacro("__TCE_V1__");
7769 Builder.defineMacro("__TCELE__");
7770 Builder.defineMacro("__TCELE_V1__");
7775 class BPFTargetInfo : public TargetInfo {
7777 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
7778 : TargetInfo(Triple) {
7779 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7780 SizeType = UnsignedLong;
7781 PtrDiffType = SignedLong;
7782 IntPtrType = SignedLong;
7783 IntMaxType = SignedLong;
7784 Int64Type = SignedLong;
7786 if (Triple.getArch() == llvm::Triple::bpfeb) {
7787 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
7789 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
7791 MaxAtomicPromoteWidth = 64;
7792 MaxAtomicInlineWidth = 64;
7793 TLSSupported = false;
7795 void getTargetDefines(const LangOptions &Opts,
7796 MacroBuilder &Builder) const override {
7797 DefineStd(Builder, "bpf", Opts);
7798 Builder.defineMacro("__BPF__");
7800 bool hasFeature(StringRef Feature) const override {
7801 return Feature == "bpf";
7804 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7805 const char *getClobbers() const override {
7808 BuiltinVaListKind getBuiltinVaListKind() const override {
7809 return TargetInfo::VoidPtrBuiltinVaList;
7811 ArrayRef<const char *> getGCCRegNames() const override {
7814 bool validateAsmConstraint(const char *&Name,
7815 TargetInfo::ConstraintInfo &info) const override {
7818 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7821 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7824 return CCCR_Warning;
7826 case CC_OpenCLKernel:
7832 class Nios2TargetInfo : public TargetInfo {
7833 void setDataLayout() {
7835 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32");
7837 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32");
7840 static const Builtin::Info BuiltinInfo[];
7845 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts)
7846 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) {
7847 SizeType = UnsignedInt;
7848 PtrDiffType = SignedInt;
7849 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7853 StringRef getABI() const override { return ABI; }
7854 bool setABI(const std::string &Name) override {
7855 if (Name == "o32" || Name == "eabi") {
7862 bool setCPU(const std::string &Name) override {
7863 if (Name == "nios2r1" || Name == "nios2r2") {
7870 void getTargetDefines(const LangOptions &Opts,
7871 MacroBuilder &Builder) const override {
7872 DefineStd(Builder, "nios2", Opts);
7873 DefineStd(Builder, "NIOS2", Opts);
7875 Builder.defineMacro("__nios2");
7876 Builder.defineMacro("__NIOS2");
7877 Builder.defineMacro("__nios2__");
7878 Builder.defineMacro("__NIOS2__");
7881 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7882 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin -
7883 Builtin::FirstTSBuiltin);
7886 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const {
7887 const bool isR2 = CPU == "nios2r2";
7888 return llvm::StringSwitch<bool>(Feature)
7889 .Case("nios2r2mandatory", isR2)
7890 .Case("nios2r2bmx", isR2)
7891 .Case("nios2r2mpx", isR2)
7892 .Case("nios2r2cdx", isR2)
7896 bool initFeatureMap(llvm::StringMap<bool> &Features,
7897 DiagnosticsEngine &Diags, StringRef CPU,
7898 const std::vector<std::string> &FeatureVec) const override {
7899 static const char *allFeatures[] = {
7900 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx"
7902 for (const char *feature : allFeatures) {
7903 Features[feature] = isFeatureSupportedByCPU(feature, CPU);
7908 bool hasFeature(StringRef Feature) const override {
7909 return isFeatureSupportedByCPU(Feature, CPU);
7912 BuiltinVaListKind getBuiltinVaListKind() const override {
7913 return TargetInfo::VoidPtrBuiltinVaList;
7916 ArrayRef<const char *> getGCCRegNames() const override {
7917 static const char *const GCCRegNames[] = {
7918 // CPU register names
7919 // Must match second column of GCCRegAliases
7920 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
7921 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
7922 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30",
7924 // Floating point register names
7925 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8",
7926 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15"
7928 return llvm::makeArrayRef(GCCRegNames);
7931 bool validateAsmConstraint(const char *&Name,
7932 TargetInfo::ConstraintInfo &Info) const override {
7937 case 'r': // CPU registers.
7938 case 'd': // Equivalent to "r" unless generating MIPS16 code.
7939 case 'y': // Equivalent to "r", backwards compatibility only.
7940 case 'f': // floating-point registers.
7941 case 'c': // $25 for indirect jumps
7942 case 'l': // lo register
7943 case 'x': // hilo register pair
7944 Info.setAllowsRegister();
7949 const char *getClobbers() const override { return ""; }
7951 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7952 static const TargetInfo::GCCRegAlias aliases[] = {
7953 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"},
7954 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"},
7955 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"},
7956 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"},
7957 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"},
7958 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"},
7959 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"},
7960 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"},
7962 return llvm::makeArrayRef(aliases);
7966 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = {
7967 #define BUILTIN(ID, TYPE, ATTRS) \
7968 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
7969 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
7970 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
7971 #include "clang/Basic/BuiltinsNios2.def"
7974 class MipsTargetInfo : public TargetInfo {
7975 void setDataLayout() {
7979 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
7980 else if (ABI == "n32")
7981 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7982 else if (ABI == "n64")
7983 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7985 llvm_unreachable("Invalid ABI");
7988 resetDataLayout(("E-" + Layout).str());
7990 resetDataLayout(("e-" + Layout).str());
7994 static const Builtin::Info BuiltinInfo[];
8001 bool CanUseBSDABICalls;
8003 HardFloat, SoftFloat
8016 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8017 : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
8018 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
8019 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
8020 HasMSA(false), DisableMadd4(false), HasFP64(false) {
8021 TheCXXABI.set(TargetCXXABI::GenericMIPS);
8023 setABI((getTriple().getArch() == llvm::Triple::mips ||
8024 getTriple().getArch() == llvm::Triple::mipsel)
8028 CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
8030 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
8031 Triple.getOS() == llvm::Triple::OpenBSD;
8034 bool isNaN2008Default() const {
8035 return CPU == "mips32r6" || CPU == "mips64r6";
8038 bool isFP64Default() const {
8039 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
8042 bool isNan2008() const override {
8046 bool processorSupportsGPR64() const {
8047 return llvm::StringSwitch<bool>(CPU)
8048 .Case("mips3", true)
8049 .Case("mips4", true)
8050 .Case("mips5", true)
8051 .Case("mips64", true)
8052 .Case("mips64r2", true)
8053 .Case("mips64r3", true)
8054 .Case("mips64r5", true)
8055 .Case("mips64r6", true)
8056 .Case("octeon", true)
8061 StringRef getABI() const override { return ABI; }
8062 bool setABI(const std::string &Name) override {
8063 if (Name == "o32") {
8069 if (Name == "n32") {
8074 if (Name == "n64") {
8082 void setO32ABITypes() {
8083 Int64Type = SignedLongLong;
8084 IntMaxType = Int64Type;
8085 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8086 LongDoubleWidth = LongDoubleAlign = 64;
8087 LongWidth = LongAlign = 32;
8088 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
8089 PointerWidth = PointerAlign = 32;
8090 PtrDiffType = SignedInt;
8091 SizeType = UnsignedInt;
8095 void setN32N64ABITypes() {
8096 LongDoubleWidth = LongDoubleAlign = 128;
8097 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8098 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
8099 LongDoubleWidth = LongDoubleAlign = 64;
8100 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8102 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8103 SuitableAlign = 128;
8106 void setN64ABITypes() {
8107 setN32N64ABITypes();
8108 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
8109 Int64Type = SignedLongLong;
8111 Int64Type = SignedLong;
8113 IntMaxType = Int64Type;
8114 LongWidth = LongAlign = 64;
8115 PointerWidth = PointerAlign = 64;
8116 PtrDiffType = SignedLong;
8117 SizeType = UnsignedLong;
8120 void setN32ABITypes() {
8121 setN32N64ABITypes();
8122 Int64Type = SignedLongLong;
8123 IntMaxType = Int64Type;
8124 LongWidth = LongAlign = 32;
8125 PointerWidth = PointerAlign = 32;
8126 PtrDiffType = SignedInt;
8127 SizeType = UnsignedInt;
8130 bool setCPU(const std::string &Name) override {
8132 return llvm::StringSwitch<bool>(Name)
8133 .Case("mips1", true)
8134 .Case("mips2", true)
8135 .Case("mips3", true)
8136 .Case("mips4", true)
8137 .Case("mips5", true)
8138 .Case("mips32", true)
8139 .Case("mips32r2", true)
8140 .Case("mips32r3", true)
8141 .Case("mips32r5", true)
8142 .Case("mips32r6", true)
8143 .Case("mips64", true)
8144 .Case("mips64r2", true)
8145 .Case("mips64r3", true)
8146 .Case("mips64r5", true)
8147 .Case("mips64r6", true)
8148 .Case("octeon", true)
8149 .Case("p5600", true)
8152 const std::string& getCPU() const { return CPU; }
8154 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8156 const std::vector<std::string> &FeaturesVec) const override {
8159 if (CPU == "octeon")
8160 Features["mips64r2"] = Features["cnmips"] = true;
8162 Features[CPU] = true;
8163 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8166 void getTargetDefines(const LangOptions &Opts,
8167 MacroBuilder &Builder) const override {
8169 DefineStd(Builder, "MIPSEB", Opts);
8170 Builder.defineMacro("_MIPSEB");
8172 DefineStd(Builder, "MIPSEL", Opts);
8173 Builder.defineMacro("_MIPSEL");
8176 Builder.defineMacro("__mips__");
8177 Builder.defineMacro("_mips");
8179 Builder.defineMacro("mips");
8182 Builder.defineMacro("__mips", "32");
8183 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
8185 Builder.defineMacro("__mips", "64");
8186 Builder.defineMacro("__mips64");
8187 Builder.defineMacro("__mips64__");
8188 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
8191 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU())
8192 .Cases("mips32", "mips64", "1")
8193 .Cases("mips32r2", "mips64r2", "2")
8194 .Cases("mips32r3", "mips64r3", "3")
8195 .Cases("mips32r5", "mips64r5", "5")
8196 .Cases("mips32r6", "mips64r6", "6")
8198 if (!ISARev.empty())
8199 Builder.defineMacro("__mips_isa_rev", ISARev);
8202 Builder.defineMacro("__mips_o32");
8203 Builder.defineMacro("_ABIO32", "1");
8204 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
8205 } else if (ABI == "n32") {
8206 Builder.defineMacro("__mips_n32");
8207 Builder.defineMacro("_ABIN32", "2");
8208 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
8209 } else if (ABI == "n64") {
8210 Builder.defineMacro("__mips_n64");
8211 Builder.defineMacro("_ABI64", "3");
8212 Builder.defineMacro("_MIPS_SIM", "_ABI64");
8214 llvm_unreachable("Invalid ABI.");
8216 if (!IsNoABICalls) {
8217 Builder.defineMacro("__mips_abicalls");
8218 if (CanUseBSDABICalls)
8219 Builder.defineMacro("__ABICALLS__");
8222 Builder.defineMacro("__REGISTER_PREFIX__", "");
8226 Builder.defineMacro("__mips_hard_float", Twine(1));
8229 Builder.defineMacro("__mips_soft_float", Twine(1));
8234 Builder.defineMacro("__mips_single_float", Twine(1));
8236 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
8237 Builder.defineMacro("_MIPS_FPSET",
8238 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
8241 Builder.defineMacro("__mips16", Twine(1));
8244 Builder.defineMacro("__mips_micromips", Twine(1));
8247 Builder.defineMacro("__mips_nan2008", Twine(1));
8253 Builder.defineMacro("__mips_dsp_rev", Twine(1));
8254 Builder.defineMacro("__mips_dsp", Twine(1));
8257 Builder.defineMacro("__mips_dsp_rev", Twine(2));
8258 Builder.defineMacro("__mips_dspr2", Twine(1));
8259 Builder.defineMacro("__mips_dsp", Twine(1));
8264 Builder.defineMacro("__mips_msa", Twine(1));
8267 Builder.defineMacro("__mips_no_madd4", Twine(1));
8269 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
8270 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
8271 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
8273 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
8274 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
8276 // These shouldn't be defined for MIPS-I but there's no need to check
8277 // for that since MIPS-I isn't supported.
8278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
8279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
8280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
8282 // 32-bit MIPS processors don't have the necessary lld/scd instructions
8283 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
8284 // the instructions exist but using them violates the ABI since they
8285 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
8286 if (ABI == "n32" || ABI == "n64")
8287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
8290 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8291 return llvm::makeArrayRef(BuiltinInfo,
8292 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
8294 bool hasFeature(StringRef Feature) const override {
8295 return llvm::StringSwitch<bool>(Feature)
8297 .Case("fp64", HasFP64)
8300 BuiltinVaListKind getBuiltinVaListKind() const override {
8301 return TargetInfo::VoidPtrBuiltinVaList;
8303 ArrayRef<const char *> getGCCRegNames() const override {
8304 static const char *const GCCRegNames[] = {
8305 // CPU register names
8306 // Must match second column of GCCRegAliases
8307 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
8308 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
8309 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
8310 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
8311 // Floating point register names
8312 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
8313 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
8314 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
8315 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
8316 // Hi/lo and condition register names
8317 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
8318 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
8320 // MSA register names
8321 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
8322 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
8323 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
8324 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
8325 // MSA control register names
8326 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
8327 "$msarequest", "$msamap", "$msaunmap"
8329 return llvm::makeArrayRef(GCCRegNames);
8331 bool validateAsmConstraint(const char *&Name,
8332 TargetInfo::ConstraintInfo &Info) const override {
8336 case 'r': // CPU registers.
8337 case 'd': // Equivalent to "r" unless generating MIPS16 code.
8338 case 'y': // Equivalent to "r", backward compatibility only.
8339 case 'f': // floating-point registers.
8340 case 'c': // $25 for indirect jumps
8341 case 'l': // lo register
8342 case 'x': // hilo register pair
8343 Info.setAllowsRegister();
8345 case 'I': // Signed 16-bit constant
8346 case 'J': // Integer 0
8347 case 'K': // Unsigned 16-bit constant
8348 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
8349 case 'M': // Constants not loadable via lui, addiu, or ori
8350 case 'N': // Constant -1 to -65535
8351 case 'O': // A signed 15-bit constant
8352 case 'P': // A constant between 1 go 65535
8354 case 'R': // An address that can be used in a non-macro load or store
8355 Info.setAllowsMemory();
8358 if (Name[1] == 'C') { // An address usable by ll, and sc.
8359 Info.setAllowsMemory();
8360 Name++; // Skip over 'Z'.
8367 std::string convertConstraint(const char *&Constraint) const override {
8369 switch (*Constraint) {
8370 case 'Z': // Two-character constraint; add "^" hint for later parsing.
8371 if (Constraint[1] == 'C') {
8372 R = std::string("^") + std::string(Constraint, 2);
8378 return TargetInfo::convertConstraint(Constraint);
8381 const char *getClobbers() const override {
8382 // In GCC, $1 is not widely used in generated code (it's used only in a few
8383 // specific situations), so there is no real need for users to add it to
8384 // the clobbers list if they want to use it in their inline assembly code.
8386 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
8387 // code generation, so using it in inline assembly without adding it to the
8388 // clobbers list can cause conflicts between the inline assembly code and
8389 // the surrounding generated code.
8391 // Another problem is that LLVM is allowed to choose $1 for inline assembly
8392 // operands, which will conflict with the ".set at" assembler option (which
8393 // we use only for inline assembly, in order to maintain compatibility with
8394 // GCC) and will also conflict with the user's usage of $1.
8396 // The easiest way to avoid these conflicts and keep $1 as an allocatable
8397 // register for generated code is to automatically clobber $1 for all inline
8400 // FIXME: We should automatically clobber $1 only for inline assembly code
8401 // which actually uses it. This would allow LLVM to use $1 for inline
8402 // assembly operands if the user's assembly code doesn't use it.
8406 bool handleTargetFeatures(std::vector<std::string> &Features,
8407 DiagnosticsEngine &Diags) override {
8409 IsMicromips = false;
8410 IsNan2008 = isNaN2008Default();
8411 IsSingleFloat = false;
8412 FloatABI = HardFloat;
8414 HasFP64 = isFP64Default();
8416 for (const auto &Feature : Features) {
8417 if (Feature == "+single-float")
8418 IsSingleFloat = true;
8419 else if (Feature == "+soft-float")
8420 FloatABI = SoftFloat;
8421 else if (Feature == "+mips16")
8423 else if (Feature == "+micromips")
8425 else if (Feature == "+dsp")
8426 DspRev = std::max(DspRev, DSP1);
8427 else if (Feature == "+dspr2")
8428 DspRev = std::max(DspRev, DSP2);
8429 else if (Feature == "+msa")
8431 else if (Feature == "+nomadd4")
8432 DisableMadd4 = true;
8433 else if (Feature == "+fp64")
8435 else if (Feature == "-fp64")
8437 else if (Feature == "+nan2008")
8439 else if (Feature == "-nan2008")
8441 else if (Feature == "+noabicalls")
8442 IsNoABICalls = true;
8450 int getEHDataRegisterNumber(unsigned RegNo) const override {
8451 if (RegNo == 0) return 4;
8452 if (RegNo == 1) return 5;
8456 bool isCLZForZeroUndef() const override { return false; }
8458 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8459 static const TargetInfo::GCCRegAlias O32RegAliases[] = {
8460 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8461 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8462 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
8463 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
8464 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
8465 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8466 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8467 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8468 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8469 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8471 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
8472 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
8473 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
8474 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
8475 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
8476 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
8477 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
8478 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
8479 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
8480 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
8481 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
8484 return llvm::makeArrayRef(O32RegAliases);
8485 return llvm::makeArrayRef(NewABIRegAliases);
8488 bool hasInt128Type() const override {
8489 return ABI == "n32" || ABI == "n64";
8492 bool validateTarget(DiagnosticsEngine &Diags) const override {
8493 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
8494 // this yet. It's better to fail here than on the backend assertion.
8495 if (processorSupportsGPR64() && ABI == "o32") {
8496 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8500 // 64-bit ABI's require 64-bit CPU's.
8501 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
8502 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
8506 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
8507 // can't handle this yet. It's better to fail here than on the
8508 // backend assertion.
8509 if ((getTriple().getArch() == llvm::Triple::mips64 ||
8510 getTriple().getArch() == llvm::Triple::mips64el) &&
8512 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8513 << ABI << getTriple().str();
8517 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
8518 // can't handle this yet. It's better to fail here than on the
8519 // backend assertion.
8520 if ((getTriple().getArch() == llvm::Triple::mips ||
8521 getTriple().getArch() == llvm::Triple::mipsel) &&
8522 (ABI == "n32" || ABI == "n64")) {
8523 Diags.Report(diag::err_target_unsupported_abi_for_triple)
8524 << ABI << getTriple().str();
8532 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
8533 #define BUILTIN(ID, TYPE, ATTRS) \
8534 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8535 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8536 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8537 #include "clang/Basic/BuiltinsMips.def"
8540 class PNaClTargetInfo : public TargetInfo {
8542 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8543 : TargetInfo(Triple) {
8544 this->LongAlign = 32;
8545 this->LongWidth = 32;
8546 this->PointerAlign = 32;
8547 this->PointerWidth = 32;
8548 this->IntMaxType = TargetInfo::SignedLongLong;
8549 this->Int64Type = TargetInfo::SignedLongLong;
8550 this->DoubleAlign = 64;
8551 this->LongDoubleWidth = 64;
8552 this->LongDoubleAlign = 64;
8553 this->SizeType = TargetInfo::UnsignedInt;
8554 this->PtrDiffType = TargetInfo::SignedInt;
8555 this->IntPtrType = TargetInfo::SignedInt;
8556 this->RegParmMax = 0; // Disallow regparm
8559 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
8560 Builder.defineMacro("__le32__");
8561 Builder.defineMacro("__pnacl__");
8563 void getTargetDefines(const LangOptions &Opts,
8564 MacroBuilder &Builder) const override {
8565 getArchDefines(Opts, Builder);
8567 bool hasFeature(StringRef Feature) const override {
8568 return Feature == "pnacl";
8570 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8571 BuiltinVaListKind getBuiltinVaListKind() const override {
8572 return TargetInfo::PNaClABIBuiltinVaList;
8574 ArrayRef<const char *> getGCCRegNames() const override;
8575 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
8576 bool validateAsmConstraint(const char *&Name,
8577 TargetInfo::ConstraintInfo &Info) const override {
8581 const char *getClobbers() const override {
8586 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
8590 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
8594 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
8595 class NaClMips32TargetInfo : public MipsTargetInfo {
8597 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8598 : MipsTargetInfo(Triple, Opts) {}
8600 BuiltinVaListKind getBuiltinVaListKind() const override {
8601 return TargetInfo::PNaClABIBuiltinVaList;
8605 class Le64TargetInfo : public TargetInfo {
8606 static const Builtin::Info BuiltinInfo[];
8609 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8610 : TargetInfo(Triple) {
8611 NoAsmVariants = true;
8612 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
8613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8614 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
8617 void getTargetDefines(const LangOptions &Opts,
8618 MacroBuilder &Builder) const override {
8619 DefineStd(Builder, "unix", Opts);
8620 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
8621 Builder.defineMacro("__ELF__");
8623 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8624 return llvm::makeArrayRef(BuiltinInfo,
8625 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
8627 BuiltinVaListKind getBuiltinVaListKind() const override {
8628 return TargetInfo::PNaClABIBuiltinVaList;
8630 const char *getClobbers() const override { return ""; }
8631 ArrayRef<const char *> getGCCRegNames() const override {
8634 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8637 bool validateAsmConstraint(const char *&Name,
8638 TargetInfo::ConstraintInfo &Info) const override {
8642 bool hasProtectedVisibility() const override { return false; }
8645 class WebAssemblyTargetInfo : public TargetInfo {
8646 static const Builtin::Info BuiltinInfo[];
8654 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
8655 : TargetInfo(T), SIMDLevel(NoSIMD) {
8656 NoAsmVariants = true;
8657 SuitableAlign = 128;
8658 LargeArrayMinWidth = 128;
8659 LargeArrayAlign = 128;
8660 SimdDefaultAlign = 128;
8661 SigAtomicType = SignedLong;
8662 LongDoubleWidth = LongDoubleAlign = 128;
8663 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8664 SizeType = UnsignedInt;
8665 PtrDiffType = SignedInt;
8666 IntPtrType = SignedInt;
8670 void getTargetDefines(const LangOptions &Opts,
8671 MacroBuilder &Builder) const override {
8672 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
8673 if (SIMDLevel >= SIMD128)
8674 Builder.defineMacro("__wasm_simd128__");
8679 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
8681 const std::vector<std::string> &FeaturesVec) const override {
8682 if (CPU == "bleeding-edge")
8683 Features["simd128"] = true;
8684 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
8686 bool hasFeature(StringRef Feature) const final {
8687 return llvm::StringSwitch<bool>(Feature)
8688 .Case("simd128", SIMDLevel >= SIMD128)
8691 bool handleTargetFeatures(std::vector<std::string> &Features,
8692 DiagnosticsEngine &Diags) final {
8693 for (const auto &Feature : Features) {
8694 if (Feature == "+simd128") {
8695 SIMDLevel = std::max(SIMDLevel, SIMD128);
8698 if (Feature == "-simd128") {
8699 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
8703 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
8704 << "-target-feature";
8709 bool setCPU(const std::string &Name) final {
8710 return llvm::StringSwitch<bool>(Name)
8712 .Case("bleeding-edge", true)
8713 .Case("generic", true)
8716 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
8717 return llvm::makeArrayRef(BuiltinInfo,
8718 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
8720 BuiltinVaListKind getBuiltinVaListKind() const final {
8721 return VoidPtrBuiltinVaList;
8723 ArrayRef<const char *> getGCCRegNames() const final {
8726 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
8730 validateAsmConstraint(const char *&Name,
8731 TargetInfo::ConstraintInfo &Info) const final {
8734 const char *getClobbers() const final { return ""; }
8735 bool isCLZForZeroUndef() const final { return false; }
8736 bool hasInt128Type() const final { return true; }
8737 IntType getIntTypeByWidth(unsigned BitWidth,
8738 bool IsSigned) const final {
8739 // WebAssembly prefers long long for explicitly 64-bit integers.
8740 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8741 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
8743 IntType getLeastIntTypeByWidth(unsigned BitWidth,
8744 bool IsSigned) const final {
8745 // WebAssembly uses long long for int_least64_t and int_fast64_t.
8746 return BitWidth == 64
8747 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
8748 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
8752 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
8753 #define BUILTIN(ID, TYPE, ATTRS) \
8754 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8755 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8756 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8757 #include "clang/Basic/BuiltinsWebAssembly.def"
8760 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
8762 explicit WebAssembly32TargetInfo(const llvm::Triple &T,
8763 const TargetOptions &Opts)
8764 : WebAssemblyTargetInfo(T, Opts) {
8765 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8766 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
8770 void getTargetDefines(const LangOptions &Opts,
8771 MacroBuilder &Builder) const override {
8772 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8773 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
8777 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
8779 explicit WebAssembly64TargetInfo(const llvm::Triple &T,
8780 const TargetOptions &Opts)
8781 : WebAssemblyTargetInfo(T, Opts) {
8782 LongAlign = LongWidth = 64;
8783 PointerAlign = PointerWidth = 64;
8784 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
8785 SizeType = UnsignedLong;
8786 PtrDiffType = SignedLong;
8787 IntPtrType = SignedLong;
8788 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
8792 void getTargetDefines(const LangOptions &Opts,
8793 MacroBuilder &Builder) const override {
8794 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
8795 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
8799 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
8800 #define BUILTIN(ID, TYPE, ATTRS) \
8801 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8802 #include "clang/Basic/BuiltinsLe64.def"
8805 static const unsigned SPIRAddrSpaceMap[] = {
8809 2, // opencl_constant
8810 4, // opencl_generic
8815 class SPIRTargetInfo : public TargetInfo {
8817 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8818 : TargetInfo(Triple) {
8819 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
8820 "SPIR target must use unknown OS");
8821 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
8822 "SPIR target must use unknown environment type");
8823 TLSSupported = false;
8824 LongWidth = LongAlign = 64;
8825 AddrSpaceMap = &SPIRAddrSpaceMap;
8826 UseAddrSpaceMapMangling = true;
8827 // Define available target features
8828 // These must be defined in sorted order!
8829 NoAsmVariants = true;
8831 void getTargetDefines(const LangOptions &Opts,
8832 MacroBuilder &Builder) const override {
8833 DefineStd(Builder, "SPIR", Opts);
8835 bool hasFeature(StringRef Feature) const override {
8836 return Feature == "spir";
8839 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
8840 const char *getClobbers() const override { return ""; }
8841 ArrayRef<const char *> getGCCRegNames() const override { return None; }
8842 bool validateAsmConstraint(const char *&Name,
8843 TargetInfo::ConstraintInfo &info) const override {
8846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8849 BuiltinVaListKind getBuiltinVaListKind() const override {
8850 return TargetInfo::VoidPtrBuiltinVaList;
8853 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
8854 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
8858 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
8859 return CC_SpirFunction;
8862 void setSupportedOpenCLOpts() override {
8863 // Assume all OpenCL extensions and optional core features are supported
8864 // for SPIR since it is a generic target.
8865 getSupportedOpenCLOpts().supportAll();
8869 class SPIR32TargetInfo : public SPIRTargetInfo {
8871 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8872 : SPIRTargetInfo(Triple, Opts) {
8873 PointerWidth = PointerAlign = 32;
8874 SizeType = TargetInfo::UnsignedInt;
8875 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
8876 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
8877 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8879 void getTargetDefines(const LangOptions &Opts,
8880 MacroBuilder &Builder) const override {
8881 DefineStd(Builder, "SPIR32", Opts);
8885 class SPIR64TargetInfo : public SPIRTargetInfo {
8887 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8888 : SPIRTargetInfo(Triple, Opts) {
8889 PointerWidth = PointerAlign = 64;
8890 SizeType = TargetInfo::UnsignedLong;
8891 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
8892 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
8893 "v96:128-v192:256-v256:256-v512:512-v1024:1024");
8895 void getTargetDefines(const LangOptions &Opts,
8896 MacroBuilder &Builder) const override {
8897 DefineStd(Builder, "SPIR64", Opts);
8901 class XCoreTargetInfo : public TargetInfo {
8902 static const Builtin::Info BuiltinInfo[];
8904 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
8905 : TargetInfo(Triple) {
8906 NoAsmVariants = true;
8909 DoubleAlign = LongDoubleAlign = 32;
8910 SizeType = UnsignedInt;
8911 PtrDiffType = SignedInt;
8912 IntPtrType = SignedInt;
8913 WCharType = UnsignedChar;
8914 WIntType = UnsignedInt;
8915 UseZeroLengthBitfieldAlignment = true;
8916 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
8917 "-f64:32-a:0:32-n32");
8919 void getTargetDefines(const LangOptions &Opts,
8920 MacroBuilder &Builder) const override {
8921 Builder.defineMacro("__XS1B__");
8923 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
8924 return llvm::makeArrayRef(BuiltinInfo,
8925 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
8927 BuiltinVaListKind getBuiltinVaListKind() const override {
8928 return TargetInfo::VoidPtrBuiltinVaList;
8930 const char *getClobbers() const override {
8933 ArrayRef<const char *> getGCCRegNames() const override {
8934 static const char * const GCCRegNames[] = {
8935 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8936 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
8938 return llvm::makeArrayRef(GCCRegNames);
8940 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
8943 bool validateAsmConstraint(const char *&Name,
8944 TargetInfo::ConstraintInfo &Info) const override {
8947 int getEHDataRegisterNumber(unsigned RegNo) const override {
8948 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
8949 return (RegNo < 2)? RegNo : -1;
8951 bool allowsLargerPreferedTypeAlignment() const override {
8956 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
8957 #define BUILTIN(ID, TYPE, ATTRS) \
8958 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
8959 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
8960 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
8961 #include "clang/Basic/BuiltinsXCore.def"
8964 // x86_32 Android target
8965 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
8967 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8968 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
8970 LongDoubleWidth = 64;
8971 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
8975 // x86_64 Android target
8976 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
8978 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
8979 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
8980 LongDoubleFormat = &llvm::APFloat::IEEEquad();
8983 bool useFloat128ManglingForLongDouble() const override {
8988 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes
8989 class RenderScript32TargetInfo : public ARMleTargetInfo {
8991 RenderScript32TargetInfo(const llvm::Triple &Triple,
8992 const TargetOptions &Opts)
8993 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
8995 Triple.getEnvironmentName()),
8997 IsRenderScriptTarget = true;
8998 LongWidth = LongAlign = 64;
9000 void getTargetDefines(const LangOptions &Opts,
9001 MacroBuilder &Builder) const override {
9002 Builder.defineMacro("__RENDERSCRIPT__");
9003 ARMleTargetInfo::getTargetDefines(Opts, Builder);
9007 // 64-bit RenderScript is aarch64
9008 class RenderScript64TargetInfo : public AArch64leTargetInfo {
9010 RenderScript64TargetInfo(const llvm::Triple &Triple,
9011 const TargetOptions &Opts)
9012 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
9014 Triple.getEnvironmentName()),
9016 IsRenderScriptTarget = true;
9019 void getTargetDefines(const LangOptions &Opts,
9020 MacroBuilder &Builder) const override {
9021 Builder.defineMacro("__RENDERSCRIPT__");
9022 AArch64leTargetInfo::getTargetDefines(Opts, Builder);
9026 /// Information about a specific microcontroller.
9029 const char *DefineName;
9032 // This list should be kept up-to-date with AVRDevices.td in LLVM.
9033 static ArrayRef<MCUInfo> AVRMcus = {
9034 { "at90s1200", "__AVR_AT90S1200__" },
9035 { "attiny11", "__AVR_ATtiny11__" },
9036 { "attiny12", "__AVR_ATtiny12__" },
9037 { "attiny15", "__AVR_ATtiny15__" },
9038 { "attiny28", "__AVR_ATtiny28__" },
9039 { "at90s2313", "__AVR_AT90S2313__" },
9040 { "at90s2323", "__AVR_AT90S2323__" },
9041 { "at90s2333", "__AVR_AT90S2333__" },
9042 { "at90s2343", "__AVR_AT90S2343__" },
9043 { "attiny22", "__AVR_ATtiny22__" },
9044 { "attiny26", "__AVR_ATtiny26__" },
9045 { "at86rf401", "__AVR_AT86RF401__" },
9046 { "at90s4414", "__AVR_AT90S4414__" },
9047 { "at90s4433", "__AVR_AT90S4433__" },
9048 { "at90s4434", "__AVR_AT90S4434__" },
9049 { "at90s8515", "__AVR_AT90S8515__" },
9050 { "at90c8534", "__AVR_AT90c8534__" },
9051 { "at90s8535", "__AVR_AT90S8535__" },
9052 { "ata5272", "__AVR_ATA5272__" },
9053 { "attiny13", "__AVR_ATtiny13__" },
9054 { "attiny13a", "__AVR_ATtiny13A__" },
9055 { "attiny2313", "__AVR_ATtiny2313__" },
9056 { "attiny2313a", "__AVR_ATtiny2313A__" },
9057 { "attiny24", "__AVR_ATtiny24__" },
9058 { "attiny24a", "__AVR_ATtiny24A__" },
9059 { "attiny4313", "__AVR_ATtiny4313__" },
9060 { "attiny44", "__AVR_ATtiny44__" },
9061 { "attiny44a", "__AVR_ATtiny44A__" },
9062 { "attiny84", "__AVR_ATtiny84__" },
9063 { "attiny84a", "__AVR_ATtiny84A__" },
9064 { "attiny25", "__AVR_ATtiny25__" },
9065 { "attiny45", "__AVR_ATtiny45__" },
9066 { "attiny85", "__AVR_ATtiny85__" },
9067 { "attiny261", "__AVR_ATtiny261__" },
9068 { "attiny261a", "__AVR_ATtiny261A__" },
9069 { "attiny461", "__AVR_ATtiny461__" },
9070 { "attiny461a", "__AVR_ATtiny461A__" },
9071 { "attiny861", "__AVR_ATtiny861__" },
9072 { "attiny861a", "__AVR_ATtiny861A__" },
9073 { "attiny87", "__AVR_ATtiny87__" },
9074 { "attiny43u", "__AVR_ATtiny43U__" },
9075 { "attiny48", "__AVR_ATtiny48__" },
9076 { "attiny88", "__AVR_ATtiny88__" },
9077 { "attiny828", "__AVR_ATtiny828__" },
9078 { "at43usb355", "__AVR_AT43USB355__" },
9079 { "at76c711", "__AVR_AT76C711__" },
9080 { "atmega103", "__AVR_ATmega103__" },
9081 { "at43usb320", "__AVR_AT43USB320__" },
9082 { "attiny167", "__AVR_ATtiny167__" },
9083 { "at90usb82", "__AVR_AT90USB82__" },
9084 { "at90usb162", "__AVR_AT90USB162__" },
9085 { "ata5505", "__AVR_ATA5505__" },
9086 { "atmega8u2", "__AVR_ATmega8U2__" },
9087 { "atmega16u2", "__AVR_ATmega16U2__" },
9088 { "atmega32u2", "__AVR_ATmega32U2__" },
9089 { "attiny1634", "__AVR_ATtiny1634__" },
9090 { "atmega8", "__AVR_ATmega8__" },
9091 { "ata6289", "__AVR_ATA6289__" },
9092 { "atmega8a", "__AVR_ATmega8A__" },
9093 { "ata6285", "__AVR_ATA6285__" },
9094 { "ata6286", "__AVR_ATA6286__" },
9095 { "atmega48", "__AVR_ATmega48__" },
9096 { "atmega48a", "__AVR_ATmega48A__" },
9097 { "atmega48pa", "__AVR_ATmega48PA__" },
9098 { "atmega48p", "__AVR_ATmega48P__" },
9099 { "atmega88", "__AVR_ATmega88__" },
9100 { "atmega88a", "__AVR_ATmega88A__" },
9101 { "atmega88p", "__AVR_ATmega88P__" },
9102 { "atmega88pa", "__AVR_ATmega88PA__" },
9103 { "atmega8515", "__AVR_ATmega8515__" },
9104 { "atmega8535", "__AVR_ATmega8535__" },
9105 { "atmega8hva", "__AVR_ATmega8HVA__" },
9106 { "at90pwm1", "__AVR_AT90PWM1__" },
9107 { "at90pwm2", "__AVR_AT90PWM2__" },
9108 { "at90pwm2b", "__AVR_AT90PWM2B__" },
9109 { "at90pwm3", "__AVR_AT90PWM3__" },
9110 { "at90pwm3b", "__AVR_AT90PWM3B__" },
9111 { "at90pwm81", "__AVR_AT90PWM81__" },
9112 { "ata5790", "__AVR_ATA5790__" },
9113 { "ata5795", "__AVR_ATA5795__" },
9114 { "atmega16", "__AVR_ATmega16__" },
9115 { "atmega16a", "__AVR_ATmega16A__" },
9116 { "atmega161", "__AVR_ATmega161__" },
9117 { "atmega162", "__AVR_ATmega162__" },
9118 { "atmega163", "__AVR_ATmega163__" },
9119 { "atmega164a", "__AVR_ATmega164A__" },
9120 { "atmega164p", "__AVR_ATmega164P__" },
9121 { "atmega164pa", "__AVR_ATmega164PA__" },
9122 { "atmega165", "__AVR_ATmega165__" },
9123 { "atmega165a", "__AVR_ATmega165A__" },
9124 { "atmega165p", "__AVR_ATmega165P__" },
9125 { "atmega165pa", "__AVR_ATmega165PA__" },
9126 { "atmega168", "__AVR_ATmega168__" },
9127 { "atmega168a", "__AVR_ATmega168A__" },
9128 { "atmega168p", "__AVR_ATmega168P__" },
9129 { "atmega168pa", "__AVR_ATmega168PA__" },
9130 { "atmega169", "__AVR_ATmega169__" },
9131 { "atmega169a", "__AVR_ATmega169A__" },
9132 { "atmega169p", "__AVR_ATmega169P__" },
9133 { "atmega169pa", "__AVR_ATmega169PA__" },
9134 { "atmega32", "__AVR_ATmega32__" },
9135 { "atmega32a", "__AVR_ATmega32A__" },
9136 { "atmega323", "__AVR_ATmega323__" },
9137 { "atmega324a", "__AVR_ATmega324A__" },
9138 { "atmega324p", "__AVR_ATmega324P__" },
9139 { "atmega324pa", "__AVR_ATmega324PA__" },
9140 { "atmega325", "__AVR_ATmega325__" },
9141 { "atmega325a", "__AVR_ATmega325A__" },
9142 { "atmega325p", "__AVR_ATmega325P__" },
9143 { "atmega325pa", "__AVR_ATmega325PA__" },
9144 { "atmega3250", "__AVR_ATmega3250__" },
9145 { "atmega3250a", "__AVR_ATmega3250A__" },
9146 { "atmega3250p", "__AVR_ATmega3250P__" },
9147 { "atmega3250pa", "__AVR_ATmega3250PA__" },
9148 { "atmega328", "__AVR_ATmega328__" },
9149 { "atmega328p", "__AVR_ATmega328P__" },
9150 { "atmega329", "__AVR_ATmega329__" },
9151 { "atmega329a", "__AVR_ATmega329A__" },
9152 { "atmega329p", "__AVR_ATmega329P__" },
9153 { "atmega329pa", "__AVR_ATmega329PA__" },
9154 { "atmega3290", "__AVR_ATmega3290__" },
9155 { "atmega3290a", "__AVR_ATmega3290A__" },
9156 { "atmega3290p", "__AVR_ATmega3290P__" },
9157 { "atmega3290pa", "__AVR_ATmega3290PA__" },
9158 { "atmega406", "__AVR_ATmega406__" },
9159 { "atmega64", "__AVR_ATmega64__" },
9160 { "atmega64a", "__AVR_ATmega64A__" },
9161 { "atmega640", "__AVR_ATmega640__" },
9162 { "atmega644", "__AVR_ATmega644__" },
9163 { "atmega644a", "__AVR_ATmega644A__" },
9164 { "atmega644p", "__AVR_ATmega644P__" },
9165 { "atmega644pa", "__AVR_ATmega644PA__" },
9166 { "atmega645", "__AVR_ATmega645__" },
9167 { "atmega645a", "__AVR_ATmega645A__" },
9168 { "atmega645p", "__AVR_ATmega645P__" },
9169 { "atmega649", "__AVR_ATmega649__" },
9170 { "atmega649a", "__AVR_ATmega649A__" },
9171 { "atmega649p", "__AVR_ATmega649P__" },
9172 { "atmega6450", "__AVR_ATmega6450__" },
9173 { "atmega6450a", "__AVR_ATmega6450A__" },
9174 { "atmega6450p", "__AVR_ATmega6450P__" },
9175 { "atmega6490", "__AVR_ATmega6490__" },
9176 { "atmega6490a", "__AVR_ATmega6490A__" },
9177 { "atmega6490p", "__AVR_ATmega6490P__" },
9178 { "atmega64rfr2", "__AVR_ATmega64RFR2__" },
9179 { "atmega644rfr2", "__AVR_ATmega644RFR2__" },
9180 { "atmega16hva", "__AVR_ATmega16HVA__" },
9181 { "atmega16hva2", "__AVR_ATmega16HVA2__" },
9182 { "atmega16hvb", "__AVR_ATmega16HVB__" },
9183 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" },
9184 { "atmega32hvb", "__AVR_ATmega32HVB__" },
9185 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" },
9186 { "atmega64hve", "__AVR_ATmega64HVE__" },
9187 { "at90can32", "__AVR_AT90CAN32__" },
9188 { "at90can64", "__AVR_AT90CAN64__" },
9189 { "at90pwm161", "__AVR_AT90PWM161__" },
9190 { "at90pwm216", "__AVR_AT90PWM216__" },
9191 { "at90pwm316", "__AVR_AT90PWM316__" },
9192 { "atmega32c1", "__AVR_ATmega32C1__" },
9193 { "atmega64c1", "__AVR_ATmega64C1__" },
9194 { "atmega16m1", "__AVR_ATmega16M1__" },
9195 { "atmega32m1", "__AVR_ATmega32M1__" },
9196 { "atmega64m1", "__AVR_ATmega64M1__" },
9197 { "atmega16u4", "__AVR_ATmega16U4__" },
9198 { "atmega32u4", "__AVR_ATmega32U4__" },
9199 { "atmega32u6", "__AVR_ATmega32U6__" },
9200 { "at90usb646", "__AVR_AT90USB646__" },
9201 { "at90usb647", "__AVR_AT90USB647__" },
9202 { "at90scr100", "__AVR_AT90SCR100__" },
9203 { "at94k", "__AVR_AT94K__" },
9204 { "m3000", "__AVR_AT000__" },
9205 { "atmega128", "__AVR_ATmega128__" },
9206 { "atmega128a", "__AVR_ATmega128A__" },
9207 { "atmega1280", "__AVR_ATmega1280__" },
9208 { "atmega1281", "__AVR_ATmega1281__" },
9209 { "atmega1284", "__AVR_ATmega1284__" },
9210 { "atmega1284p", "__AVR_ATmega1284P__" },
9211 { "atmega128rfa1", "__AVR_ATmega128RFA1__" },
9212 { "atmega128rfr2", "__AVR_ATmega128RFR2__" },
9213 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" },
9214 { "at90can128", "__AVR_AT90CAN128__" },
9215 { "at90usb1286", "__AVR_AT90USB1286__" },
9216 { "at90usb1287", "__AVR_AT90USB1287__" },
9217 { "atmega2560", "__AVR_ATmega2560__" },
9218 { "atmega2561", "__AVR_ATmega2561__" },
9219 { "atmega256rfr2", "__AVR_ATmega256RFR2__" },
9220 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" },
9221 { "atxmega16a4", "__AVR_ATxmega16A4__" },
9222 { "atxmega16a4u", "__AVR_ATxmega16a4U__" },
9223 { "atxmega16c4", "__AVR_ATxmega16C4__" },
9224 { "atxmega16d4", "__AVR_ATxmega16D4__" },
9225 { "atxmega32a4", "__AVR_ATxmega32A4__" },
9226 { "atxmega32a4u", "__AVR_ATxmega32A4U__" },
9227 { "atxmega32c4", "__AVR_ATxmega32C4__" },
9228 { "atxmega32d4", "__AVR_ATxmega32D4__" },
9229 { "atxmega32e5", "__AVR_ATxmega32E5__" },
9230 { "atxmega16e5", "__AVR_ATxmega16E5__" },
9231 { "atxmega8e5", "__AVR_ATxmega8E5__" },
9232 { "atxmega32x1", "__AVR_ATxmega32X1__" },
9233 { "atxmega64a3", "__AVR_ATxmega64A3__" },
9234 { "atxmega64a3u", "__AVR_ATxmega64A3U__" },
9235 { "atxmega64a4u", "__AVR_ATxmega64A4U__" },
9236 { "atxmega64b1", "__AVR_ATxmega64B1__" },
9237 { "atxmega64b3", "__AVR_ATxmega64B3__" },
9238 { "atxmega64c3", "__AVR_ATxmega64C3__" },
9239 { "atxmega64d3", "__AVR_ATxmega64D3__" },
9240 { "atxmega64d4", "__AVR_ATxmega64D4__" },
9241 { "atxmega64a1", "__AVR_ATxmega64A1__" },
9242 { "atxmega64a1u", "__AVR_ATxmega64A1U__" },
9243 { "atxmega128a3", "__AVR_ATxmega128A3__" },
9244 { "atxmega128a3u", "__AVR_ATxmega128A3U__" },
9245 { "atxmega128b1", "__AVR_ATxmega128B1__" },
9246 { "atxmega128b3", "__AVR_ATxmega128B3__" },
9247 { "atxmega128c3", "__AVR_ATxmega128C3__" },
9248 { "atxmega128d3", "__AVR_ATxmega128D3__" },
9249 { "atxmega128d4", "__AVR_ATxmega128D4__" },
9250 { "atxmega192a3", "__AVR_ATxmega192A3__" },
9251 { "atxmega192a3u", "__AVR_ATxmega192A3U__" },
9252 { "atxmega192c3", "__AVR_ATxmega192C3__" },
9253 { "atxmega192d3", "__AVR_ATxmega192D3__" },
9254 { "atxmega256a3", "__AVR_ATxmega256A3__" },
9255 { "atxmega256a3u", "__AVR_ATxmega256A3U__" },
9256 { "atxmega256a3b", "__AVR_ATxmega256A3B__" },
9257 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" },
9258 { "atxmega256c3", "__AVR_ATxmega256C3__" },
9259 { "atxmega256d3", "__AVR_ATxmega256D3__" },
9260 { "atxmega384c3", "__AVR_ATxmega384C3__" },
9261 { "atxmega384d3", "__AVR_ATxmega384D3__" },
9262 { "atxmega128a1", "__AVR_ATxmega128A1__" },
9263 { "atxmega128a1u", "__AVR_ATxmega128A1U__" },
9264 { "atxmega128a4u", "__AVR_ATxmega128a4U__" },
9265 { "attiny4", "__AVR_ATtiny4__" },
9266 { "attiny5", "__AVR_ATtiny5__" },
9267 { "attiny9", "__AVR_ATtiny9__" },
9268 { "attiny10", "__AVR_ATtiny10__" },
9269 { "attiny20", "__AVR_ATtiny20__" },
9270 { "attiny40", "__AVR_ATtiny40__" },
9271 { "attiny102", "__AVR_ATtiny102__" },
9272 { "attiny104", "__AVR_ATtiny104__" },
9276 class AVRTargetInfo : public TargetInfo {
9278 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
9279 : TargetInfo(Triple) {
9280 TLSSupported = false;
9290 DefaultAlignForAttributeAligned = 8;
9297 DoubleFormat = &llvm::APFloat::IEEEsingle();
9298 LongDoubleWidth = 32;
9299 LongDoubleAlign = 8;
9300 LongDoubleFormat = &llvm::APFloat::IEEEsingle();
9301 SizeType = UnsignedInt;
9302 PtrDiffType = SignedInt;
9303 IntPtrType = SignedInt;
9304 Char16Type = UnsignedInt;
9305 WCharType = SignedInt;
9306 WIntType = SignedInt;
9307 Char32Type = UnsignedLong;
9308 SigAtomicType = SignedChar;
9309 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
9310 "-f32:32:32-f64:64:64-n8");
9313 void getTargetDefines(const LangOptions &Opts,
9314 MacroBuilder &Builder) const override {
9315 Builder.defineMacro("AVR");
9316 Builder.defineMacro("__AVR");
9317 Builder.defineMacro("__AVR__");
9319 if (!this->CPU.empty()) {
9320 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9321 [&](const MCUInfo &Info) { return Info.Name == this->CPU; });
9323 if (It != AVRMcus.end())
9324 Builder.defineMacro(It->DefineName);
9328 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
9332 BuiltinVaListKind getBuiltinVaListKind() const override {
9333 return TargetInfo::VoidPtrBuiltinVaList;
9336 const char *getClobbers() const override {
9340 ArrayRef<const char *> getGCCRegNames() const override {
9341 static const char * const GCCRegNames[] = {
9342 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9343 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
9344 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
9345 "r24", "r25", "X", "Y", "Z", "SP"
9347 return llvm::makeArrayRef(GCCRegNames);
9350 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
9354 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
9355 static const TargetInfo::AddlRegName AddlRegNames[] = {
9356 { { "r26", "r27"}, 26 },
9357 { { "r28", "r29"}, 27 },
9358 { { "r30", "r31"}, 28 },
9359 { { "SPL", "SPH"}, 29 },
9361 return llvm::makeArrayRef(AddlRegNames);
9364 bool validateAsmConstraint(const char *&Name,
9365 TargetInfo::ConstraintInfo &Info) const override {
9366 // There aren't any multi-character AVR specific constraints.
9367 if (StringRef(Name).size() > 1) return false;
9370 default: return false;
9371 case 'a': // Simple upper registers
9372 case 'b': // Base pointer registers pairs
9373 case 'd': // Upper register
9374 case 'l': // Lower registers
9375 case 'e': // Pointer register pairs
9376 case 'q': // Stack pointer register
9377 case 'r': // Any register
9378 case 'w': // Special upper register pairs
9379 case 't': // Temporary register
9380 case 'x': case 'X': // Pointer register pair X
9381 case 'y': case 'Y': // Pointer register pair Y
9382 case 'z': case 'Z': // Pointer register pair Z
9383 Info.setAllowsRegister();
9385 case 'I': // 6-bit positive integer constant
9386 Info.setRequiresImmediate(0, 63);
9388 case 'J': // 6-bit negative integer constant
9389 Info.setRequiresImmediate(-63, 0);
9391 case 'K': // Integer constant (Range: 2)
9392 Info.setRequiresImmediate(2);
9394 case 'L': // Integer constant (Range: 0)
9395 Info.setRequiresImmediate(0);
9397 case 'M': // 8-bit integer constant
9398 Info.setRequiresImmediate(0, 0xff);
9400 case 'N': // Integer constant (Range: -1)
9401 Info.setRequiresImmediate(-1);
9403 case 'O': // Integer constant (Range: 8, 16, 24)
9404 Info.setRequiresImmediate({8, 16, 24});
9406 case 'P': // Integer constant (Range: 1)
9407 Info.setRequiresImmediate(1);
9409 case 'R': // Integer constant (Range: -6 to 5)
9410 Info.setRequiresImmediate(-6, 5);
9412 case 'G': // Floating point constant
9413 case 'Q': // A memory address based on Y or Z pointer with displacement.
9420 IntType getIntTypeByWidth(unsigned BitWidth,
9421 bool IsSigned) const final {
9422 // AVR prefers int for 16-bit integers.
9423 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt)
9424 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
9427 IntType getLeastIntTypeByWidth(unsigned BitWidth,
9428 bool IsSigned) const final {
9429 // AVR uses int for int_least16_t and int_fast16_t.
9430 return BitWidth == 16
9431 ? (IsSigned ? SignedInt : UnsignedInt)
9432 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
9435 bool setCPU(const std::string &Name) override {
9436 bool IsFamily = llvm::StringSwitch<bool>(Name)
9439 .Case("avr25", true)
9441 .Case("avr31", true)
9442 .Case("avr35", true)
9445 .Case("avr51", true)
9447 .Case("avrxmega1", true)
9448 .Case("avrxmega2", true)
9449 .Case("avrxmega3", true)
9450 .Case("avrxmega4", true)
9451 .Case("avrxmega5", true)
9452 .Case("avrxmega6", true)
9453 .Case("avrxmega7", true)
9454 .Case("avrtiny", true)
9457 if (IsFamily) this->CPU = Name;
9459 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(),
9460 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end();
9462 if (IsMCU) this->CPU = Name;
9464 return IsFamily || IsMCU;
9471 } // end anonymous namespace
9473 //===----------------------------------------------------------------------===//
9475 //===----------------------------------------------------------------------===//
9477 static TargetInfo *AllocateTarget(const llvm::Triple &Triple,
9478 const TargetOptions &Opts) {
9479 llvm::Triple::OSType os = Triple.getOS();
9481 switch (Triple.getArch()) {
9485 case llvm::Triple::xcore:
9486 return new XCoreTargetInfo(Triple, Opts);
9488 case llvm::Triple::hexagon:
9489 return new HexagonTargetInfo(Triple, Opts);
9491 case llvm::Triple::lanai:
9492 return new LanaiTargetInfo(Triple, Opts);
9494 case llvm::Triple::aarch64:
9495 if (Triple.isOSDarwin())
9496 return new DarwinAArch64TargetInfo(Triple, Opts);
9499 case llvm::Triple::CloudABI:
9500 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts);
9501 case llvm::Triple::FreeBSD:
9502 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9503 case llvm::Triple::Fuchsia:
9504 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9505 case llvm::Triple::Linux:
9506 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9507 case llvm::Triple::NetBSD:
9508 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9509 case llvm::Triple::OpenBSD:
9510 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts);
9511 case llvm::Triple::Win32:
9512 return new MicrosoftARM64TargetInfo(Triple, Opts);
9514 return new AArch64leTargetInfo(Triple, Opts);
9517 case llvm::Triple::aarch64_be:
9519 case llvm::Triple::FreeBSD:
9520 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9521 case llvm::Triple::Fuchsia:
9522 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9523 case llvm::Triple::Linux:
9524 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9525 case llvm::Triple::NetBSD:
9526 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts);
9528 return new AArch64beTargetInfo(Triple, Opts);
9531 case llvm::Triple::arm:
9532 case llvm::Triple::thumb:
9533 if (Triple.isOSBinFormatMachO())
9534 return new DarwinARMTargetInfo(Triple, Opts);
9537 case llvm::Triple::CloudABI:
9538 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts);
9539 case llvm::Triple::Linux:
9540 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts);
9541 case llvm::Triple::FreeBSD:
9542 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9543 case llvm::Triple::NetBSD:
9544 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9545 case llvm::Triple::OpenBSD:
9546 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
9547 case llvm::Triple::Bitrig:
9548 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts);
9549 case llvm::Triple::RTEMS:
9550 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
9551 case llvm::Triple::NaCl:
9552 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
9553 case llvm::Triple::Win32:
9554 switch (Triple.getEnvironment()) {
9555 case llvm::Triple::Cygnus:
9556 return new CygwinARMTargetInfo(Triple, Opts);
9557 case llvm::Triple::GNU:
9558 return new MinGWARMTargetInfo(Triple, Opts);
9559 case llvm::Triple::Itanium:
9560 return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
9561 case llvm::Triple::MSVC:
9562 default: // Assume MSVC for unknown environments
9563 return new MicrosoftARMleTargetInfo(Triple, Opts);
9566 return new ARMleTargetInfo(Triple, Opts);
9569 case llvm::Triple::armeb:
9570 case llvm::Triple::thumbeb:
9571 if (Triple.isOSDarwin())
9572 return new DarwinARMTargetInfo(Triple, Opts);
9575 case llvm::Triple::Linux:
9576 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9577 case llvm::Triple::FreeBSD:
9578 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9579 case llvm::Triple::NetBSD:
9580 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9581 case llvm::Triple::OpenBSD:
9582 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9583 case llvm::Triple::Bitrig:
9584 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9585 case llvm::Triple::RTEMS:
9586 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9587 case llvm::Triple::NaCl:
9588 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
9590 return new ARMbeTargetInfo(Triple, Opts);
9593 case llvm::Triple::avr:
9594 return new AVRTargetInfo(Triple, Opts);
9595 case llvm::Triple::bpfeb:
9596 case llvm::Triple::bpfel:
9597 return new BPFTargetInfo(Triple, Opts);
9599 case llvm::Triple::msp430:
9600 return new MSP430TargetInfo(Triple, Opts);
9602 case llvm::Triple::nios2:
9603 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts);
9605 case llvm::Triple::mips:
9607 case llvm::Triple::Linux:
9608 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9609 case llvm::Triple::RTEMS:
9610 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9611 case llvm::Triple::FreeBSD:
9612 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9613 case llvm::Triple::NetBSD:
9614 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9616 return new MipsTargetInfo(Triple, Opts);
9619 case llvm::Triple::mipsel:
9621 case llvm::Triple::Linux:
9622 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9623 case llvm::Triple::RTEMS:
9624 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9625 case llvm::Triple::FreeBSD:
9626 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9627 case llvm::Triple::NetBSD:
9628 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9629 case llvm::Triple::NaCl:
9630 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
9632 return new MipsTargetInfo(Triple, Opts);
9635 case llvm::Triple::mips64:
9637 case llvm::Triple::Linux:
9638 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9639 case llvm::Triple::RTEMS:
9640 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9641 case llvm::Triple::FreeBSD:
9642 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9643 case llvm::Triple::NetBSD:
9644 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9645 case llvm::Triple::OpenBSD:
9646 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9648 return new MipsTargetInfo(Triple, Opts);
9651 case llvm::Triple::mips64el:
9653 case llvm::Triple::Linux:
9654 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
9655 case llvm::Triple::RTEMS:
9656 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
9657 case llvm::Triple::FreeBSD:
9658 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9659 case llvm::Triple::NetBSD:
9660 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9661 case llvm::Triple::OpenBSD:
9662 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
9664 return new MipsTargetInfo(Triple, Opts);
9667 case llvm::Triple::le32:
9669 case llvm::Triple::NaCl:
9670 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
9675 case llvm::Triple::le64:
9676 return new Le64TargetInfo(Triple, Opts);
9678 case llvm::Triple::ppc:
9679 if (Triple.isOSDarwin())
9680 return new DarwinPPC32TargetInfo(Triple, Opts);
9682 case llvm::Triple::Linux:
9683 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
9684 case llvm::Triple::FreeBSD:
9685 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9686 case llvm::Triple::NetBSD:
9687 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9688 case llvm::Triple::OpenBSD:
9689 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
9690 case llvm::Triple::RTEMS:
9691 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts);
9693 return new PPC32TargetInfo(Triple, Opts);
9696 case llvm::Triple::ppc64:
9697 if (Triple.isOSDarwin())
9698 return new DarwinPPC64TargetInfo(Triple, Opts);
9700 case llvm::Triple::Linux:
9701 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9702 case llvm::Triple::Lv2:
9703 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts);
9704 case llvm::Triple::FreeBSD:
9705 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9706 case llvm::Triple::NetBSD:
9707 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9709 return new PPC64TargetInfo(Triple, Opts);
9712 case llvm::Triple::ppc64le:
9714 case llvm::Triple::Linux:
9715 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts);
9716 case llvm::Triple::NetBSD:
9717 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts);
9719 return new PPC64TargetInfo(Triple, Opts);
9722 case llvm::Triple::nvptx:
9723 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32);
9724 case llvm::Triple::nvptx64:
9725 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
9727 case llvm::Triple::amdgcn:
9728 case llvm::Triple::r600:
9729 return new AMDGPUTargetInfo(Triple, Opts);
9731 case llvm::Triple::sparc:
9733 case llvm::Triple::Linux:
9734 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9735 case llvm::Triple::Solaris:
9736 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9737 case llvm::Triple::NetBSD:
9738 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9739 case llvm::Triple::OpenBSD:
9740 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9741 case llvm::Triple::RTEMS:
9742 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts);
9744 return new SparcV8TargetInfo(Triple, Opts);
9747 // The 'sparcel' architecture copies all the above cases except for Solaris.
9748 case llvm::Triple::sparcel:
9750 case llvm::Triple::Linux:
9751 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9752 case llvm::Triple::NetBSD:
9753 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9754 case llvm::Triple::OpenBSD:
9755 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9756 case llvm::Triple::RTEMS:
9757 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts);
9759 return new SparcV8elTargetInfo(Triple, Opts);
9762 case llvm::Triple::sparcv9:
9764 case llvm::Triple::Linux:
9765 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9766 case llvm::Triple::Solaris:
9767 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9768 case llvm::Triple::NetBSD:
9769 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9770 case llvm::Triple::OpenBSD:
9771 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9772 case llvm::Triple::FreeBSD:
9773 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts);
9775 return new SparcV9TargetInfo(Triple, Opts);
9778 case llvm::Triple::systemz:
9780 case llvm::Triple::Linux:
9781 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts);
9783 return new SystemZTargetInfo(Triple, Opts);
9786 case llvm::Triple::tce:
9787 return new TCETargetInfo(Triple, Opts);
9789 case llvm::Triple::tcele:
9790 return new TCELETargetInfo(Triple, Opts);
9792 case llvm::Triple::x86:
9793 if (Triple.isOSDarwin())
9794 return new DarwinI386TargetInfo(Triple, Opts);
9797 case llvm::Triple::Ananas:
9798 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts);
9799 case llvm::Triple::CloudABI:
9800 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts);
9801 case llvm::Triple::Linux: {
9802 switch (Triple.getEnvironment()) {
9804 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts);
9805 case llvm::Triple::Android:
9806 return new AndroidX86_32TargetInfo(Triple, Opts);
9809 case llvm::Triple::DragonFly:
9810 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9811 case llvm::Triple::NetBSD:
9812 return new NetBSDI386TargetInfo(Triple, Opts);
9813 case llvm::Triple::OpenBSD:
9814 return new OpenBSDI386TargetInfo(Triple, Opts);
9815 case llvm::Triple::Bitrig:
9816 return new BitrigI386TargetInfo(Triple, Opts);
9817 case llvm::Triple::FreeBSD:
9818 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9819 case llvm::Triple::KFreeBSD:
9820 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts);
9821 case llvm::Triple::Minix:
9822 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts);
9823 case llvm::Triple::Solaris:
9824 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts);
9825 case llvm::Triple::Win32: {
9826 switch (Triple.getEnvironment()) {
9827 case llvm::Triple::Cygnus:
9828 return new CygwinX86_32TargetInfo(Triple, Opts);
9829 case llvm::Triple::GNU:
9830 return new MinGWX86_32TargetInfo(Triple, Opts);
9831 case llvm::Triple::Itanium:
9832 case llvm::Triple::MSVC:
9833 default: // Assume MSVC for unknown environments
9834 return new MicrosoftX86_32TargetInfo(Triple, Opts);
9837 case llvm::Triple::Haiku:
9838 return new HaikuX86_32TargetInfo(Triple, Opts);
9839 case llvm::Triple::RTEMS:
9840 return new RTEMSX86_32TargetInfo(Triple, Opts);
9841 case llvm::Triple::NaCl:
9842 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
9843 case llvm::Triple::ELFIAMCU:
9844 return new MCUX86_32TargetInfo(Triple, Opts);
9846 return new X86_32TargetInfo(Triple, Opts);
9849 case llvm::Triple::x86_64:
9850 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
9851 return new DarwinX86_64TargetInfo(Triple, Opts);
9854 case llvm::Triple::Ananas:
9855 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts);
9856 case llvm::Triple::CloudABI:
9857 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts);
9858 case llvm::Triple::Linux: {
9859 switch (Triple.getEnvironment()) {
9861 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts);
9862 case llvm::Triple::Android:
9863 return new AndroidX86_64TargetInfo(Triple, Opts);
9866 case llvm::Triple::DragonFly:
9867 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9868 case llvm::Triple::NetBSD:
9869 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9870 case llvm::Triple::OpenBSD:
9871 return new OpenBSDX86_64TargetInfo(Triple, Opts);
9872 case llvm::Triple::Bitrig:
9873 return new BitrigX86_64TargetInfo(Triple, Opts);
9874 case llvm::Triple::FreeBSD:
9875 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9876 case llvm::Triple::Fuchsia:
9877 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts);
9878 case llvm::Triple::KFreeBSD:
9879 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts);
9880 case llvm::Triple::Solaris:
9881 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts);
9882 case llvm::Triple::Win32: {
9883 switch (Triple.getEnvironment()) {
9884 case llvm::Triple::Cygnus:
9885 return new CygwinX86_64TargetInfo(Triple, Opts);
9886 case llvm::Triple::GNU:
9887 return new MinGWX86_64TargetInfo(Triple, Opts);
9888 case llvm::Triple::MSVC:
9889 default: // Assume MSVC for unknown environments
9890 return new MicrosoftX86_64TargetInfo(Triple, Opts);
9893 case llvm::Triple::Haiku:
9894 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
9895 case llvm::Triple::NaCl:
9896 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
9897 case llvm::Triple::PS4:
9898 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
9900 return new X86_64TargetInfo(Triple, Opts);
9903 case llvm::Triple::spir: {
9904 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9905 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9907 return new SPIR32TargetInfo(Triple, Opts);
9909 case llvm::Triple::spir64: {
9910 if (Triple.getOS() != llvm::Triple::UnknownOS ||
9911 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
9913 return new SPIR64TargetInfo(Triple, Opts);
9915 case llvm::Triple::wasm32:
9916 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9917 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9918 Triple.getOS() != llvm::Triple::UnknownOS ||
9919 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9920 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9922 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts);
9923 case llvm::Triple::wasm64:
9924 if (Triple.getSubArch() != llvm::Triple::NoSubArch ||
9925 Triple.getVendor() != llvm::Triple::UnknownVendor ||
9926 Triple.getOS() != llvm::Triple::UnknownOS ||
9927 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment ||
9928 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm()))
9930 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts);
9932 case llvm::Triple::renderscript32:
9933 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts);
9934 case llvm::Triple::renderscript64:
9935 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts);
9939 /// CreateTargetInfo - Return the target info object for the specified target
9942 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
9943 const std::shared_ptr<TargetOptions> &Opts) {
9944 llvm::Triple Triple(Opts->Triple);
9946 // Construct the target
9947 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts));
9949 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
9952 Target->TargetOpts = Opts;
9954 // Set the target CPU if specified.
9955 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
9956 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
9960 // Set the target ABI if specified.
9961 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
9962 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
9966 // Set the fp math unit.
9967 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
9968 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
9972 // Compute the default target features, we need the target to handle this
9973 // because features may have dependencies on one another.
9974 llvm::StringMap<bool> Features;
9975 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
9976 Opts->FeaturesAsWritten))
9979 // Add the features to the compile options.
9980 Opts->Features.clear();
9981 for (const auto &F : Features)
9982 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
9984 if (!Target->handleTargetFeatures(Opts->Features, Diags))
9987 Target->setSupportedOpenCLOpts();
9988 Target->setOpenCLExtensionOpts();
9990 if (!Target->validateTarget(Diags))
9993 return Target.release();