1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
26 #include "llvm/CodeGen/MIRYamlMapping.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
46 #include "llvm/IR/IRPrintingPasses.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/ModuleSlotTracker.h"
52 #include "llvm/IR/Value.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
78 static cl::opt<bool> SimplifyMIR(
79 "simplify-mir", cl::Hidden,
80 cl::desc("Leave out unnecessary information when printing MIR"));
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
90 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
93 /// Return an ordinary stack object reference.
94 static FrameIndexOperand create(StringRef Name, unsigned ID) {
95 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
98 /// Return a fixed stack object reference.
99 static FrameIndexOperand createFixed(unsigned ID) {
100 return FrameIndexOperand("", ID, /*IsFixed=*/true);
104 } // end anonymous namespace
108 /// This class prints out the machine functions using the MIR serialization
112 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113 /// Maps from stack object indices to operand indices which will be used when
114 /// printing frame index machine operands.
115 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
118 MIRPrinter(raw_ostream &OS) : OS(OS) {}
120 void print(const MachineFunction &MF);
122 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123 const TargetRegisterInfo *TRI);
124 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125 const MachineFrameInfo &MFI);
126 void convert(yaml::MachineFunction &MF,
127 const MachineConstantPool &ConstantPool);
128 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129 const MachineJumpTableInfo &JTI);
130 void convertStackObjects(yaml::MachineFunction &YMF,
131 const MachineFunction &MF, ModuleSlotTracker &MST);
134 void initRegisterMaskIds(const MachineFunction &MF);
137 /// This class prints out the machine instructions using the MIR serialization
141 ModuleSlotTracker &MST;
142 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144 /// Synchronization scope names registered with LLVMContext.
145 SmallVector<StringRef, 8> SSNs;
147 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148 bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
151 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155 StackObjectOperandMapping(StackObjectOperandMapping) {}
157 void print(const MachineBasicBlock &MBB);
159 void print(const MachineInstr &MI);
160 void printIRValueReference(const Value &V);
161 void printStackObjectReference(int FrameIndex);
162 void print(const MachineInstr &MI, unsigned OpIdx,
163 const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
164 LLT TypeToPrint, bool PrintDef = true);
165 void print(const LLVMContext &Context, const TargetInstrInfo &TII,
166 const MachineMemOperand &Op);
167 void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
170 } // end namespace llvm
175 /// This struct serializes the LLVM IR module.
176 template <> struct BlockScalarTraits<Module> {
177 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
178 Mod.print(OS, nullptr);
181 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
182 llvm_unreachable("LLVM Module is supposed to be parsed separately");
187 } // end namespace yaml
188 } // end namespace llvm
190 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
191 const TargetRegisterInfo *TRI) {
192 raw_string_ostream OS(Dest.Value);
193 OS << printReg(Reg, TRI);
196 void MIRPrinter::print(const MachineFunction &MF) {
197 initRegisterMaskIds(MF);
199 yaml::MachineFunction YamlMF;
200 YamlMF.Name = MF.getName();
201 YamlMF.Alignment = MF.getAlignment();
202 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
204 YamlMF.Legalized = MF.getProperties().hasProperty(
205 MachineFunctionProperties::Property::Legalized);
206 YamlMF.RegBankSelected = MF.getProperties().hasProperty(
207 MachineFunctionProperties::Property::RegBankSelected);
208 YamlMF.Selected = MF.getProperties().hasProperty(
209 MachineFunctionProperties::Property::Selected);
211 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
212 ModuleSlotTracker MST(MF.getFunction().getParent());
213 MST.incorporateFunction(MF.getFunction());
214 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
215 convertStackObjects(YamlMF, MF, MST);
216 if (const auto *ConstantPool = MF.getConstantPool())
217 convert(YamlMF, *ConstantPool);
218 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
219 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
220 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
221 bool IsNewlineNeeded = false;
222 for (const auto &MBB : MF) {
225 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
227 IsNewlineNeeded = true;
230 yaml::Output Out(OS);
232 Out.setWriteDefaultValues(true);
236 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
237 const TargetRegisterInfo *TRI) {
238 assert(RegMask && "Can't print an empty register mask");
239 OS << StringRef("CustomRegMask(");
241 bool IsRegInRegMaskFound = false;
242 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
243 // Check whether the register is asserted in regmask.
244 if (RegMask[I / 32] & (1u << (I % 32))) {
245 if (IsRegInRegMaskFound)
247 OS << printReg(I, TRI);
248 IsRegInRegMaskFound = true;
255 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
256 const MachineRegisterInfo &RegInfo,
257 const TargetRegisterInfo *TRI) {
258 raw_string_ostream OS(Dest.Value);
259 OS << printRegClassOrBank(Reg, RegInfo, TRI);
263 void MIRPrinter::convert(yaml::MachineFunction &MF,
264 const MachineRegisterInfo &RegInfo,
265 const TargetRegisterInfo *TRI) {
266 MF.TracksRegLiveness = RegInfo.tracksLiveness();
268 // Print the virtual register definitions.
269 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
270 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
271 yaml::VirtualRegisterDefinition VReg;
273 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
274 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
276 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
277 MF.VirtualRegisters.push_back(VReg);
280 // Print the live ins.
281 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
282 yaml::MachineFunctionLiveIn LiveIn;
283 printRegMIR(LI.first, LiveIn.Register, TRI);
285 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
286 MF.LiveIns.push_back(LiveIn);
289 // Prints the callee saved registers.
290 if (RegInfo.isUpdatedCSRsInitialized()) {
291 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
292 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
293 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
294 yaml::FlowStringValue Reg;
295 printRegMIR(*I, Reg, TRI);
296 CalleeSavedRegisters.push_back(Reg);
298 MF.CalleeSavedRegisters = CalleeSavedRegisters;
302 void MIRPrinter::convert(ModuleSlotTracker &MST,
303 yaml::MachineFrameInfo &YamlMFI,
304 const MachineFrameInfo &MFI) {
305 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
306 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
307 YamlMFI.HasStackMap = MFI.hasStackMap();
308 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
309 YamlMFI.StackSize = MFI.getStackSize();
310 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
311 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
312 YamlMFI.AdjustsStack = MFI.adjustsStack();
313 YamlMFI.HasCalls = MFI.hasCalls();
314 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
315 ? MFI.getMaxCallFrameSize() : ~0u;
316 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
317 YamlMFI.HasVAStart = MFI.hasVAStart();
318 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
319 if (MFI.getSavePoint()) {
320 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
321 StrOS << printMBBReference(*MFI.getSavePoint());
323 if (MFI.getRestorePoint()) {
324 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
325 StrOS << printMBBReference(*MFI.getRestorePoint());
329 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
330 const MachineFunction &MF,
331 ModuleSlotTracker &MST) {
332 const MachineFrameInfo &MFI = MF.getFrameInfo();
333 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
334 // Process fixed stack objects.
336 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
337 if (MFI.isDeadObjectIndex(I))
340 yaml::FixedMachineStackObject YamlObject;
342 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
343 ? yaml::FixedMachineStackObject::SpillSlot
344 : yaml::FixedMachineStackObject::DefaultType;
345 YamlObject.Offset = MFI.getObjectOffset(I);
346 YamlObject.Size = MFI.getObjectSize(I);
347 YamlObject.Alignment = MFI.getObjectAlignment(I);
348 YamlObject.StackID = MFI.getStackID(I);
349 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
350 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
351 YMF.FixedStackObjects.push_back(YamlObject);
352 StackObjectOperandMapping.insert(
353 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
356 // Process ordinary stack objects.
358 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
359 if (MFI.isDeadObjectIndex(I))
362 yaml::MachineStackObject YamlObject;
364 if (const auto *Alloca = MFI.getObjectAllocation(I))
365 YamlObject.Name.Value =
366 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
367 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
368 ? yaml::MachineStackObject::SpillSlot
369 : MFI.isVariableSizedObjectIndex(I)
370 ? yaml::MachineStackObject::VariableSized
371 : yaml::MachineStackObject::DefaultType;
372 YamlObject.Offset = MFI.getObjectOffset(I);
373 YamlObject.Size = MFI.getObjectSize(I);
374 YamlObject.Alignment = MFI.getObjectAlignment(I);
375 YamlObject.StackID = MFI.getStackID(I);
377 YMF.StackObjects.push_back(YamlObject);
378 StackObjectOperandMapping.insert(std::make_pair(
379 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
382 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
383 yaml::StringValue Reg;
384 printRegMIR(CSInfo.getReg(), Reg, TRI);
385 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
386 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
387 "Invalid stack object index");
388 const FrameIndexOperand &StackObject = StackObjectInfo->second;
389 if (StackObject.IsFixed) {
390 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
391 YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
394 YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
395 YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
399 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
400 auto LocalObject = MFI.getLocalFrameObjectMap(I);
401 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
402 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
403 "Invalid stack object index");
404 const FrameIndexOperand &StackObject = StackObjectInfo->second;
405 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
406 YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
409 // Print the stack object references in the frame information class after
410 // converting the stack objects.
411 if (MFI.hasStackProtectorIndex()) {
412 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
413 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
414 .printStackObjectReference(MFI.getStackProtectorIndex());
417 // Print the debug variable information.
418 for (const MachineFunction::VariableDbgInfo &DebugVar :
419 MF.getVariableDbgInfo()) {
420 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
421 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
422 "Invalid stack object index");
423 const FrameIndexOperand &StackObject = StackObjectInfo->second;
424 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
425 auto &Object = YMF.StackObjects[StackObject.ID];
427 raw_string_ostream StrOS(Object.DebugVar.Value);
428 DebugVar.Var->printAsOperand(StrOS, MST);
431 raw_string_ostream StrOS(Object.DebugExpr.Value);
432 DebugVar.Expr->printAsOperand(StrOS, MST);
435 raw_string_ostream StrOS(Object.DebugLoc.Value);
436 DebugVar.Loc->printAsOperand(StrOS, MST);
441 void MIRPrinter::convert(yaml::MachineFunction &MF,
442 const MachineConstantPool &ConstantPool) {
444 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
446 raw_string_ostream StrOS(Str);
447 if (Constant.isMachineConstantPoolEntry()) {
448 Constant.Val.MachineCPVal->print(StrOS);
450 Constant.Val.ConstVal->printAsOperand(StrOS);
453 yaml::MachineConstantPoolValue YamlConstant;
454 YamlConstant.ID = ID++;
455 YamlConstant.Value = StrOS.str();
456 YamlConstant.Alignment = Constant.getAlignment();
457 YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
459 MF.Constants.push_back(YamlConstant);
463 void MIRPrinter::convert(ModuleSlotTracker &MST,
464 yaml::MachineJumpTable &YamlJTI,
465 const MachineJumpTableInfo &JTI) {
466 YamlJTI.Kind = JTI.getEntryKind();
468 for (const auto &Table : JTI.getJumpTables()) {
470 yaml::MachineJumpTable::Entry Entry;
472 for (const auto *MBB : Table.MBBs) {
473 raw_string_ostream StrOS(Str);
474 StrOS << printMBBReference(*MBB);
475 Entry.Blocks.push_back(StrOS.str());
478 YamlJTI.Entries.push_back(Entry);
482 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
483 const auto *TRI = MF.getSubtarget().getRegisterInfo();
485 for (const uint32_t *Mask : TRI->getRegMasks())
486 RegisterMaskIds.insert(std::make_pair(Mask, I++));
489 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
490 SmallVectorImpl<MachineBasicBlock*> &Result,
491 bool &IsFallthrough) {
492 SmallPtrSet<MachineBasicBlock*,8> Seen;
494 for (const MachineInstr &MI : MBB) {
497 for (const MachineOperand &MO : MI.operands()) {
500 MachineBasicBlock *Succ = MO.getMBB();
501 auto RP = Seen.insert(Succ);
503 Result.push_back(Succ);
506 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
507 IsFallthrough = I == MBB.end() || !I->isBarrier();
511 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
512 if (MBB.succ_size() <= 1)
514 if (!MBB.hasSuccessorProbabilities())
517 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
519 BranchProbability::normalizeProbabilities(Normalized.begin(),
521 SmallVector<BranchProbability,8> Equal(Normalized.size());
522 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
524 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
527 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
528 SmallVector<MachineBasicBlock*,8> GuessedSuccs;
529 bool GuessedFallthrough;
530 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
531 if (GuessedFallthrough) {
532 const MachineFunction &MF = *MBB.getParent();
533 MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
534 if (NextI != MF.end()) {
535 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
536 if (!is_contained(GuessedSuccs, Next))
537 GuessedSuccs.push_back(Next);
540 if (GuessedSuccs.size() != MBB.succ_size())
542 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
545 void MIPrinter::print(const MachineBasicBlock &MBB) {
546 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
547 OS << "bb." << MBB.getNumber();
548 bool HasAttributes = false;
549 if (const auto *BB = MBB.getBasicBlock()) {
551 OS << "." << BB->getName();
553 HasAttributes = true;
555 int Slot = MST.getLocalSlot(BB);
557 OS << "<ir-block badref>";
559 OS << (Twine("%ir-block.") + Twine(Slot)).str();
562 if (MBB.hasAddressTaken()) {
563 OS << (HasAttributes ? ", " : " (");
564 OS << "address-taken";
565 HasAttributes = true;
568 OS << (HasAttributes ? ", " : " (");
570 HasAttributes = true;
572 if (MBB.getAlignment()) {
573 OS << (HasAttributes ? ", " : " (");
574 OS << "align " << MBB.getAlignment();
575 HasAttributes = true;
581 bool HasLineAttributes = false;
582 // Print the successors
583 bool canPredictProbs = canPredictBranchProbabilities(MBB);
584 // Even if the list of successors is empty, if we cannot guess it,
585 // we need to print it to tell the parser that the list is empty.
586 // This is needed, because MI model unreachable as empty blocks
587 // with an empty successor list. If the parser would see that
588 // without the successor list, it would guess the code would
590 if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
591 !canPredictSuccessors(MBB)) {
592 OS.indent(2) << "successors: ";
593 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
594 if (I != MBB.succ_begin())
596 OS << printMBBReference(**I);
597 if (!SimplifyMIR || !canPredictProbs)
599 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
603 HasLineAttributes = true;
606 // Print the live in registers.
607 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
608 if (MRI.tracksLiveness() && !MBB.livein_empty()) {
609 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
610 OS.indent(2) << "liveins: ";
612 for (const auto &LI : MBB.liveins()) {
616 OS << printReg(LI.PhysReg, &TRI);
617 if (!LI.LaneMask.all())
618 OS << ":0x" << PrintLaneMask(LI.LaneMask);
621 HasLineAttributes = true;
624 if (HasLineAttributes)
626 bool IsInBundle = false;
627 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
628 const MachineInstr &MI = *I;
629 if (IsInBundle && !MI.isInsideBundle()) {
630 OS.indent(2) << "}\n";
633 OS.indent(IsInBundle ? 4 : 2);
635 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
642 OS.indent(2) << "}\n";
645 void MIPrinter::print(const MachineInstr &MI) {
646 const auto *MF = MI.getMF();
647 const auto &MRI = MF->getRegInfo();
648 const auto &SubTarget = MF->getSubtarget();
649 const auto *TRI = SubTarget.getRegisterInfo();
650 assert(TRI && "Expected target register info");
651 const auto *TII = SubTarget.getInstrInfo();
652 assert(TII && "Expected target instruction info");
653 if (MI.isCFIInstruction())
654 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
656 SmallBitVector PrintedTypes(8);
657 bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
658 unsigned I = 0, E = MI.getNumOperands();
659 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
660 !MI.getOperand(I).isImplicit();
664 print(MI, I, TRI, ShouldPrintRegisterTies,
665 MI.getTypeToPrint(I, PrintedTypes, MRI),
671 if (MI.getFlag(MachineInstr::FrameSetup))
672 OS << "frame-setup ";
673 OS << TII->getName(MI.getOpcode());
677 bool NeedComma = false;
681 print(MI, I, TRI, ShouldPrintRegisterTies,
682 MI.getTypeToPrint(I, PrintedTypes, MRI));
686 if (MI.getDebugLoc()) {
689 OS << " debug-location ";
690 MI.getDebugLoc()->printAsOperand(OS, MST);
693 if (!MI.memoperands_empty()) {
695 const LLVMContext &Context = MF->getFunction().getContext();
696 bool NeedComma = false;
697 for (const auto *Op : MI.memoperands()) {
700 print(Context, *TII, *Op);
706 void MIPrinter::printIRValueReference(const Value &V) {
707 if (isa<GlobalValue>(V)) {
708 V.printAsOperand(OS, /*PrintType=*/false, MST);
711 if (isa<Constant>(V)) {
712 // Machine memory operands can load/store to/from constant value pointers.
714 V.printAsOperand(OS, /*PrintType=*/true, MST);
720 printLLVMNameWithoutPrefix(OS, V.getName());
723 MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V));
726 void MIPrinter::printStackObjectReference(int FrameIndex) {
727 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
728 assert(ObjectInfo != StackObjectOperandMapping.end() &&
729 "Invalid frame index");
730 const FrameIndexOperand &Operand = ObjectInfo->second;
731 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
735 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
736 const TargetRegisterInfo *TRI,
737 bool ShouldPrintRegisterTies, LLT TypeToPrint,
739 const MachineOperand &Op = MI.getOperand(OpIdx);
740 switch (Op.getType()) {
741 case MachineOperand::MO_Immediate:
742 if (MI.isOperandSubregIdx(OpIdx)) {
743 MachineOperand::printTargetFlags(OS, Op);
744 MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
748 case MachineOperand::MO_Register:
749 case MachineOperand::MO_CImmediate:
750 case MachineOperand::MO_FPImmediate:
751 case MachineOperand::MO_MachineBasicBlock:
752 case MachineOperand::MO_ConstantPoolIndex:
753 case MachineOperand::MO_TargetIndex:
754 case MachineOperand::MO_JumpTableIndex:
755 case MachineOperand::MO_ExternalSymbol:
756 case MachineOperand::MO_GlobalAddress:
757 case MachineOperand::MO_RegisterLiveOut:
758 case MachineOperand::MO_Metadata:
759 case MachineOperand::MO_MCSymbol:
760 case MachineOperand::MO_CFIIndex:
761 case MachineOperand::MO_IntrinsicID:
762 case MachineOperand::MO_Predicate:
763 case MachineOperand::MO_BlockAddress: {
764 unsigned TiedOperandIdx = 0;
765 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
766 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
767 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
768 Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
769 TiedOperandIdx, TRI, TII);
772 case MachineOperand::MO_FrameIndex:
773 printStackObjectReference(Op.getIndex());
775 case MachineOperand::MO_RegisterMask: {
776 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
777 if (RegMaskInfo != RegisterMaskIds.end())
778 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
780 printCustomRegMask(Op.getRegMask(), OS, TRI);
786 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
788 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
789 for (const auto &I : Flags) {
790 if (I.first == TMMOFlag) {
797 void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII,
798 const MachineMemOperand &Op) {
802 if (Op.isNonTemporal())
803 OS << "non-temporal ";
804 if (Op.isDereferenceable())
805 OS << "dereferenceable ";
806 if (Op.isInvariant())
808 if (Op.getFlags() & MachineMemOperand::MOTargetFlag1)
809 OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag1)
811 if (Op.getFlags() & MachineMemOperand::MOTargetFlag2)
812 OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag2)
814 if (Op.getFlags() & MachineMemOperand::MOTargetFlag3)
815 OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3)
818 assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)");
824 printSyncScope(Context, Op.getSyncScopeID());
826 if (Op.getOrdering() != AtomicOrdering::NotAtomic)
827 OS << toIRString(Op.getOrdering()) << ' ';
828 if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
829 OS << toIRString(Op.getFailureOrdering()) << ' ';
832 if (const Value *Val = Op.getValue()) {
833 OS << ((Op.isLoad() && Op.isStore()) ? " on "
834 : Op.isLoad() ? " from " : " into ");
835 printIRValueReference(*Val);
836 } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
837 OS << ((Op.isLoad() && Op.isStore()) ? " on "
838 : Op.isLoad() ? " from " : " into ");
839 assert(PVal && "Expected a pseudo source value");
840 switch (PVal->kind()) {
841 case PseudoSourceValue::Stack:
844 case PseudoSourceValue::GOT:
847 case PseudoSourceValue::JumpTable:
850 case PseudoSourceValue::ConstantPool:
851 OS << "constant-pool";
853 case PseudoSourceValue::FixedStack:
854 printStackObjectReference(
855 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
857 case PseudoSourceValue::GlobalValueCallEntry:
859 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
860 OS, /*PrintType=*/false, MST);
862 case PseudoSourceValue::ExternalSymbolCallEntry:
863 OS << "call-entry $";
864 printLLVMNameWithoutPrefix(
865 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
867 case PseudoSourceValue::TargetCustom:
868 llvm_unreachable("TargetCustom pseudo source values are not supported");
872 MachineOperand::printOperandOffset(OS, Op.getOffset());
873 if (Op.getBaseAlignment() != Op.getSize())
874 OS << ", align " << Op.getBaseAlignment();
875 auto AAInfo = Op.getAAInfo();
878 AAInfo.TBAA->printAsOperand(OS, MST);
881 OS << ", !alias.scope ";
882 AAInfo.Scope->printAsOperand(OS, MST);
884 if (AAInfo.NoAlias) {
886 AAInfo.NoAlias->printAsOperand(OS, MST);
888 if (Op.getRanges()) {
890 Op.getRanges()->printAsOperand(OS, MST);
895 void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) {
897 case SyncScope::System: {
902 Context.getSyncScopeNames(SSNs);
904 OS << "syncscope(\"";
905 PrintEscapedString(SSNs[SSID], OS);
912 void llvm::printMIR(raw_ostream &OS, const Module &M) {
913 yaml::Output Out(OS);
914 Out << const_cast<Module &>(M);
917 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
918 MIRPrinter Printer(OS);