1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/IR/Metadata.h"
32 #include "llvm/IR/Module.h"
33 #include "llvm/IR/ModuleSlotTracker.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/IR/Value.h"
36 #include "llvm/MC/MCInstrDesc.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetIntrinsicInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include "llvm/Target/TargetSubtargetInfo.h"
50 static cl::opt<bool> PrintWholeRegMask(
51 "print-whole-regmask",
52 cl::desc("Print the full contents of regmask operands in IR dumps"),
53 cl::init(true), cl::Hidden);
55 //===----------------------------------------------------------------------===//
56 // MachineOperand Implementation
57 //===----------------------------------------------------------------------===//
59 void MachineOperand::setReg(unsigned Reg) {
60 if (getReg() == Reg) return; // No change.
62 // Otherwise, we have to change the register. If this operand is embedded
63 // into a machine function, we need to update the old and new register's
65 if (MachineInstr *MI = getParent())
66 if (MachineBasicBlock *MBB = MI->getParent())
67 if (MachineFunction *MF = MBB->getParent()) {
68 MachineRegisterInfo &MRI = MF->getRegInfo();
69 MRI.removeRegOperandFromUseList(this);
70 SmallContents.RegNo = Reg;
71 MRI.addRegOperandToUseList(this);
75 // Otherwise, just change the register, no problem. :)
76 SmallContents.RegNo = Reg;
79 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
80 const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isVirtualRegister(Reg));
82 if (SubIdx && getSubReg())
83 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
89 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
90 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
92 Reg = TRI.getSubReg(Reg, getSubReg());
93 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
94 // That won't happen in legal code.
102 /// Change a def to a use, or a use to a def.
103 void MachineOperand::setIsDef(bool Val) {
104 assert(isReg() && "Wrong MachineOperand accessor");
105 assert((!Val || !isDebug()) && "Marking a debug operation as def");
108 // MRI may keep uses and defs in different list positions.
109 if (MachineInstr *MI = getParent())
110 if (MachineBasicBlock *MBB = MI->getParent())
111 if (MachineFunction *MF = MBB->getParent()) {
112 MachineRegisterInfo &MRI = MF->getRegInfo();
113 MRI.removeRegOperandFromUseList(this);
115 MRI.addRegOperandToUseList(this);
121 // If this operand is currently a register operand, and if this is in a
122 // function, deregister the operand from the register's use/def list.
123 void MachineOperand::removeRegFromUses() {
124 if (!isReg() || !isOnRegUseList())
127 if (MachineInstr *MI = getParent()) {
128 if (MachineBasicBlock *MBB = MI->getParent()) {
129 if (MachineFunction *MF = MBB->getParent())
130 MF->getRegInfo().removeRegOperandFromUseList(this);
135 /// ChangeToImmediate - Replace this operand with a new immediate operand of
136 /// the specified value. If an operand is known to be an immediate already,
137 /// the setImm method should be used.
138 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
139 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
143 OpKind = MO_Immediate;
144 Contents.ImmVal = ImmVal;
147 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
148 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
152 OpKind = MO_FPImmediate;
153 Contents.CFP = FPImm;
156 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
157 assert((!isReg() || !isTied()) &&
158 "Cannot change a tied operand into an external symbol");
162 OpKind = MO_ExternalSymbol;
163 Contents.OffsetedInfo.Val.SymbolName = SymName;
164 setOffset(0); // Offset is always 0.
165 setTargetFlags(TargetFlags);
168 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
169 assert((!isReg() || !isTied()) &&
170 "Cannot change a tied operand into an MCSymbol");
174 OpKind = MO_MCSymbol;
178 void MachineOperand::ChangeToFrameIndex(int Idx) {
179 assert((!isReg() || !isTied()) &&
180 "Cannot change a tied operand into a FrameIndex");
184 OpKind = MO_FrameIndex;
188 /// ChangeToRegister - Replace this operand with a new register operand of
189 /// the specified value. If an operand is known to be an register already,
190 /// the setReg method should be used.
191 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
192 bool isKill, bool isDead, bool isUndef,
194 MachineRegisterInfo *RegInfo = nullptr;
195 if (MachineInstr *MI = getParent())
196 if (MachineBasicBlock *MBB = MI->getParent())
197 if (MachineFunction *MF = MBB->getParent())
198 RegInfo = &MF->getRegInfo();
199 // If this operand is already a register operand, remove it from the
200 // register's use/def lists.
201 bool WasReg = isReg();
202 if (RegInfo && WasReg)
203 RegInfo->removeRegOperandFromUseList(this);
205 // Change this to a register and set the reg#.
206 OpKind = MO_Register;
207 SmallContents.RegNo = Reg;
208 SubReg_TargetFlags = 0;
214 IsInternalRead = false;
215 IsEarlyClobber = false;
217 // Ensure isOnRegUseList() returns false.
218 Contents.Reg.Prev = nullptr;
219 // Preserve the tie when the operand was already a register.
223 // If this operand is embedded in a function, add the operand to the
224 // register's use/def list.
226 RegInfo->addRegOperandToUseList(this);
229 /// isIdenticalTo - Return true if this operand is identical to the specified
230 /// operand. Note that this should stay in sync with the hash_value overload
232 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
233 if (getType() != Other.getType() ||
234 getTargetFlags() != Other.getTargetFlags())
238 case MachineOperand::MO_Register:
239 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
240 getSubReg() == Other.getSubReg();
241 case MachineOperand::MO_Immediate:
242 return getImm() == Other.getImm();
243 case MachineOperand::MO_CImmediate:
244 return getCImm() == Other.getCImm();
245 case MachineOperand::MO_FPImmediate:
246 return getFPImm() == Other.getFPImm();
247 case MachineOperand::MO_MachineBasicBlock:
248 return getMBB() == Other.getMBB();
249 case MachineOperand::MO_FrameIndex:
250 return getIndex() == Other.getIndex();
251 case MachineOperand::MO_ConstantPoolIndex:
252 case MachineOperand::MO_TargetIndex:
253 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
254 case MachineOperand::MO_JumpTableIndex:
255 return getIndex() == Other.getIndex();
256 case MachineOperand::MO_GlobalAddress:
257 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
258 case MachineOperand::MO_ExternalSymbol:
259 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
260 getOffset() == Other.getOffset();
261 case MachineOperand::MO_BlockAddress:
262 return getBlockAddress() == Other.getBlockAddress() &&
263 getOffset() == Other.getOffset();
264 case MachineOperand::MO_RegisterMask:
265 case MachineOperand::MO_RegisterLiveOut:
266 return getRegMask() == Other.getRegMask();
267 case MachineOperand::MO_MCSymbol:
268 return getMCSymbol() == Other.getMCSymbol();
269 case MachineOperand::MO_CFIIndex:
270 return getCFIIndex() == Other.getCFIIndex();
271 case MachineOperand::MO_Metadata:
272 return getMetadata() == Other.getMetadata();
273 case MachineOperand::MO_IntrinsicID:
274 return getIntrinsicID() == Other.getIntrinsicID();
275 case MachineOperand::MO_Predicate:
276 return getPredicate() == Other.getPredicate();
278 llvm_unreachable("Invalid machine operand type");
281 // Note: this must stay exactly in sync with isIdenticalTo above.
282 hash_code llvm::hash_value(const MachineOperand &MO) {
283 switch (MO.getType()) {
284 case MachineOperand::MO_Register:
285 // Register operands don't have target flags.
286 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
287 case MachineOperand::MO_Immediate:
288 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
289 case MachineOperand::MO_CImmediate:
290 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
291 case MachineOperand::MO_FPImmediate:
292 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
293 case MachineOperand::MO_MachineBasicBlock:
294 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
295 case MachineOperand::MO_FrameIndex:
296 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
297 case MachineOperand::MO_ConstantPoolIndex:
298 case MachineOperand::MO_TargetIndex:
299 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
301 case MachineOperand::MO_JumpTableIndex:
302 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
303 case MachineOperand::MO_ExternalSymbol:
304 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
306 case MachineOperand::MO_GlobalAddress:
307 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
309 case MachineOperand::MO_BlockAddress:
310 return hash_combine(MO.getType(), MO.getTargetFlags(),
311 MO.getBlockAddress(), MO.getOffset());
312 case MachineOperand::MO_RegisterMask:
313 case MachineOperand::MO_RegisterLiveOut:
314 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
315 case MachineOperand::MO_Metadata:
316 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
317 case MachineOperand::MO_MCSymbol:
318 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
319 case MachineOperand::MO_CFIIndex:
320 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
321 case MachineOperand::MO_IntrinsicID:
322 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
323 case MachineOperand::MO_Predicate:
324 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
326 llvm_unreachable("Invalid machine operand type");
329 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
330 const TargetIntrinsicInfo *IntrinsicInfo) const {
331 ModuleSlotTracker DummyMST(nullptr);
332 print(OS, DummyMST, TRI, IntrinsicInfo);
335 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
336 const TargetRegisterInfo *TRI,
337 const TargetIntrinsicInfo *IntrinsicInfo) const {
339 case MachineOperand::MO_Register:
340 OS << PrintReg(getReg(), TRI, getSubReg());
342 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
343 isInternalRead() || isEarlyClobber() || isTied()) {
345 bool NeedComma = false;
347 if (NeedComma) OS << ',';
348 if (isEarlyClobber())
349 OS << "earlyclobber,";
354 // <def,read-undef> only makes sense when getSubReg() is set.
355 // Don't clutter the output otherwise.
356 if (isUndef() && getSubReg())
358 } else if (isImplicit()) {
364 if (NeedComma) OS << ',';
369 if (NeedComma) OS << ',';
373 if (isUndef() && isUse()) {
374 if (NeedComma) OS << ',';
378 if (isInternalRead()) {
379 if (NeedComma) OS << ',';
384 if (NeedComma) OS << ',';
387 OS << unsigned(TiedTo - 1);
392 case MachineOperand::MO_Immediate:
395 case MachineOperand::MO_CImmediate:
396 getCImm()->getValue().print(OS, false);
398 case MachineOperand::MO_FPImmediate:
399 if (getFPImm()->getType()->isFloatTy()) {
400 OS << getFPImm()->getValueAPF().convertToFloat();
401 } else if (getFPImm()->getType()->isHalfTy()) {
402 APFloat APF = getFPImm()->getValueAPF();
404 APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
405 OS << "half " << APF.convertToFloat();
407 OS << getFPImm()->getValueAPF().convertToDouble();
410 case MachineOperand::MO_MachineBasicBlock:
411 OS << "<BB#" << getMBB()->getNumber() << ">";
413 case MachineOperand::MO_FrameIndex:
414 OS << "<fi#" << getIndex() << '>';
416 case MachineOperand::MO_ConstantPoolIndex:
417 OS << "<cp#" << getIndex();
418 if (getOffset()) OS << "+" << getOffset();
421 case MachineOperand::MO_TargetIndex:
422 OS << "<ti#" << getIndex();
423 if (getOffset()) OS << "+" << getOffset();
426 case MachineOperand::MO_JumpTableIndex:
427 OS << "<jt#" << getIndex() << '>';
429 case MachineOperand::MO_GlobalAddress:
431 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
432 if (getOffset()) OS << "+" << getOffset();
435 case MachineOperand::MO_ExternalSymbol:
436 OS << "<es:" << getSymbolName();
437 if (getOffset()) OS << "+" << getOffset();
440 case MachineOperand::MO_BlockAddress:
442 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
443 if (getOffset()) OS << "+" << getOffset();
446 case MachineOperand::MO_RegisterMask: {
447 unsigned NumRegsInMask = 0;
448 unsigned NumRegsEmitted = 0;
450 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
451 unsigned MaskWord = i / 32;
452 unsigned MaskBit = i % 32;
453 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
454 if (PrintWholeRegMask || NumRegsEmitted <= 10) {
455 OS << " " << PrintReg(i, TRI);
461 if (NumRegsEmitted != NumRegsInMask)
462 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
466 case MachineOperand::MO_RegisterLiveOut:
467 OS << "<regliveout>";
469 case MachineOperand::MO_Metadata:
471 getMetadata()->printAsOperand(OS, MST);
474 case MachineOperand::MO_MCSymbol:
475 OS << "<MCSym=" << *getMCSymbol() << '>';
477 case MachineOperand::MO_CFIIndex:
478 OS << "<call frame instruction>";
480 case MachineOperand::MO_IntrinsicID: {
481 Intrinsic::ID ID = getIntrinsicID();
482 if (ID < Intrinsic::num_intrinsics)
483 OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
484 else if (IntrinsicInfo)
485 OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
487 OS << "<intrinsic:" << ID << '>';
490 case MachineOperand::MO_Predicate: {
491 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
492 OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
493 << CmpInst::getPredicateName(Pred) << '>';
496 if (unsigned TF = getTargetFlags())
497 OS << "[TF=" << TF << ']';
500 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
501 LLVM_DUMP_METHOD void MachineOperand::dump() const {
502 dbgs() << *this << '\n';
506 //===----------------------------------------------------------------------===//
507 // MachineMemOperand Implementation
508 //===----------------------------------------------------------------------===//
510 /// getAddrSpace - Return the LLVM IR address space number that this pointer
512 unsigned MachinePointerInfo::getAddrSpace() const {
513 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
514 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
517 /// getConstantPool - Return a MachinePointerInfo record that refers to the
519 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
520 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
523 /// getFixedStack - Return a MachinePointerInfo record that refers to the
524 /// the specified FrameIndex.
525 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
526 int FI, int64_t Offset) {
527 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
530 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
531 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
534 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
535 return MachinePointerInfo(MF.getPSVManager().getGOT());
538 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
540 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
543 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
544 uint64_t s, unsigned int a,
545 const AAMDNodes &AAInfo,
546 const MDNode *Ranges,
547 SynchronizationScope SynchScope,
548 AtomicOrdering Ordering,
549 AtomicOrdering FailureOrdering)
550 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
551 AAInfo(AAInfo), Ranges(Ranges) {
552 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
553 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
554 "invalid pointer value");
555 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
556 assert((isLoad() || isStore()) && "Not a load/store!");
558 AtomicInfo.SynchScope = static_cast<unsigned>(SynchScope);
559 assert(getSynchScope() == SynchScope && "Value truncated");
560 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
561 assert(getOrdering() == Ordering && "Value truncated");
562 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
563 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
566 /// Profile - Gather unique data for the object.
568 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
569 ID.AddInteger(getOffset());
571 ID.AddPointer(getOpaqueValue());
572 ID.AddInteger(getFlags());
573 ID.AddInteger(getBaseAlignment());
576 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
577 // The Value and Offset may differ due to CSE. But the flags and size
578 // should be the same.
579 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
580 assert(MMO->getSize() == getSize() && "Size mismatch!");
582 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
583 // Update the alignment value.
584 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
585 // Also update the base and offset, because the new alignment may
586 // not be applicable with the old ones.
587 PtrInfo = MMO->PtrInfo;
591 /// getAlignment - Return the minimum known alignment in bytes of the
592 /// actual memory reference.
593 uint64_t MachineMemOperand::getAlignment() const {
594 return MinAlign(getBaseAlignment(), getOffset());
597 void MachineMemOperand::print(raw_ostream &OS) const {
598 ModuleSlotTracker DummyMST(nullptr);
601 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
602 assert((isLoad() || isStore()) &&
603 "SV has to be a load, store or both.");
614 // Print the address information.
616 if (const Value *V = getValue())
617 V->printAsOperand(OS, /*PrintType=*/false, MST);
618 else if (const PseudoSourceValue *PSV = getPseudoValue())
619 PSV->printCustom(OS);
623 unsigned AS = getAddrSpace();
625 OS << "(addrspace=" << AS << ')';
627 // If the alignment of the memory reference itself differs from the alignment
628 // of the base pointer, print the base alignment explicitly, next to the base
630 if (getBaseAlignment() != getAlignment())
631 OS << "(align=" << getBaseAlignment() << ")";
633 if (getOffset() != 0)
634 OS << "+" << getOffset();
637 // Print the alignment of the reference.
638 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
639 OS << "(align=" << getAlignment() << ")";
642 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
644 if (TBAAInfo->getNumOperands() > 0)
645 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
651 // Print AA scope info.
652 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
653 OS << "(alias.scope=";
654 if (ScopeInfo->getNumOperands() > 0)
655 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
656 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
665 // Print AA noalias scope info.
666 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
668 if (NoAliasInfo->getNumOperands() > 0)
669 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
670 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
680 OS << "(nontemporal)";
681 if (isDereferenceable())
682 OS << "(dereferenceable)";
687 //===----------------------------------------------------------------------===//
688 // MachineInstr Implementation
689 //===----------------------------------------------------------------------===//
691 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
692 if (MCID->ImplicitDefs)
693 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
695 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
696 if (MCID->ImplicitUses)
697 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
699 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
702 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
703 /// implicit operands. It reserves space for the number of operands specified by
705 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
706 DebugLoc dl, bool NoImp)
707 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
708 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
709 debugLoc(std::move(dl)) {
710 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
712 // Reserve space for the expected number of operands.
713 if (unsigned NumOps = MCID->getNumOperands() +
714 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
715 CapOperands = OperandCapacity::get(NumOps);
716 Operands = MF.allocateOperandArray(CapOperands);
720 addImplicitDefUseOperands(MF);
723 /// MachineInstr ctor - Copies MachineInstr arg exactly
725 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
726 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
727 Flags(0), AsmPrinterFlags(0), NumMemRefs(MI.NumMemRefs),
728 MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc()) {
729 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
731 CapOperands = OperandCapacity::get(MI.getNumOperands());
732 Operands = MF.allocateOperandArray(CapOperands);
735 for (const MachineOperand &MO : MI.operands())
738 // Copy all the sensible flags.
742 /// getRegInfo - If this instruction is embedded into a MachineFunction,
743 /// return the MachineRegisterInfo object for the current function, otherwise
745 MachineRegisterInfo *MachineInstr::getRegInfo() {
746 if (MachineBasicBlock *MBB = getParent())
747 return &MBB->getParent()->getRegInfo();
751 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
752 /// this instruction from their respective use lists. This requires that the
753 /// operands already be on their use lists.
754 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
755 for (MachineOperand &MO : operands())
757 MRI.removeRegOperandFromUseList(&MO);
760 /// AddRegOperandsToUseLists - Add all of the register operands in
761 /// this instruction from their respective use lists. This requires that the
762 /// operands not be on their use lists yet.
763 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
764 for (MachineOperand &MO : operands())
766 MRI.addRegOperandToUseList(&MO);
769 void MachineInstr::addOperand(const MachineOperand &Op) {
770 MachineBasicBlock *MBB = getParent();
771 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
772 MachineFunction *MF = MBB->getParent();
773 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
777 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
778 /// ranges. If MRI is non-null also update use-def chains.
779 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
780 unsigned NumOps, MachineRegisterInfo *MRI) {
782 return MRI->moveOperands(Dst, Src, NumOps);
784 // MachineOperand is a trivially copyable type so we can just use memmove.
785 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
788 /// addOperand - Add the specified operand to the instruction. If it is an
789 /// implicit operand, it is added to the end of the operand list. If it is
790 /// an explicit operand it is added at the end of the explicit operand list
791 /// (before the first implicit operand).
792 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
793 assert(MCID && "Cannot add operands before providing an instr descriptor");
795 // Check if we're adding one of our existing operands.
796 if (&Op >= Operands && &Op < Operands + NumOperands) {
797 // This is unusual: MI->addOperand(MI->getOperand(i)).
798 // If adding Op requires reallocating or moving existing operands around,
799 // the Op reference could go stale. Support it by copying Op.
800 MachineOperand CopyOp(Op);
801 return addOperand(MF, CopyOp);
804 // Find the insert location for the new operand. Implicit registers go at
805 // the end, everything else goes before the implicit regs.
807 // FIXME: Allow mixed explicit and implicit operands on inline asm.
808 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
809 // implicit-defs, but they must not be moved around. See the FIXME in
811 unsigned OpNo = getNumOperands();
812 bool isImpReg = Op.isReg() && Op.isImplicit();
813 if (!isImpReg && !isInlineAsm()) {
814 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
816 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
821 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
822 // OpNo now points as the desired insertion point. Unless this is a variadic
823 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
824 // RegMask operands go between the explicit and implicit operands.
825 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
826 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
827 "Trying to add an operand to a machine instr that is already done!");
830 MachineRegisterInfo *MRI = getRegInfo();
832 // Determine if the Operands array needs to be reallocated.
833 // Save the old capacity and operand array.
834 OperandCapacity OldCap = CapOperands;
835 MachineOperand *OldOperands = Operands;
836 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
837 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
838 Operands = MF.allocateOperandArray(CapOperands);
839 // Move the operands before the insertion point.
841 moveOperands(Operands, OldOperands, OpNo, MRI);
844 // Move the operands following the insertion point.
845 if (OpNo != NumOperands)
846 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
850 // Deallocate the old operand array.
851 if (OldOperands != Operands && OldOperands)
852 MF.deallocateOperandArray(OldCap, OldOperands);
854 // Copy Op into place. It still needs to be inserted into the MRI use lists.
855 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
856 NewMO->ParentMI = this;
858 // When adding a register operand, tell MRI about it.
859 if (NewMO->isReg()) {
860 // Ensure isOnRegUseList() returns false, regardless of Op's status.
861 NewMO->Contents.Reg.Prev = nullptr;
862 // Ignore existing ties. This is not a property that can be copied.
864 // Add the new operand to MRI, but only for instructions in an MBB.
866 MRI->addRegOperandToUseList(NewMO);
867 // The MCID operand information isn't accurate until we start adding
868 // explicit operands. The implicit operands are added first, then the
869 // explicits are inserted before them.
871 // Tie uses to defs as indicated in MCInstrDesc.
872 if (NewMO->isUse()) {
873 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
875 tieOperands(DefIdx, OpNo);
877 // If the register operand is flagged as early, mark the operand as such.
878 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
879 NewMO->setIsEarlyClobber(true);
884 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
885 /// fewer operand than it started with.
887 void MachineInstr::RemoveOperand(unsigned OpNo) {
888 assert(OpNo < getNumOperands() && "Invalid operand number");
889 untieRegOperand(OpNo);
892 // Moving tied operands would break the ties.
893 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
894 if (Operands[i].isReg())
895 assert(!Operands[i].isTied() && "Cannot move tied operands");
898 MachineRegisterInfo *MRI = getRegInfo();
899 if (MRI && Operands[OpNo].isReg())
900 MRI->removeRegOperandFromUseList(Operands + OpNo);
902 // Don't call the MachineOperand destructor. A lot of this code depends on
903 // MachineOperand having a trivial destructor anyway, and adding a call here
904 // wouldn't make it 'destructor-correct'.
906 if (unsigned N = NumOperands - 1 - OpNo)
907 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
911 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
912 /// This function should be used only occasionally. The setMemRefs function
913 /// is the primary method for setting up a MachineInstr's MemRefs list.
914 void MachineInstr::addMemOperand(MachineFunction &MF,
915 MachineMemOperand *MO) {
916 mmo_iterator OldMemRefs = MemRefs;
917 unsigned OldNumMemRefs = NumMemRefs;
919 unsigned NewNum = NumMemRefs + 1;
920 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
922 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
923 NewMemRefs[NewNum - 1] = MO;
924 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
927 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
929 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
930 auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
931 auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
932 if ((E1 - I1) != (E2 - I2))
934 for (; I1 != E1; ++I1, ++I2) {
941 std::pair<MachineInstr::mmo_iterator, unsigned>
942 MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
944 // If either of the incoming memrefs are empty, we must be conservative and
945 // treat this as if we've exhausted our space for memrefs and dropped them.
946 if (memoperands_empty() || Other.memoperands_empty())
947 return std::make_pair(nullptr, 0);
949 // If both instructions have identical memrefs, we don't need to merge them.
950 // Since many instructions have a single memref, and we tend to merge things
951 // like pairs of loads from the same location, this catches a large number of
952 // cases in practice.
953 if (hasIdenticalMMOs(*this, Other))
954 return std::make_pair(MemRefs, NumMemRefs);
956 // TODO: consider uniquing elements within the operand lists to reduce
957 // space usage and fall back to conservative information less often.
958 size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
960 // If we don't have enough room to store this many memrefs, be conservative
961 // and drop them. Otherwise, we'd fail asserts when trying to add them to
962 // the new instruction.
963 if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
964 return std::make_pair(nullptr, 0);
966 MachineFunction *MF = getParent()->getParent();
967 mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
968 mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
970 MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
972 assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
975 return std::make_pair(MemBegin, CombinedNumMemRefs);
978 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
979 assert(!isBundledWithPred() && "Must be called on bundle header");
980 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
981 if (MII->getDesc().getFlags() & Mask) {
982 if (Type == AnyInBundle)
985 if (Type == AllInBundle && !MII->isBundle())
988 // This was the last instruction in the bundle.
989 if (!MII->isBundledWithSucc())
990 return Type == AllInBundle;
994 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
995 MICheckType Check) const {
996 // If opcodes or number of operands are not the same then the two
997 // instructions are obviously not identical.
998 if (Other.getOpcode() != getOpcode() ||
999 Other.getNumOperands() != getNumOperands())
1003 // We have passed the test above that both instructions have the same
1004 // opcode, so we know that both instructions are bundles here. Let's compare
1005 // MIs inside the bundle.
1006 assert(Other.isBundle() && "Expected that both instructions are bundles.");
1007 MachineBasicBlock::const_instr_iterator I1 = getIterator();
1008 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
1009 // Loop until we analysed the last intruction inside at least one of the
1011 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
1014 if (!I1->isIdenticalTo(*I2, Check))
1017 // If we've reached the end of just one of the two bundles, but not both,
1018 // the instructions are not identical.
1019 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
1023 // Check operands to make sure they match.
1024 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1025 const MachineOperand &MO = getOperand(i);
1026 const MachineOperand &OMO = Other.getOperand(i);
1028 if (!MO.isIdenticalTo(OMO))
1033 // Clients may or may not want to ignore defs when testing for equality.
1034 // For example, machine CSE pass only cares about finding common
1035 // subexpressions, so it's safe to ignore virtual register defs.
1037 if (Check == IgnoreDefs)
1039 else if (Check == IgnoreVRegDefs) {
1040 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1041 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
1042 if (MO.getReg() != OMO.getReg())
1045 if (!MO.isIdenticalTo(OMO))
1047 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
1051 if (!MO.isIdenticalTo(OMO))
1053 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
1057 // If DebugLoc does not match then two dbg.values are not identical.
1059 if (getDebugLoc() && Other.getDebugLoc() &&
1060 getDebugLoc() != Other.getDebugLoc())
1065 MachineInstr *MachineInstr::removeFromParent() {
1066 assert(getParent() && "Not embedded in a basic block!");
1067 return getParent()->remove(this);
1070 MachineInstr *MachineInstr::removeFromBundle() {
1071 assert(getParent() && "Not embedded in a basic block!");
1072 return getParent()->remove_instr(this);
1075 void MachineInstr::eraseFromParent() {
1076 assert(getParent() && "Not embedded in a basic block!");
1077 getParent()->erase(this);
1080 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
1081 assert(getParent() && "Not embedded in a basic block!");
1082 MachineBasicBlock *MBB = getParent();
1083 MachineFunction *MF = MBB->getParent();
1084 assert(MF && "Not embedded in a function!");
1086 MachineInstr *MI = (MachineInstr *)this;
1087 MachineRegisterInfo &MRI = MF->getRegInfo();
1089 for (const MachineOperand &MO : MI->operands()) {
1090 if (!MO.isReg() || !MO.isDef())
1092 unsigned Reg = MO.getReg();
1093 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1095 MRI.markUsesInDebugValueAsUndef(Reg);
1097 MI->eraseFromParent();
1100 void MachineInstr::eraseFromBundle() {
1101 assert(getParent() && "Not embedded in a basic block!");
1102 getParent()->erase_instr(this);
1105 /// getNumExplicitOperands - Returns the number of non-implicit operands.
1107 unsigned MachineInstr::getNumExplicitOperands() const {
1108 unsigned NumOperands = MCID->getNumOperands();
1109 if (!MCID->isVariadic())
1112 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
1113 const MachineOperand &MO = getOperand(i);
1114 if (!MO.isReg() || !MO.isImplicit())
1120 void MachineInstr::bundleWithPred() {
1121 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
1122 setFlag(BundledPred);
1123 MachineBasicBlock::instr_iterator Pred = getIterator();
1125 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1126 Pred->setFlag(BundledSucc);
1129 void MachineInstr::bundleWithSucc() {
1130 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
1131 setFlag(BundledSucc);
1132 MachineBasicBlock::instr_iterator Succ = getIterator();
1134 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
1135 Succ->setFlag(BundledPred);
1138 void MachineInstr::unbundleFromPred() {
1139 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
1140 clearFlag(BundledPred);
1141 MachineBasicBlock::instr_iterator Pred = getIterator();
1143 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1144 Pred->clearFlag(BundledSucc);
1147 void MachineInstr::unbundleFromSucc() {
1148 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1149 clearFlag(BundledSucc);
1150 MachineBasicBlock::instr_iterator Succ = getIterator();
1152 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1153 Succ->clearFlag(BundledPred);
1156 bool MachineInstr::isStackAligningInlineAsm() const {
1157 if (isInlineAsm()) {
1158 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1159 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1165 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
1166 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1167 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1168 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1171 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
1172 unsigned *GroupNo) const {
1173 assert(isInlineAsm() && "Expected an inline asm instruction");
1174 assert(OpIdx < getNumOperands() && "OpIdx out of range");
1176 // Ignore queries about the initial operands.
1177 if (OpIdx < InlineAsm::MIOp_FirstOperand)
1182 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1184 const MachineOperand &FlagMO = getOperand(i);
1185 // If we reach the implicit register operands, stop looking.
1186 if (!FlagMO.isImm())
1188 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1189 if (i + NumOps > OpIdx) {
1199 const DILocalVariable *MachineInstr::getDebugVariable() const {
1200 assert(isDebugValue() && "not a DBG_VALUE");
1201 return cast<DILocalVariable>(getOperand(2).getMetadata());
1204 const DIExpression *MachineInstr::getDebugExpression() const {
1205 assert(isDebugValue() && "not a DBG_VALUE");
1206 return cast<DIExpression>(getOperand(3).getMetadata());
1209 const TargetRegisterClass*
1210 MachineInstr::getRegClassConstraint(unsigned OpIdx,
1211 const TargetInstrInfo *TII,
1212 const TargetRegisterInfo *TRI) const {
1213 assert(getParent() && "Can't have an MBB reference here!");
1214 assert(getParent()->getParent() && "Can't have an MF reference here!");
1215 const MachineFunction &MF = *getParent()->getParent();
1217 // Most opcodes have fixed constraints in their MCInstrDesc.
1219 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1221 if (!getOperand(OpIdx).isReg())
1224 // For tied uses on inline asm, get the constraint from the def.
1226 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1229 // Inline asm stores register class constraints in the flag word.
1230 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1234 unsigned Flag = getOperand(FlagIdx).getImm();
1236 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
1237 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
1238 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
1239 InlineAsm::hasRegClassConstraint(Flag, RCID))
1240 return TRI->getRegClass(RCID);
1242 // Assume that all registers in a memory operand are pointers.
1243 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1244 return TRI->getPointerRegClass(MF);
1249 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1250 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1251 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1252 // Check every operands inside the bundle if we have
1255 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
1257 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1258 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1260 // Otherwise, just check the current operands.
1261 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1262 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1266 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1267 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1268 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1269 assert(CurRC && "Invalid initial register class");
1270 // Check if Reg is constrained by some of its use/def from MI.
1271 const MachineOperand &MO = getOperand(OpIdx);
1272 if (!MO.isReg() || MO.getReg() != Reg)
1274 // If yes, accumulate the constraints through the operand.
1275 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1278 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1279 unsigned OpIdx, const TargetRegisterClass *CurRC,
1280 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1281 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1282 const MachineOperand &MO = getOperand(OpIdx);
1283 assert(MO.isReg() &&
1284 "Cannot get register constraints for non-register operand");
1285 assert(CurRC && "Invalid initial register class");
1286 if (unsigned SubIdx = MO.getSubReg()) {
1288 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1290 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1292 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1296 /// Return the number of instructions inside the MI bundle, not counting the
1297 /// header instruction.
1298 unsigned MachineInstr::getBundleSize() const {
1299 MachineBasicBlock::const_instr_iterator I = getIterator();
1301 while (I->isBundledWithSucc()) {
1308 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1309 /// the given register (not considering sub/super-registers).
1310 bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
1311 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1312 const MachineOperand &MO = getOperand(i);
1313 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1319 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1320 /// the specific register or -1 if it is not found. It further tightens
1321 /// the search criteria to a use that kills the register if isKill is true.
1322 int MachineInstr::findRegisterUseOperandIdx(
1323 unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1324 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1325 const MachineOperand &MO = getOperand(i);
1326 if (!MO.isReg() || !MO.isUse())
1328 unsigned MOReg = MO.getReg();
1331 if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1332 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1333 TRI->isSubRegister(MOReg, Reg)))
1334 if (!isKill || MO.isKill())
1340 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1341 /// indicating if this instruction reads or writes Reg. This also considers
1342 /// partial defines.
1343 std::pair<bool,bool>
1344 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1345 SmallVectorImpl<unsigned> *Ops) const {
1346 bool PartDef = false; // Partial redefine.
1347 bool FullDef = false; // Full define.
1350 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1351 const MachineOperand &MO = getOperand(i);
1352 if (!MO.isReg() || MO.getReg() != Reg)
1357 Use |= !MO.isUndef();
1358 else if (MO.getSubReg() && !MO.isUndef())
1359 // A partial <def,undef> doesn't count as reading the register.
1364 // A partial redefine uses Reg unless there is also a full define.
1365 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1368 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1369 /// the specified register or -1 if it is not found. If isDead is true, defs
1370 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1371 /// also checks if there is a def of a super-register.
1373 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1374 const TargetRegisterInfo *TRI) const {
1375 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1376 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1377 const MachineOperand &MO = getOperand(i);
1378 // Accept regmask operands when Overlap is set.
1379 // Ignore them when looking for a specific def operand (Overlap == false).
1380 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1382 if (!MO.isReg() || !MO.isDef())
1384 unsigned MOReg = MO.getReg();
1385 bool Found = (MOReg == Reg);
1386 if (!Found && TRI && isPhys &&
1387 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1389 Found = TRI->regsOverlap(MOReg, Reg);
1391 Found = TRI->isSubRegister(MOReg, Reg);
1393 if (Found && (!isDead || MO.isDead()))
1399 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1400 /// operand list that is used to represent the predicate. It returns -1 if
1402 int MachineInstr::findFirstPredOperandIdx() const {
1403 // Don't call MCID.findFirstPredOperandIdx() because this variant
1404 // is sometimes called on an instruction that's not yet complete, and
1405 // so the number of operands is less than the MCID indicates. In
1406 // particular, the PTX target does this.
1407 const MCInstrDesc &MCID = getDesc();
1408 if (MCID.isPredicable()) {
1409 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1410 if (MCID.OpInfo[i].isPredicate())
1417 // MachineOperand::TiedTo is 4 bits wide.
1418 const unsigned TiedMax = 15;
1420 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1422 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1423 /// field. TiedTo can have these values:
1425 /// 0: Operand is not tied to anything.
1426 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1427 /// TiedMax: Tied to an operand >= TiedMax-1.
1429 /// The tied def must be one of the first TiedMax operands on a normal
1430 /// instruction. INLINEASM instructions allow more tied defs.
1432 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1433 MachineOperand &DefMO = getOperand(DefIdx);
1434 MachineOperand &UseMO = getOperand(UseIdx);
1435 assert(DefMO.isDef() && "DefIdx must be a def operand");
1436 assert(UseMO.isUse() && "UseIdx must be a use operand");
1437 assert(!DefMO.isTied() && "Def is already tied to another use");
1438 assert(!UseMO.isTied() && "Use is already tied to another def");
1440 if (DefIdx < TiedMax)
1441 UseMO.TiedTo = DefIdx + 1;
1443 // Inline asm can use the group descriptors to find tied operands, but on
1444 // normal instruction, the tied def must be within the first TiedMax
1446 assert(isInlineAsm() && "DefIdx out of range");
1447 UseMO.TiedTo = TiedMax;
1450 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1451 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1454 /// Given the index of a tied register operand, find the operand it is tied to.
1455 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1456 /// which must exist.
1457 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1458 const MachineOperand &MO = getOperand(OpIdx);
1459 assert(MO.isTied() && "Operand isn't tied");
1461 // Normally TiedTo is in range.
1462 if (MO.TiedTo < TiedMax)
1463 return MO.TiedTo - 1;
1465 // Uses on normal instructions can be out of range.
1466 if (!isInlineAsm()) {
1467 // Normal tied defs must be in the 0..TiedMax-1 range.
1470 // MO is a def. Search for the tied use.
1471 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1472 const MachineOperand &UseMO = getOperand(i);
1473 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1476 llvm_unreachable("Can't find tied use");
1479 // Now deal with inline asm by parsing the operand group descriptor flags.
1480 // Find the beginning of each operand group.
1481 SmallVector<unsigned, 8> GroupIdx;
1482 unsigned OpIdxGroup = ~0u;
1484 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1486 const MachineOperand &FlagMO = getOperand(i);
1487 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1488 unsigned CurGroup = GroupIdx.size();
1489 GroupIdx.push_back(i);
1490 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1491 // OpIdx belongs to this operand group.
1492 if (OpIdx > i && OpIdx < i + NumOps)
1493 OpIdxGroup = CurGroup;
1495 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1497 // Operands in this group are tied to operands in TiedGroup which must be
1498 // earlier. Find the number of operands between the two groups.
1499 unsigned Delta = i - GroupIdx[TiedGroup];
1501 // OpIdx is a use tied to TiedGroup.
1502 if (OpIdxGroup == CurGroup)
1503 return OpIdx - Delta;
1505 // OpIdx is a def tied to this use group.
1506 if (OpIdxGroup == TiedGroup)
1507 return OpIdx + Delta;
1509 llvm_unreachable("Invalid tied operand on inline asm");
1512 /// clearKillInfo - Clears kill flags on all operands.
1514 void MachineInstr::clearKillInfo() {
1515 for (MachineOperand &MO : operands()) {
1516 if (MO.isReg() && MO.isUse())
1517 MO.setIsKill(false);
1521 void MachineInstr::substituteRegister(unsigned FromReg,
1524 const TargetRegisterInfo &RegInfo) {
1525 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1527 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1528 for (MachineOperand &MO : operands()) {
1529 if (!MO.isReg() || MO.getReg() != FromReg)
1531 MO.substPhysReg(ToReg, RegInfo);
1534 for (MachineOperand &MO : operands()) {
1535 if (!MO.isReg() || MO.getReg() != FromReg)
1537 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1542 /// isSafeToMove - Return true if it is safe to move this instruction. If
1543 /// SawStore is set to true, it means that there is a store (or call) between
1544 /// the instruction's location and its intended destination.
1545 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1546 // Ignore stuff that we obviously can't move.
1548 // Treat volatile loads as stores. This is not strictly necessary for
1549 // volatiles, but it is required for atomic loads. It is not allowed to move
1550 // a load across an atomic load with Ordering > Monotonic.
1551 if (mayStore() || isCall() ||
1552 (mayLoad() && hasOrderedMemoryRef())) {
1557 if (isPosition() || isDebugValue() || isTerminator() ||
1558 hasUnmodeledSideEffects())
1561 // See if this instruction does a load. If so, we have to guarantee that the
1562 // loaded value doesn't change between the load and the its intended
1563 // destination. The check for isInvariantLoad gives the targe the chance to
1564 // classify the load as always returning a constant, e.g. a constant pool
1566 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1567 // Otherwise, this is a real load. If there is a store between the load and
1568 // end of block, we can't move it.
1574 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1575 /// or volatile memory reference, or if the information describing the memory
1576 /// reference is not available. Return false if it is known to have no ordered
1577 /// memory references.
1578 bool MachineInstr::hasOrderedMemoryRef() const {
1579 // An instruction known never to access memory won't have a volatile access.
1583 !hasUnmodeledSideEffects())
1586 // Otherwise, if the instruction has no memory reference information,
1587 // conservatively assume it wasn't preserved.
1588 if (memoperands_empty())
1591 // Check if any of our memory operands are ordered.
1592 return any_of(memoperands(), [](const MachineMemOperand *MMO) {
1593 return !MMO->isUnordered();
1597 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1598 /// trap and is loading from a location whose value is invariant across a run of
1600 bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1601 // If the instruction doesn't load at all, it isn't an invariant load.
1605 // If the instruction has lost its memoperands, conservatively assume that
1606 // it may not be an invariant load.
1607 if (memoperands_empty())
1610 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1612 for (MachineMemOperand *MMO : memoperands()) {
1613 if (MMO->isVolatile()) return false;
1614 if (MMO->isStore()) return false;
1615 if (MMO->isInvariant() && MMO->isDereferenceable())
1618 // A load from a constant PseudoSourceValue is invariant.
1619 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1620 if (PSV->isConstant(&MFI))
1623 if (const Value *V = MMO->getValue()) {
1624 // If we have an AliasAnalysis, ask it whether the memory is constant.
1626 AA->pointsToConstantMemory(
1627 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1631 // Otherwise assume conservatively.
1635 // Everything checks out.
1639 /// isConstantValuePHI - If the specified instruction is a PHI that always
1640 /// merges together the same virtual register, return the register, otherwise
1642 unsigned MachineInstr::isConstantValuePHI() const {
1645 assert(getNumOperands() >= 3 &&
1646 "It's illegal to have a PHI without source operands");
1648 unsigned Reg = getOperand(1).getReg();
1649 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1650 if (getOperand(i).getReg() != Reg)
1655 bool MachineInstr::hasUnmodeledSideEffects() const {
1656 if (hasProperty(MCID::UnmodeledSideEffects))
1658 if (isInlineAsm()) {
1659 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1660 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1667 bool MachineInstr::isLoadFoldBarrier() const {
1668 return mayStore() || isCall() || hasUnmodeledSideEffects();
1671 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1673 bool MachineInstr::allDefsAreDead() const {
1674 for (const MachineOperand &MO : operands()) {
1675 if (!MO.isReg() || MO.isUse())
1683 /// copyImplicitOps - Copy implicit register operands from specified
1684 /// instruction to this instruction.
1685 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1686 const MachineInstr &MI) {
1687 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1689 const MachineOperand &MO = MI.getOperand(i);
1690 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1695 LLVM_DUMP_METHOD void MachineInstr::dump(const TargetInstrInfo *TII) const {
1696 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1698 print(dbgs(), false /* SkipOpers */, TII);
1702 void MachineInstr::print(raw_ostream &OS, bool SkipOpers,
1703 const TargetInstrInfo *TII) const {
1704 const Module *M = nullptr;
1705 if (const MachineBasicBlock *MBB = getParent())
1706 if (const MachineFunction *MF = MBB->getParent())
1707 M = MF->getFunction()->getParent();
1709 ModuleSlotTracker MST(M);
1710 print(OS, MST, SkipOpers, TII);
1713 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1714 bool SkipOpers, const TargetInstrInfo *TII) const {
1715 // We can be a bit tidier if we know the MachineFunction.
1716 const MachineFunction *MF = nullptr;
1717 const TargetRegisterInfo *TRI = nullptr;
1718 const MachineRegisterInfo *MRI = nullptr;
1719 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1721 if (const MachineBasicBlock *MBB = getParent()) {
1722 MF = MBB->getParent();
1724 MRI = &MF->getRegInfo();
1725 TRI = MF->getSubtarget().getRegisterInfo();
1727 TII = MF->getSubtarget().getInstrInfo();
1728 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
1732 // Save a list of virtual registers.
1733 SmallVector<unsigned, 8> VirtRegs;
1735 // Print explicitly defined operands on the left of an assignment syntax.
1736 unsigned StartOp = 0, e = getNumOperands();
1737 for (; StartOp < e && getOperand(StartOp).isReg() &&
1738 getOperand(StartOp).isDef() &&
1739 !getOperand(StartOp).isImplicit();
1741 if (StartOp != 0) OS << ", ";
1742 getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
1743 unsigned Reg = getOperand(StartOp).getReg();
1744 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1745 VirtRegs.push_back(Reg);
1746 LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
1748 OS << '(' << Ty << ')';
1755 // Print the opcode name.
1757 OS << TII->getName(getOpcode());
1764 // Print the rest of the operands.
1765 bool OmittedAnyCallClobbers = false;
1766 bool FirstOp = true;
1767 unsigned AsmDescOp = ~0u;
1768 unsigned AsmOpCount = 0;
1770 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1771 // Print asm string.
1773 getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1775 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1776 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1777 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1778 OS << " [sideeffect]";
1779 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1781 if (ExtraInfo & InlineAsm::Extra_MayStore)
1782 OS << " [maystore]";
1783 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1784 OS << " [isconvergent]";
1785 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1786 OS << " [alignstack]";
1787 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1788 OS << " [attdialect]";
1789 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1790 OS << " [inteldialect]";
1792 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1796 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1797 const MachineOperand &MO = getOperand(i);
1799 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1800 VirtRegs.push_back(MO.getReg());
1802 // Omit call-clobbered registers which aren't used anywhere. This makes
1803 // call instructions much less noisy on targets where calls clobber lots
1804 // of registers. Don't rely on MO.isDead() because we may be called before
1805 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1806 if (MRI && isCall() &&
1807 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1808 unsigned Reg = MO.getReg();
1809 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1810 if (MRI->use_empty(Reg)) {
1811 bool HasAliasLive = false;
1812 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1813 unsigned AliasReg = *AI;
1814 if (!MRI->use_empty(AliasReg)) {
1815 HasAliasLive = true;
1819 if (!HasAliasLive) {
1820 OmittedAnyCallClobbers = true;
1827 if (FirstOp) FirstOp = false; else OS << ",";
1829 if (i < getDesc().NumOperands) {
1830 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1831 if (MCOI.isPredicate())
1833 if (MCOI.isOptionalDef())
1836 if (isDebugValue() && MO.isMetadata()) {
1837 // Pretty print DBG_VALUE instructions.
1838 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1839 if (DIV && !DIV->getName().empty())
1840 OS << "!\"" << DIV->getName() << '\"';
1842 MO.print(OS, MST, TRI);
1843 } else if (TRI && (isInsertSubreg() || isRegSequence() ||
1844 (isSubregToReg() && i == 3)) && MO.isImm()) {
1845 OS << TRI->getSubRegIndexName(MO.getImm());
1846 } else if (i == AsmDescOp && MO.isImm()) {
1847 // Pretty print the inline asm operand descriptor.
1848 OS << '$' << AsmOpCount++;
1849 unsigned Flag = MO.getImm();
1850 switch (InlineAsm::getKind(Flag)) {
1851 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1852 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1853 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1854 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1855 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1856 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1857 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1861 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1862 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1864 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1866 OS << ":RC" << RCID;
1869 if (InlineAsm::isMemKind(Flag)) {
1870 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1872 case InlineAsm::Constraint_es: OS << ":es"; break;
1873 case InlineAsm::Constraint_i: OS << ":i"; break;
1874 case InlineAsm::Constraint_m: OS << ":m"; break;
1875 case InlineAsm::Constraint_o: OS << ":o"; break;
1876 case InlineAsm::Constraint_v: OS << ":v"; break;
1877 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1878 case InlineAsm::Constraint_R: OS << ":R"; break;
1879 case InlineAsm::Constraint_S: OS << ":S"; break;
1880 case InlineAsm::Constraint_T: OS << ":T"; break;
1881 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1882 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1883 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1884 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1885 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1886 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1887 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1888 case InlineAsm::Constraint_X: OS << ":X"; break;
1889 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1890 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1891 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1892 default: OS << ":?"; break;
1896 unsigned TiedTo = 0;
1897 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1898 OS << " tiedto:$" << TiedTo;
1902 // Compute the index of the next operand descriptor.
1903 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1905 MO.print(OS, MST, TRI);
1908 // Briefly indicate whether any call clobbers were omitted.
1909 if (OmittedAnyCallClobbers) {
1910 if (!FirstOp) OS << ",";
1914 bool HaveSemi = false;
1915 const unsigned PrintableFlags = FrameSetup | FrameDestroy;
1916 if (Flags & PrintableFlags) {
1923 if (Flags & FrameSetup)
1926 if (Flags & FrameDestroy)
1927 OS << "FrameDestroy";
1930 if (!memoperands_empty()) {
1937 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1939 (*i)->print(OS, MST);
1940 if (std::next(i) != e)
1945 // Print the regclass of any virtual registers encountered.
1946 if (MRI && !VirtRegs.empty()) {
1951 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1952 const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]);
1955 // Generic virtual registers do not have register classes.
1956 if (RC.is<const RegisterBank *>())
1957 OS << " " << RC.get<const RegisterBank *>()->getName();
1960 << TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
1961 OS << ':' << PrintReg(VirtRegs[i]);
1962 for (unsigned j = i+1; j != VirtRegs.size();) {
1963 if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
1967 if (VirtRegs[i] != VirtRegs[j])
1968 OS << "," << PrintReg(VirtRegs[j]);
1969 VirtRegs.erase(VirtRegs.begin()+j);
1974 // Print debug location information.
1975 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1978 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1979 OS << " line no:" << DV->getLine();
1980 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1981 DebugLoc InlinedAtDL(InlinedAt);
1982 if (InlinedAtDL && MF) {
1983 OS << " inlined @[ ";
1984 InlinedAtDL.print(OS);
1988 if (isIndirectDebugValue())
1990 } else if (debugLoc && MF) {
2000 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
2001 const TargetRegisterInfo *RegInfo,
2002 bool AddIfNotFound) {
2003 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
2004 bool hasAliases = isPhysReg &&
2005 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
2007 SmallVector<unsigned,4> DeadOps;
2008 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2009 MachineOperand &MO = getOperand(i);
2010 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2013 // DEBUG_VALUE nodes do not contribute to code generation and should
2014 // always be ignored. Failure to do so may result in trying to modify
2015 // KILL flags on DEBUG_VALUE nodes.
2019 unsigned Reg = MO.getReg();
2023 if (Reg == IncomingReg) {
2026 // The register is already marked kill.
2028 if (isPhysReg && isRegTiedToDefOperand(i))
2029 // Two-address uses of physregs must not be marked kill.
2034 } else if (hasAliases && MO.isKill() &&
2035 TargetRegisterInfo::isPhysicalRegister(Reg)) {
2036 // A super-register kill already exists.
2037 if (RegInfo->isSuperRegister(IncomingReg, Reg))
2039 if (RegInfo->isSubRegister(IncomingReg, Reg))
2040 DeadOps.push_back(i);
2044 // Trim unneeded kill operands.
2045 while (!DeadOps.empty()) {
2046 unsigned OpIdx = DeadOps.back();
2047 if (getOperand(OpIdx).isImplicit())
2048 RemoveOperand(OpIdx);
2050 getOperand(OpIdx).setIsKill(false);
2054 // If not found, this means an alias of one of the operands is killed. Add a
2055 // new implicit operand if required.
2056 if (!Found && AddIfNotFound) {
2057 addOperand(MachineOperand::CreateReg(IncomingReg,
2066 void MachineInstr::clearRegisterKills(unsigned Reg,
2067 const TargetRegisterInfo *RegInfo) {
2068 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
2070 for (MachineOperand &MO : operands()) {
2071 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2073 unsigned OpReg = MO.getReg();
2074 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
2075 MO.setIsKill(false);
2079 bool MachineInstr::addRegisterDead(unsigned Reg,
2080 const TargetRegisterInfo *RegInfo,
2081 bool AddIfNotFound) {
2082 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
2083 bool hasAliases = isPhysReg &&
2084 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2086 SmallVector<unsigned,4> DeadOps;
2087 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2088 MachineOperand &MO = getOperand(i);
2089 if (!MO.isReg() || !MO.isDef())
2091 unsigned MOReg = MO.getReg();
2098 } else if (hasAliases && MO.isDead() &&
2099 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
2100 // There exists a super-register that's marked dead.
2101 if (RegInfo->isSuperRegister(Reg, MOReg))
2103 if (RegInfo->isSubRegister(Reg, MOReg))
2104 DeadOps.push_back(i);
2108 // Trim unneeded dead operands.
2109 while (!DeadOps.empty()) {
2110 unsigned OpIdx = DeadOps.back();
2111 if (getOperand(OpIdx).isImplicit())
2112 RemoveOperand(OpIdx);
2114 getOperand(OpIdx).setIsDead(false);
2118 // If not found, this means an alias of one of the operands is dead. Add a
2119 // new implicit operand if required.
2120 if (Found || !AddIfNotFound)
2123 addOperand(MachineOperand::CreateReg(Reg,
2131 void MachineInstr::clearRegisterDeads(unsigned Reg) {
2132 for (MachineOperand &MO : operands()) {
2133 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2135 MO.setIsDead(false);
2139 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
2140 for (MachineOperand &MO : operands()) {
2141 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2143 MO.setIsUndef(IsUndef);
2147 void MachineInstr::addRegisterDefined(unsigned Reg,
2148 const TargetRegisterInfo *RegInfo) {
2149 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
2150 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
2154 for (const MachineOperand &MO : operands()) {
2155 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2156 MO.getSubReg() == 0)
2160 addOperand(MachineOperand::CreateReg(Reg,
2165 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
2166 const TargetRegisterInfo &TRI) {
2167 bool HasRegMask = false;
2168 for (MachineOperand &MO : operands()) {
2169 if (MO.isRegMask()) {
2173 if (!MO.isReg() || !MO.isDef()) continue;
2174 unsigned Reg = MO.getReg();
2175 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
2176 // If there are no uses, including partial uses, the def is dead.
2177 if (none_of(UsedRegs,
2178 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
2182 // This is a call with a register mask operand.
2183 // Mask clobbers are always dead, so add defs for the non-dead defines.
2185 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2187 addRegisterDefined(*I, &TRI);
2191 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2192 // Build up a buffer of hash code components.
2193 SmallVector<size_t, 8> HashComponents;
2194 HashComponents.reserve(MI->getNumOperands() + 1);
2195 HashComponents.push_back(MI->getOpcode());
2196 for (const MachineOperand &MO : MI->operands()) {
2197 if (MO.isReg() && MO.isDef() &&
2198 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
2199 continue; // Skip virtual register defs.
2201 HashComponents.push_back(hash_value(MO));
2203 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2206 void MachineInstr::emitError(StringRef Msg) const {
2207 // Find the source location cookie.
2208 unsigned LocCookie = 0;
2209 const MDNode *LocMD = nullptr;
2210 for (unsigned i = getNumOperands(); i != 0; --i) {
2211 if (getOperand(i-1).isMetadata() &&
2212 (LocMD = getOperand(i-1).getMetadata()) &&
2213 LocMD->getNumOperands() != 0) {
2214 if (const ConstantInt *CI =
2215 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2216 LocCookie = CI->getZExtValue();
2222 if (const MachineBasicBlock *MBB = getParent())
2223 if (const MachineFunction *MF = MBB->getParent())
2224 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2225 report_fatal_error(Msg);
2228 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2229 const MCInstrDesc &MCID, bool IsIndirect,
2230 unsigned Reg, unsigned Offset,
2231 const MDNode *Variable, const MDNode *Expr) {
2232 assert(isa<DILocalVariable>(Variable) && "not a variable");
2233 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2234 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2235 "Expected inlined-at fields to agree");
2237 return BuildMI(MF, DL, MCID)
2238 .addReg(Reg, RegState::Debug)
2240 .addMetadata(Variable)
2243 assert(Offset == 0 && "A direct address cannot have an offset.");
2244 return BuildMI(MF, DL, MCID)
2245 .addReg(Reg, RegState::Debug)
2246 .addReg(0U, RegState::Debug)
2247 .addMetadata(Variable)
2252 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2253 MachineBasicBlock::iterator I,
2254 const DebugLoc &DL, const MCInstrDesc &MCID,
2255 bool IsIndirect, unsigned Reg,
2256 unsigned Offset, const MDNode *Variable,
2257 const MDNode *Expr) {
2258 assert(isa<DILocalVariable>(Variable) && "not a variable");
2259 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2260 MachineFunction &MF = *BB.getParent();
2262 BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, Variable, Expr);
2264 return MachineInstrBuilder(MF, MI);