1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Type.h"
19 #include "llvm/Value.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetInstrDesc.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Analysis/AliasAnalysis.h"
30 #include "llvm/Analysis/DebugInfo.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/LeakDetector.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/FoldingSet.h"
38 //===----------------------------------------------------------------------===//
39 // MachineOperand Implementation
40 //===----------------------------------------------------------------------===//
42 /// AddRegOperandToRegInfo - Add this register operand to the specified
43 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
44 /// explicitly nulled out.
45 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
46 assert(isReg() && "Can only add reg operand to use lists");
48 // If the reginfo pointer is null, just explicitly null out or next/prev
49 // pointers, to ensure they are not garbage.
51 Contents.Reg.Prev = 0;
52 Contents.Reg.Next = 0;
56 // Otherwise, add this operand to the head of the registers use/def list.
57 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
59 // For SSA values, we prefer to keep the definition at the start of the list.
60 // we do this by skipping over the definition if it is at the head of the
62 if (*Head && (*Head)->isDef())
63 Head = &(*Head)->Contents.Reg.Next;
65 Contents.Reg.Next = *Head;
66 if (Contents.Reg.Next) {
67 assert(getReg() == Contents.Reg.Next->getReg() &&
68 "Different regs on the same list!");
69 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
72 Contents.Reg.Prev = Head;
76 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
77 /// MachineRegisterInfo it is linked with.
78 void MachineOperand::RemoveRegOperandFromRegInfo() {
79 assert(isOnRegUseList() && "Reg operand is not on a use list");
80 // Unlink this from the doubly linked list of operands.
81 MachineOperand *NextOp = Contents.Reg.Next;
82 *Contents.Reg.Prev = NextOp;
84 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
85 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
87 Contents.Reg.Prev = 0;
88 Contents.Reg.Next = 0;
91 void MachineOperand::setReg(unsigned Reg) {
92 if (getReg() == Reg) return; // No change.
94 // Otherwise, we have to change the register. If this operand is embedded
95 // into a machine function, we need to update the old and new register's
97 if (MachineInstr *MI = getParent())
98 if (MachineBasicBlock *MBB = MI->getParent())
99 if (MachineFunction *MF = MBB->getParent()) {
100 RemoveRegOperandFromRegInfo();
101 Contents.Reg.RegNo = Reg;
102 AddRegOperandToRegInfo(&MF->getRegInfo());
106 // Otherwise, just change the register, no problem. :)
107 Contents.Reg.RegNo = Reg;
110 /// ChangeToImmediate - Replace this operand with a new immediate operand of
111 /// the specified value. If an operand is known to be an immediate already,
112 /// the setImm method should be used.
113 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114 // If this operand is currently a register operand, and if this is in a
115 // function, deregister the operand from the register's use/def list.
116 if (isReg() && getParent() && getParent()->getParent() &&
117 getParent()->getParent()->getParent())
118 RemoveRegOperandFromRegInfo();
120 OpKind = MO_Immediate;
121 Contents.ImmVal = ImmVal;
124 /// ChangeToRegister - Replace this operand with a new register operand of
125 /// the specified value. If an operand is known to be an register already,
126 /// the setReg method should be used.
127 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
128 bool isKill, bool isDead, bool isUndef) {
129 // If this operand is already a register operand, use setReg to update the
130 // register's use/def lists.
132 assert(!isEarlyClobber());
135 // Otherwise, change this to a register and set the reg#.
136 OpKind = MO_Register;
137 Contents.Reg.RegNo = Reg;
139 // If this operand is embedded in a function, add the operand to the
140 // register's use/def list.
141 if (MachineInstr *MI = getParent())
142 if (MachineBasicBlock *MBB = MI->getParent())
143 if (MachineFunction *MF = MBB->getParent())
144 AddRegOperandToRegInfo(&MF->getRegInfo());
152 IsEarlyClobber = false;
156 /// isIdenticalTo - Return true if this operand is identical to the specified
158 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
159 if (getType() != Other.getType() ||
160 getTargetFlags() != Other.getTargetFlags())
164 default: llvm_unreachable("Unrecognized operand type");
165 case MachineOperand::MO_Register:
166 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
167 getSubReg() == Other.getSubReg();
168 case MachineOperand::MO_Immediate:
169 return getImm() == Other.getImm();
170 case MachineOperand::MO_FPImmediate:
171 return getFPImm() == Other.getFPImm();
172 case MachineOperand::MO_MachineBasicBlock:
173 return getMBB() == Other.getMBB();
174 case MachineOperand::MO_FrameIndex:
175 return getIndex() == Other.getIndex();
176 case MachineOperand::MO_ConstantPoolIndex:
177 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
178 case MachineOperand::MO_JumpTableIndex:
179 return getIndex() == Other.getIndex();
180 case MachineOperand::MO_GlobalAddress:
181 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
182 case MachineOperand::MO_ExternalSymbol:
183 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
184 getOffset() == Other.getOffset();
185 case MachineOperand::MO_BlockAddress:
186 return getBlockAddress() == Other.getBlockAddress();
190 /// print - Print the specified machine operand.
192 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
193 // If the instruction is embedded into a basic block, we can find the
194 // target info for the instruction.
196 if (const MachineInstr *MI = getParent())
197 if (const MachineBasicBlock *MBB = MI->getParent())
198 if (const MachineFunction *MF = MBB->getParent())
199 TM = &MF->getTarget();
202 case MachineOperand::MO_Register:
203 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
204 OS << "%reg" << getReg();
207 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
209 OS << "%physreg" << getReg();
212 if (getSubReg() != 0)
213 OS << ':' << getSubReg();
215 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
218 bool NeedComma = false;
220 if (NeedComma) OS << ',';
221 if (isEarlyClobber())
222 OS << "earlyclobber,";
227 } else if (isImplicit()) {
232 if (isKill() || isDead() || isUndef()) {
233 if (NeedComma) OS << ',';
234 if (isKill()) OS << "kill";
235 if (isDead()) OS << "dead";
237 if (isKill() || isDead())
245 case MachineOperand::MO_Immediate:
248 case MachineOperand::MO_FPImmediate:
249 if (getFPImm()->getType()->isFloatTy())
250 OS << getFPImm()->getValueAPF().convertToFloat();
252 OS << getFPImm()->getValueAPF().convertToDouble();
254 case MachineOperand::MO_MachineBasicBlock:
255 OS << "<BB#" << getMBB()->getNumber() << ">";
257 case MachineOperand::MO_FrameIndex:
258 OS << "<fi#" << getIndex() << '>';
260 case MachineOperand::MO_ConstantPoolIndex:
261 OS << "<cp#" << getIndex();
262 if (getOffset()) OS << "+" << getOffset();
265 case MachineOperand::MO_JumpTableIndex:
266 OS << "<jt#" << getIndex() << '>';
268 case MachineOperand::MO_GlobalAddress:
270 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
271 if (getOffset()) OS << "+" << getOffset();
274 case MachineOperand::MO_ExternalSymbol:
275 OS << "<es:" << getSymbolName();
276 if (getOffset()) OS << "+" << getOffset();
279 case MachineOperand::MO_BlockAddress:
281 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
285 llvm_unreachable("Unrecognized operand type");
288 if (unsigned TF = getTargetFlags())
289 OS << "[TF=" << TF << ']';
292 //===----------------------------------------------------------------------===//
293 // MachineMemOperand Implementation
294 //===----------------------------------------------------------------------===//
296 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
297 int64_t o, uint64_t s, unsigned int a)
298 : Offset(o), Size(s), V(v),
299 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
300 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
301 assert((isLoad() || isStore()) && "Not a load/store!");
304 /// Profile - Gather unique data for the object.
306 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
307 ID.AddInteger(Offset);
310 ID.AddInteger(Flags);
313 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
314 // The Value and Offset may differ due to CSE. But the flags and size
315 // should be the same.
316 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
317 assert(MMO->getSize() == getSize() && "Size mismatch!");
319 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
320 // Update the alignment value.
321 Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3);
322 // Also update the base and offset, because the new alignment may
323 // not be applicable with the old ones.
325 Offset = MMO->getOffset();
329 /// getAlignment - Return the minimum known alignment in bytes of the
330 /// actual memory reference.
331 uint64_t MachineMemOperand::getAlignment() const {
332 return MinAlign(getBaseAlignment(), getOffset());
335 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
336 assert((MMO.isLoad() || MMO.isStore()) &&
337 "SV has to be a load, store or both.");
339 if (MMO.isVolatile())
348 // Print the address information.
353 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
355 // If the alignment of the memory reference itself differs from the alignment
356 // of the base pointer, print the base alignment explicitly, next to the base
358 if (MMO.getBaseAlignment() != MMO.getAlignment())
359 OS << "(align=" << MMO.getBaseAlignment() << ")";
361 if (MMO.getOffset() != 0)
362 OS << "+" << MMO.getOffset();
365 // Print the alignment of the reference.
366 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
367 MMO.getBaseAlignment() != MMO.getSize())
368 OS << "(align=" << MMO.getAlignment() << ")";
373 //===----------------------------------------------------------------------===//
374 // MachineInstr Implementation
375 //===----------------------------------------------------------------------===//
377 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
378 /// TID NULL and no operands.
379 MachineInstr::MachineInstr()
380 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
381 Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
382 // Make sure that we get added to a machine basicblock
383 LeakDetector::addGarbageObject(this);
386 void MachineInstr::addImplicitDefUseOperands() {
387 if (TID->ImplicitDefs)
388 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
389 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
390 if (TID->ImplicitUses)
391 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
392 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
395 /// MachineInstr ctor - This constructor create a MachineInstr and add the
396 /// implicit operands. It reserves space for number of operands specified by
397 /// TargetInstrDesc or the numOperands if it is not zero. (for
398 /// instructions with variable number of operands).
399 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
400 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
401 MemRefs(0), MemRefsEnd(0), Parent(0),
402 debugLoc(DebugLoc::getUnknownLoc()) {
403 if (!NoImp && TID->getImplicitDefs())
404 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
406 if (!NoImp && TID->getImplicitUses())
407 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
409 Operands.reserve(NumImplicitOps + TID->getNumOperands());
411 addImplicitDefUseOperands();
412 // Make sure that we get added to a machine basicblock
413 LeakDetector::addGarbageObject(this);
416 /// MachineInstr ctor - As above, but with a DebugLoc.
417 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
419 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
420 Parent(0), debugLoc(dl) {
421 if (!NoImp && TID->getImplicitDefs())
422 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
424 if (!NoImp && TID->getImplicitUses())
425 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
427 Operands.reserve(NumImplicitOps + TID->getNumOperands());
429 addImplicitDefUseOperands();
430 // Make sure that we get added to a machine basicblock
431 LeakDetector::addGarbageObject(this);
434 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
435 /// that the MachineInstr is created and added to the end of the specified
438 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
439 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
440 MemRefs(0), MemRefsEnd(0), Parent(0),
441 debugLoc(DebugLoc::getUnknownLoc()) {
442 assert(MBB && "Cannot use inserting ctor with null basic block!");
443 if (TID->ImplicitDefs)
444 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
446 if (TID->ImplicitUses)
447 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
449 Operands.reserve(NumImplicitOps + TID->getNumOperands());
450 addImplicitDefUseOperands();
451 // Make sure that we get added to a machine basicblock
452 LeakDetector::addGarbageObject(this);
453 MBB->push_back(this); // Add instruction to end of basic block!
456 /// MachineInstr ctor - As above, but with a DebugLoc.
458 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
459 const TargetInstrDesc &tid)
460 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
461 Parent(0), debugLoc(dl) {
462 assert(MBB && "Cannot use inserting ctor with null basic block!");
463 if (TID->ImplicitDefs)
464 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
466 if (TID->ImplicitUses)
467 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
469 Operands.reserve(NumImplicitOps + TID->getNumOperands());
470 addImplicitDefUseOperands();
471 // Make sure that we get added to a machine basicblock
472 LeakDetector::addGarbageObject(this);
473 MBB->push_back(this); // Add instruction to end of basic block!
476 /// MachineInstr ctor - Copies MachineInstr arg exactly
478 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
479 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
480 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
481 Parent(0), debugLoc(MI.getDebugLoc()) {
482 Operands.reserve(MI.getNumOperands());
485 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
486 addOperand(MI.getOperand(i));
487 NumImplicitOps = MI.NumImplicitOps;
489 // Set parent to null.
492 LeakDetector::addGarbageObject(this);
495 MachineInstr::~MachineInstr() {
496 LeakDetector::removeGarbageObject(this);
498 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
499 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
500 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
501 "Reg operand def/use list corrupted");
506 /// getRegInfo - If this instruction is embedded into a MachineFunction,
507 /// return the MachineRegisterInfo object for the current function, otherwise
509 MachineRegisterInfo *MachineInstr::getRegInfo() {
510 if (MachineBasicBlock *MBB = getParent())
511 return &MBB->getParent()->getRegInfo();
515 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
516 /// this instruction from their respective use lists. This requires that the
517 /// operands already be on their use lists.
518 void MachineInstr::RemoveRegOperandsFromUseLists() {
519 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
520 if (Operands[i].isReg())
521 Operands[i].RemoveRegOperandFromRegInfo();
525 /// AddRegOperandsToUseLists - Add all of the register operands in
526 /// this instruction from their respective use lists. This requires that the
527 /// operands not be on their use lists yet.
528 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
529 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
530 if (Operands[i].isReg())
531 Operands[i].AddRegOperandToRegInfo(&RegInfo);
536 /// addOperand - Add the specified operand to the instruction. If it is an
537 /// implicit operand, it is added to the end of the operand list. If it is
538 /// an explicit operand it is added at the end of the explicit operand list
539 /// (before the first implicit operand).
540 void MachineInstr::addOperand(const MachineOperand &Op) {
541 bool isImpReg = Op.isReg() && Op.isImplicit();
542 assert((isImpReg || !OperandsComplete()) &&
543 "Trying to add an operand to a machine instr that is already done!");
545 MachineRegisterInfo *RegInfo = getRegInfo();
547 // If we are adding the operand to the end of the list, our job is simpler.
548 // This is true most of the time, so this is a reasonable optimization.
549 if (isImpReg || NumImplicitOps == 0) {
550 // We can only do this optimization if we know that the operand list won't
552 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
553 Operands.push_back(Op);
555 // Set the parent of the operand.
556 Operands.back().ParentMI = this;
558 // If the operand is a register, update the operand's use list.
560 Operands.back().AddRegOperandToRegInfo(RegInfo);
561 // If the register operand is flagged as early, mark the operand as such
562 unsigned OpNo = Operands.size() - 1;
563 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
564 Operands[OpNo].setIsEarlyClobber(true);
570 // Otherwise, we have to insert a real operand before any implicit ones.
571 unsigned OpNo = Operands.size()-NumImplicitOps;
573 // If this instruction isn't embedded into a function, then we don't need to
574 // update any operand lists.
576 // Simple insertion, no reginfo update needed for other register operands.
577 Operands.insert(Operands.begin()+OpNo, Op);
578 Operands[OpNo].ParentMI = this;
580 // Do explicitly set the reginfo for this operand though, to ensure the
581 // next/prev fields are properly nulled out.
582 if (Operands[OpNo].isReg()) {
583 Operands[OpNo].AddRegOperandToRegInfo(0);
584 // If the register operand is flagged as early, mark the operand as such
585 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
586 Operands[OpNo].setIsEarlyClobber(true);
589 } else if (Operands.size()+1 <= Operands.capacity()) {
590 // Otherwise, we have to remove register operands from their register use
591 // list, add the operand, then add the register operands back to their use
592 // list. This also must handle the case when the operand list reallocates
593 // to somewhere else.
595 // If insertion of this operand won't cause reallocation of the operand
596 // list, just remove the implicit operands, add the operand, then re-add all
597 // the rest of the operands.
598 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
599 assert(Operands[i].isReg() && "Should only be an implicit reg!");
600 Operands[i].RemoveRegOperandFromRegInfo();
603 // Add the operand. If it is a register, add it to the reg list.
604 Operands.insert(Operands.begin()+OpNo, Op);
605 Operands[OpNo].ParentMI = this;
607 if (Operands[OpNo].isReg()) {
608 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
609 // If the register operand is flagged as early, mark the operand as such
610 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
611 Operands[OpNo].setIsEarlyClobber(true);
614 // Re-add all the implicit ops.
615 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
616 assert(Operands[i].isReg() && "Should only be an implicit reg!");
617 Operands[i].AddRegOperandToRegInfo(RegInfo);
620 // Otherwise, we will be reallocating the operand list. Remove all reg
621 // operands from their list, then readd them after the operand list is
623 RemoveRegOperandsFromUseLists();
625 Operands.insert(Operands.begin()+OpNo, Op);
626 Operands[OpNo].ParentMI = this;
628 // Re-add all the operands.
629 AddRegOperandsToUseLists(*RegInfo);
631 // If the register operand is flagged as early, mark the operand as such
632 if (Operands[OpNo].isReg()
633 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
634 Operands[OpNo].setIsEarlyClobber(true);
638 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
639 /// fewer operand than it started with.
641 void MachineInstr::RemoveOperand(unsigned OpNo) {
642 assert(OpNo < Operands.size() && "Invalid operand number");
644 // Special case removing the last one.
645 if (OpNo == Operands.size()-1) {
646 // If needed, remove from the reg def/use list.
647 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
648 Operands.back().RemoveRegOperandFromRegInfo();
654 // Otherwise, we are removing an interior operand. If we have reginfo to
655 // update, remove all operands that will be shifted down from their reg lists,
656 // move everything down, then re-add them.
657 MachineRegisterInfo *RegInfo = getRegInfo();
659 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
660 if (Operands[i].isReg())
661 Operands[i].RemoveRegOperandFromRegInfo();
665 Operands.erase(Operands.begin()+OpNo);
668 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
669 if (Operands[i].isReg())
670 Operands[i].AddRegOperandToRegInfo(RegInfo);
675 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
676 /// This function should be used only occasionally. The setMemRefs function
677 /// is the primary method for setting up a MachineInstr's MemRefs list.
678 void MachineInstr::addMemOperand(MachineFunction &MF,
679 MachineMemOperand *MO) {
680 mmo_iterator OldMemRefs = MemRefs;
681 mmo_iterator OldMemRefsEnd = MemRefsEnd;
683 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
684 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
685 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
687 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
688 NewMemRefs[NewNum - 1] = MO;
690 MemRefs = NewMemRefs;
691 MemRefsEnd = NewMemRefsEnd;
694 /// removeFromParent - This method unlinks 'this' from the containing basic
695 /// block, and returns it, but does not delete it.
696 MachineInstr *MachineInstr::removeFromParent() {
697 assert(getParent() && "Not embedded in a basic block!");
698 getParent()->remove(this);
703 /// eraseFromParent - This method unlinks 'this' from the containing basic
704 /// block, and deletes it.
705 void MachineInstr::eraseFromParent() {
706 assert(getParent() && "Not embedded in a basic block!");
707 getParent()->erase(this);
711 /// OperandComplete - Return true if it's illegal to add a new operand
713 bool MachineInstr::OperandsComplete() const {
714 unsigned short NumOperands = TID->getNumOperands();
715 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
716 return true; // Broken: we have all the operands of this instruction!
720 /// getNumExplicitOperands - Returns the number of non-implicit operands.
722 unsigned MachineInstr::getNumExplicitOperands() const {
723 unsigned NumOperands = TID->getNumOperands();
724 if (!TID->isVariadic())
727 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
728 const MachineOperand &MO = getOperand(i);
729 if (!MO.isReg() || !MO.isImplicit())
736 /// isLabel - Returns true if the MachineInstr represents a label.
738 bool MachineInstr::isLabel() const {
739 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
740 getOpcode() == TargetInstrInfo::EH_LABEL ||
741 getOpcode() == TargetInstrInfo::GC_LABEL;
744 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
746 bool MachineInstr::isDebugLabel() const {
747 return getOpcode() == TargetInstrInfo::DBG_LABEL;
750 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
751 /// the specific register or -1 if it is not found. It further tightens
752 /// the search criteria to a use that kills the register if isKill is true.
753 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
754 const TargetRegisterInfo *TRI) const {
755 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
756 const MachineOperand &MO = getOperand(i);
757 if (!MO.isReg() || !MO.isUse())
759 unsigned MOReg = MO.getReg();
764 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
765 TargetRegisterInfo::isPhysicalRegister(Reg) &&
766 TRI->isSubRegister(MOReg, Reg)))
767 if (!isKill || MO.isKill())
773 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
774 /// the specified register or -1 if it is not found. If isDead is true, defs
775 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
776 /// also checks if there is a def of a super-register.
777 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
778 const TargetRegisterInfo *TRI) const {
779 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
780 const MachineOperand &MO = getOperand(i);
781 if (!MO.isReg() || !MO.isDef())
783 unsigned MOReg = MO.getReg();
786 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
787 TargetRegisterInfo::isPhysicalRegister(Reg) &&
788 TRI->isSubRegister(MOReg, Reg)))
789 if (!isDead || MO.isDead())
795 /// findFirstPredOperandIdx() - Find the index of the first operand in the
796 /// operand list that is used to represent the predicate. It returns -1 if
798 int MachineInstr::findFirstPredOperandIdx() const {
799 const TargetInstrDesc &TID = getDesc();
800 if (TID.isPredicable()) {
801 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
802 if (TID.OpInfo[i].isPredicate())
809 /// isRegTiedToUseOperand - Given the index of a register def operand,
810 /// check if the register def is tied to a source operand, due to either
811 /// two-address elimination or inline assembly constraints. Returns the
812 /// first tied use operand index by reference is UseOpIdx is not null.
814 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
815 if (getOpcode() == TargetInstrInfo::INLINEASM) {
816 assert(DefOpIdx >= 2);
817 const MachineOperand &MO = getOperand(DefOpIdx);
818 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
820 // Determine the actual operand index that corresponds to this index.
822 unsigned DefPart = 0;
823 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
824 const MachineOperand &FMO = getOperand(i);
825 // After the normal asm operands there may be additional imp-def regs.
828 // Skip over this def.
829 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
830 unsigned PrevDef = i + 1;
831 i = PrevDef + NumOps;
833 DefPart = DefOpIdx - PrevDef;
838 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
839 const MachineOperand &FMO = getOperand(i);
842 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
845 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
848 *UseOpIdx = (unsigned)i + 1 + DefPart;
855 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
856 const TargetInstrDesc &TID = getDesc();
857 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
858 const MachineOperand &MO = getOperand(i);
859 if (MO.isReg() && MO.isUse() &&
860 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
862 *UseOpIdx = (unsigned)i;
869 /// isRegTiedToDefOperand - Return true if the operand of the specified index
870 /// is a register use and it is tied to an def operand. It also returns the def
871 /// operand index by reference.
873 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
874 if (getOpcode() == TargetInstrInfo::INLINEASM) {
875 const MachineOperand &MO = getOperand(UseOpIdx);
876 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
879 // Find the flag operand corresponding to UseOpIdx
880 unsigned FlagIdx, NumOps=0;
881 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
882 const MachineOperand &UFMO = getOperand(FlagIdx);
883 // After the normal asm operands there may be additional imp-def regs.
886 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
887 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
888 if (UseOpIdx < FlagIdx+NumOps+1)
891 if (FlagIdx >= UseOpIdx)
893 const MachineOperand &UFMO = getOperand(FlagIdx);
895 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
900 // Remember to adjust the index. First operand is asm string, then there
901 // is a flag for each.
903 const MachineOperand &FMO = getOperand(DefIdx);
905 // Skip over this def.
906 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
909 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
915 const TargetInstrDesc &TID = getDesc();
916 if (UseOpIdx >= TID.getNumOperands())
918 const MachineOperand &MO = getOperand(UseOpIdx);
919 if (!MO.isReg() || !MO.isUse())
921 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
925 *DefOpIdx = (unsigned)DefIdx;
929 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
931 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
932 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
933 const MachineOperand &MO = MI->getOperand(i);
934 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
936 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
937 MachineOperand &MOp = getOperand(j);
938 if (!MOp.isIdenticalTo(MO))
949 /// copyPredicates - Copies predicate operand(s) from MI.
950 void MachineInstr::copyPredicates(const MachineInstr *MI) {
951 const TargetInstrDesc &TID = MI->getDesc();
952 if (!TID.isPredicable())
954 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
955 if (TID.OpInfo[i].isPredicate()) {
956 // Predicated operands must be last operands.
957 addOperand(MI->getOperand(i));
962 /// isSafeToMove - Return true if it is safe to move this instruction. If
963 /// SawStore is set to true, it means that there is a store (or call) between
964 /// the instruction's location and its intended destination.
965 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
967 AliasAnalysis *AA) const {
968 // Ignore stuff that we obviously can't move.
969 if (TID->mayStore() || TID->isCall()) {
973 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
976 // See if this instruction does a load. If so, we have to guarantee that the
977 // loaded value doesn't change between the load and the its intended
978 // destination. The check for isInvariantLoad gives the targe the chance to
979 // classify the load as always returning a constant, e.g. a constant pool
981 if (TID->mayLoad() && !isInvariantLoad(AA))
982 // Otherwise, this is a real load. If there is a store between the load and
983 // end of block, or if the load is volatile, we can't move it.
984 return !SawStore && !hasVolatileMemoryRef();
989 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
990 /// instruction which defined the specified register instead of copying it.
991 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
993 AliasAnalysis *AA) const {
994 bool SawStore = false;
995 if (!TII->isTriviallyReMaterializable(this, AA) ||
996 !isSafeToMove(TII, SawStore, AA))
998 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
999 const MachineOperand &MO = getOperand(i);
1002 // FIXME: For now, do not remat any instruction with register operands.
1003 // Later on, we can loosen the restriction is the register operands have
1004 // not been modified between the def and use. Note, this is different from
1005 // MachineSink because the code is no longer in two-address form (at least
1009 else if (!MO.isDead() && MO.getReg() != DstReg)
1015 /// hasVolatileMemoryRef - Return true if this instruction may have a
1016 /// volatile memory reference, or if the information describing the
1017 /// memory reference is not available. Return false if it is known to
1018 /// have no volatile memory references.
1019 bool MachineInstr::hasVolatileMemoryRef() const {
1020 // An instruction known never to access memory won't have a volatile access.
1021 if (!TID->mayStore() &&
1024 !TID->hasUnmodeledSideEffects())
1027 // Otherwise, if the instruction has no memory reference information,
1028 // conservatively assume it wasn't preserved.
1029 if (memoperands_empty())
1032 // Check the memory reference information for volatile references.
1033 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1034 if ((*I)->isVolatile())
1040 /// isInvariantLoad - Return true if this instruction is loading from a
1041 /// location whose value is invariant across the function. For example,
1042 /// loading a value from the constant pool or from from the argument area
1043 /// of a function if it does not change. This should only return true of
1044 /// *all* loads the instruction does are invariant (if it does multiple loads).
1045 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1046 // If the instruction doesn't load at all, it isn't an invariant load.
1047 if (!TID->mayLoad())
1050 // If the instruction has lost its memoperands, conservatively assume that
1051 // it may not be an invariant load.
1052 if (memoperands_empty())
1055 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1057 for (mmo_iterator I = memoperands_begin(),
1058 E = memoperands_end(); I != E; ++I) {
1059 if ((*I)->isVolatile()) return false;
1060 if ((*I)->isStore()) return false;
1062 if (const Value *V = (*I)->getValue()) {
1063 // A load from a constant PseudoSourceValue is invariant.
1064 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1065 if (PSV->isConstant(MFI))
1067 // If we have an AliasAnalysis, ask it whether the memory is constant.
1068 if (AA && AA->pointsToConstantMemory(V))
1072 // Otherwise assume conservatively.
1076 // Everything checks out.
1080 /// isConstantValuePHI - If the specified instruction is a PHI that always
1081 /// merges together the same virtual register, return the register, otherwise
1083 unsigned MachineInstr::isConstantValuePHI() const {
1084 if (getOpcode() != TargetInstrInfo::PHI)
1086 assert(getNumOperands() >= 3 &&
1087 "It's illegal to have a PHI without source operands");
1089 unsigned Reg = getOperand(1).getReg();
1090 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1091 if (getOperand(i).getReg() != Reg)
1096 void MachineInstr::dump() const {
1097 errs() << " " << *this;
1100 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1101 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1102 const MachineFunction *MF = 0;
1103 if (const MachineBasicBlock *MBB = getParent()) {
1104 MF = MBB->getParent();
1106 TM = &MF->getTarget();
1109 // Print explicitly defined operands on the left of an assignment syntax.
1110 unsigned StartOp = 0, e = getNumOperands();
1111 for (; StartOp < e && getOperand(StartOp).isReg() &&
1112 getOperand(StartOp).isDef() &&
1113 !getOperand(StartOp).isImplicit();
1115 if (StartOp != 0) OS << ", ";
1116 getOperand(StartOp).print(OS, TM);
1122 // Print the opcode name.
1123 OS << getDesc().getName();
1125 // Print the rest of the operands.
1126 bool OmittedAnyCallClobbers = false;
1127 bool FirstOp = true;
1128 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1129 const MachineOperand &MO = getOperand(i);
1131 // Omit call-clobbered registers which aren't used anywhere. This makes
1132 // call instructions much less noisy on targets where calls clobber lots
1133 // of registers. Don't rely on MO.isDead() because we may be called before
1134 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1135 if (MF && getDesc().isCall() &&
1136 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1137 unsigned Reg = MO.getReg();
1138 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1139 const MachineRegisterInfo &MRI = MF->getRegInfo();
1140 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1141 bool HasAliasLive = false;
1142 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1143 unsigned AliasReg = *Alias; ++Alias)
1144 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1145 HasAliasLive = true;
1148 if (!HasAliasLive) {
1149 OmittedAnyCallClobbers = true;
1156 if (FirstOp) FirstOp = false; else OS << ",";
1161 // Briefly indicate whether any call clobbers were omitted.
1162 if (OmittedAnyCallClobbers) {
1163 if (!FirstOp) OS << ",";
1167 bool HaveSemi = false;
1168 if (!memoperands_empty()) {
1169 if (!HaveSemi) OS << ";"; HaveSemi = true;
1172 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1180 if (!debugLoc.isUnknown() && MF) {
1181 if (!HaveSemi) OS << ";";
1183 // TODO: print InlinedAtLoc information
1185 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1186 DIScope Scope(DLT.Scope);
1188 // Omit the directory, since it's usually long and uninteresting.
1189 if (!Scope.isNull())
1190 OS << Scope.getFilename();
1193 OS << ':' << DLT.Line;
1195 OS << ':' << DLT.Col;
1201 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1202 const TargetRegisterInfo *RegInfo,
1203 bool AddIfNotFound) {
1204 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1205 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1207 SmallVector<unsigned,4> DeadOps;
1208 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1209 MachineOperand &MO = getOperand(i);
1210 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1212 unsigned Reg = MO.getReg();
1216 if (Reg == IncomingReg) {
1219 // The register is already marked kill.
1221 if (isPhysReg && isRegTiedToDefOperand(i))
1222 // Two-address uses of physregs must not be marked kill.
1227 } else if (hasAliases && MO.isKill() &&
1228 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1229 // A super-register kill already exists.
1230 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1232 if (RegInfo->isSubRegister(IncomingReg, Reg))
1233 DeadOps.push_back(i);
1237 // Trim unneeded kill operands.
1238 while (!DeadOps.empty()) {
1239 unsigned OpIdx = DeadOps.back();
1240 if (getOperand(OpIdx).isImplicit())
1241 RemoveOperand(OpIdx);
1243 getOperand(OpIdx).setIsKill(false);
1247 // If not found, this means an alias of one of the operands is killed. Add a
1248 // new implicit operand if required.
1249 if (!Found && AddIfNotFound) {
1250 addOperand(MachineOperand::CreateReg(IncomingReg,
1259 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1260 const TargetRegisterInfo *RegInfo,
1261 bool AddIfNotFound) {
1262 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1263 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1265 SmallVector<unsigned,4> DeadOps;
1266 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1267 MachineOperand &MO = getOperand(i);
1268 if (!MO.isReg() || !MO.isDef())
1270 unsigned Reg = MO.getReg();
1274 if (Reg == IncomingReg) {
1277 // The register is already marked dead.
1282 } else if (hasAliases && MO.isDead() &&
1283 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1284 // There exists a super-register that's marked dead.
1285 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1287 if (RegInfo->getSubRegisters(IncomingReg) &&
1288 RegInfo->getSuperRegisters(Reg) &&
1289 RegInfo->isSubRegister(IncomingReg, Reg))
1290 DeadOps.push_back(i);
1294 // Trim unneeded dead operands.
1295 while (!DeadOps.empty()) {
1296 unsigned OpIdx = DeadOps.back();
1297 if (getOperand(OpIdx).isImplicit())
1298 RemoveOperand(OpIdx);
1300 getOperand(OpIdx).setIsDead(false);
1304 // If not found, this means an alias of one of the operands is dead. Add a
1305 // new implicit operand if required.
1306 if (Found || !AddIfNotFound)
1309 addOperand(MachineOperand::CreateReg(IncomingReg,