1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/PostOrderIterator.h"
53 #include "llvm/ADT/Statistic.h"
57 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
58 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
59 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
60 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
63 STATISTIC(NumBBWithOutOfOrderLineInfo,
64 "Number of blocks with out of order line number info");
65 STATISTIC(NumMBBWithOutOfOrderLineInfo,
66 "Number of machine blocks with out of order line number info");
70 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
71 cl::desc("Enable verbose messages in the \"fast\" "
72 "instruction selector"));
74 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
75 cl::desc("Enable abort calls when \"fast\" instruction fails"));
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::Latency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::RegPressure)
150 return createBURRListDAGScheduler(IS, OptLevel);
151 if (TLI.getSchedulingPreference() == Sched::Hybrid)
152 return createHybridListDAGScheduler(IS, OptLevel);
153 assert(TLI.getSchedulingPreference() == Sched::ILP &&
154 "Unknown sched type!");
155 return createILPListDAGScheduler(IS, OptLevel);
159 // EmitInstrWithCustomInserter - This method should be implemented by targets
160 // that mark instructions with the 'usesCustomInserter' flag. These
161 // instructions are special in various ways, which require special support to
162 // insert. The specified MachineInstr is created but not inserted into any
163 // basic blocks, and this method is called to expand it into a sequence of
164 // instructions, potentially also creating new basic blocks and control flow.
165 // When new basic blocks are inserted and the edges from MBB to its successors
166 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
169 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB) const {
172 dbgs() << "If a target marks an instruction with "
173 "'usesCustomInserter', it must implement "
174 "TargetLowering::EmitInstrWithCustomInserter!";
180 //===----------------------------------------------------------------------===//
181 // SelectionDAGISel code
182 //===----------------------------------------------------------------------===//
184 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
185 CodeGenOpt::Level OL) :
186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
187 FuncInfo(new FunctionLoweringInfo(TLI)),
188 CurDAG(new SelectionDAG(tm)),
189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
197 SelectionDAGISel::~SelectionDAGISel() {
203 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
204 AU.addRequired<AliasAnalysis>();
205 AU.addPreserved<AliasAnalysis>();
206 AU.addRequired<GCModuleInfo>();
207 AU.addPreserved<GCModuleInfo>();
208 MachineFunctionPass::getAnalysisUsage(AU);
211 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
212 /// other function that gcc recognizes as "returning twice". This is used to
213 /// limit code-gen optimizations on the machine function.
215 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
216 static bool FunctionCallsSetJmp(const Function *F) {
217 const Module *M = F->getParent();
218 static const char *ReturnsTwiceFns[] = {
228 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
230 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
231 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
232 if (!Callee->use_empty())
233 for (Value::const_use_iterator
234 I = Callee->use_begin(), E = Callee->use_end();
236 if (const CallInst *CI = dyn_cast<CallInst>(*I))
237 if (CI->getParent()->getParent() == F)
242 #undef NUM_RETURNS_TWICE_FNS
245 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
246 /// may trap on it. In this case we have to split the edge so that the path
247 /// through the predecessor block that doesn't go to the phi block doesn't
248 /// execute the possibly trapping instruction.
250 /// This is required for correctness, so it must be done at -O0.
252 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
253 // Loop for blocks with phi nodes.
254 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
255 PHINode *PN = dyn_cast<PHINode>(BB->begin());
256 if (PN == 0) continue;
259 // For each block with a PHI node, check to see if any of the input values
260 // are potentially trapping constant expressions. Constant expressions are
261 // the only potentially trapping value that can occur as the argument to a
263 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
264 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
265 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
266 if (CE == 0 || !CE->canTrap()) continue;
268 // The only case we have to worry about is when the edge is critical.
269 // Since this block has a PHI Node, we assume it has multiple input
270 // edges: check to see if the pred has multiple successors.
271 BasicBlock *Pred = PN->getIncomingBlock(i);
272 if (Pred->getTerminator()->getNumSuccessors() == 1)
275 // Okay, we have to split this edge.
276 SplitCriticalEdge(Pred->getTerminator(),
277 GetSuccessorNumber(Pred, BB), SDISel, true);
283 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
284 // Do some sanity-checking on the command-line options.
285 assert((!EnableFastISelVerbose || EnableFastISel) &&
286 "-fast-isel-verbose requires -fast-isel");
287 assert((!EnableFastISelAbort || EnableFastISel) &&
288 "-fast-isel-abort requires -fast-isel");
290 const Function &Fn = *mf.getFunction();
291 const TargetInstrInfo &TII = *TM.getInstrInfo();
292 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
295 RegInfo = &MF->getRegInfo();
296 AA = &getAnalysis<AliasAnalysis>();
297 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
299 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
301 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
304 FuncInfo->set(Fn, *MF);
307 SelectAllBasicBlocks(Fn);
309 // If the first basic block in the function has live ins that need to be
310 // copied into vregs, emit the copies into the top of the block before
311 // emitting the code for the block.
312 MachineBasicBlock *EntryMBB = MF->begin();
313 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
315 DenseMap<unsigned, unsigned> LiveInMap;
316 if (!FuncInfo->ArgDbgValues.empty())
317 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
318 E = RegInfo->livein_end(); LI != E; ++LI)
320 LiveInMap.insert(std::make_pair(LI->first, LI->second));
322 // Insert DBG_VALUE instructions for function arguments to the entry block.
323 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
324 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
325 unsigned Reg = MI->getOperand(0).getReg();
326 if (TargetRegisterInfo::isPhysicalRegister(Reg))
327 EntryMBB->insert(EntryMBB->begin(), MI);
329 MachineInstr *Def = RegInfo->getVRegDef(Reg);
330 MachineBasicBlock::iterator InsertPos = Def;
331 // FIXME: VR def may not be in entry block.
332 Def->getParent()->insert(llvm::next(InsertPos), MI);
335 // If Reg is live-in then update debug info to track its copy in a vreg.
336 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
337 if (LDI != LiveInMap.end()) {
338 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
339 MachineBasicBlock::iterator InsertPos = Def;
340 const MDNode *Variable =
341 MI->getOperand(MI->getNumOperands()-1).getMetadata();
342 unsigned Offset = MI->getOperand(1).getImm();
343 // Def is never a terminator here, so it is ok to increment InsertPos.
344 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
345 TII.get(TargetOpcode::DBG_VALUE))
346 .addReg(LDI->second, RegState::Debug)
347 .addImm(Offset).addMetadata(Variable);
349 // If this vreg is directly copied into an exported register then
350 // that COPY instructions also need DBG_VALUE, if it is the only
351 // user of LDI->second.
352 MachineInstr *CopyUseMI = NULL;
353 for (MachineRegisterInfo::use_iterator
354 UI = RegInfo->use_begin(LDI->second);
355 MachineInstr *UseMI = UI.skipInstruction();) {
356 if (UseMI->isDebugValue()) continue;
357 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
358 CopyUseMI = UseMI; continue;
360 // Otherwise this is another use or second copy use.
361 CopyUseMI = NULL; break;
364 MachineInstr *NewMI =
365 BuildMI(*MF, CopyUseMI->getDebugLoc(),
366 TII.get(TargetOpcode::DBG_VALUE))
367 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
368 .addImm(Offset).addMetadata(Variable);
369 EntryMBB->insertAfter(CopyUseMI, NewMI);
374 // Determine if there are any calls in this machine function.
375 MachineFrameInfo *MFI = MF->getFrameInfo();
376 if (!MFI->hasCalls()) {
377 for (MachineFunction::const_iterator
378 I = MF->begin(), E = MF->end(); I != E; ++I) {
379 const MachineBasicBlock *MBB = I;
380 for (MachineBasicBlock::const_iterator
381 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
382 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
384 if ((TID.isCall() && !TID.isReturn()) ||
385 II->isStackAligningInlineAsm()) {
386 MFI->setHasCalls(true);
394 // Determine if there is a call to setjmp in the machine function.
395 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
397 // Replace forward-declared registers with the registers containing
398 // the desired value.
399 MachineRegisterInfo &MRI = MF->getRegInfo();
400 for (DenseMap<unsigned, unsigned>::iterator
401 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
403 unsigned From = I->first;
404 unsigned To = I->second;
405 // If To is also scheduled to be replaced, find what its ultimate
408 DenseMap<unsigned, unsigned>::iterator J =
409 FuncInfo->RegFixups.find(To);
414 MRI.replaceRegWith(From, To);
417 // Release function-specific state. SDB and CurDAG are already cleared
424 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
425 BasicBlock::const_iterator End,
427 // Lower all of the non-terminator instructions. If a call is emitted
428 // as a tail call, cease emitting nodes for this block. Terminators
429 // are handled below.
430 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
433 // Make sure the root of the DAG is up-to-date.
434 CurDAG->setRoot(SDB->getControlRoot());
435 HadTailCall = SDB->HasTailCall;
438 // Final step, emit the lowered DAG as machine code.
442 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
443 SmallPtrSet<SDNode*, 128> VisitedNodes;
444 SmallVector<SDNode*, 128> Worklist;
446 Worklist.push_back(CurDAG->getRoot().getNode());
453 SDNode *N = Worklist.pop_back_val();
455 // If we've already seen this node, ignore it.
456 if (!VisitedNodes.insert(N))
459 // Otherwise, add all chain operands to the worklist.
460 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
461 if (N->getOperand(i).getValueType() == MVT::Other)
462 Worklist.push_back(N->getOperand(i).getNode());
464 // If this is a CopyToReg with a vreg dest, process it.
465 if (N->getOpcode() != ISD::CopyToReg)
468 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
469 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
472 // Ignore non-scalar or non-integer values.
473 SDValue Src = N->getOperand(2);
474 EVT SrcVT = Src.getValueType();
475 if (!SrcVT.isInteger() || SrcVT.isVector())
478 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
479 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
480 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
481 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
482 } while (!Worklist.empty());
485 void SelectionDAGISel::CodeGenAndEmitDAG() {
486 std::string GroupName;
487 if (TimePassesIsEnabled)
488 GroupName = "Instruction Selection and Scheduling";
489 std::string BlockName;
490 int BlockNumber = -1;
492 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
493 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
497 BlockNumber = FuncInfo->MBB->getNumber();
498 BlockName = MF->getFunction()->getNameStr() + ":" +
499 FuncInfo->MBB->getBasicBlock()->getNameStr();
501 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
502 << " '" << BlockName << "'\n"; CurDAG->dump());
504 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
506 // Run the DAG combiner in pre-legalize mode.
508 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
509 CurDAG->Combine(Unrestricted, *AA, OptLevel);
512 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
513 << " '" << BlockName << "'\n"; CurDAG->dump());
515 // Second step, hack on the DAG until it only uses operations and types that
516 // the target supports.
517 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
522 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
523 Changed = CurDAG->LegalizeTypes();
526 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
527 << " '" << BlockName << "'\n"; CurDAG->dump());
530 if (ViewDAGCombineLT)
531 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
533 // Run the DAG combiner in post-type-legalize mode.
535 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
536 TimePassesIsEnabled);
537 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
540 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
541 << " '" << BlockName << "'\n"; CurDAG->dump());
545 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
546 Changed = CurDAG->LegalizeVectors();
551 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
552 CurDAG->LegalizeTypes();
555 if (ViewDAGCombineLT)
556 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
558 // Run the DAG combiner in post-type-legalize mode.
560 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
561 TimePassesIsEnabled);
562 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
565 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
566 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
569 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
572 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
573 CurDAG->Legalize(OptLevel);
576 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
577 << " '" << BlockName << "'\n"; CurDAG->dump());
579 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
581 // Run the DAG combiner in post-legalize mode.
583 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
584 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
587 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
588 << " '" << BlockName << "'\n"; CurDAG->dump());
590 if (OptLevel != CodeGenOpt::None)
591 ComputeLiveOutVRegInfo();
593 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
595 // Third, instruction select all of the operations to machine code, adding the
596 // code to the MachineBasicBlock.
598 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
599 DoInstructionSelection();
602 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
603 << " '" << BlockName << "'\n"; CurDAG->dump());
605 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
607 // Schedule machine code.
608 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
610 NamedRegionTimer T("Instruction Scheduling", GroupName,
611 TimePassesIsEnabled);
612 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
615 if (ViewSUnitDAGs) Scheduler->viewGraph();
617 // Emit machine code to BB. This can change 'BB' to the last block being
619 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
621 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
623 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
624 FuncInfo->InsertPt = Scheduler->InsertPos;
627 // If the block was split, make sure we update any references that are used to
628 // update PHI nodes later on.
629 if (FirstMBB != LastMBB)
630 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
632 // Free the scheduler state.
634 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
635 TimePassesIsEnabled);
639 // Free the SelectionDAG state, now that we're finished with it.
643 void SelectionDAGISel::DoInstructionSelection() {
644 DEBUG(errs() << "===== Instruction selection begins: BB#"
645 << FuncInfo->MBB->getNumber()
646 << " '" << FuncInfo->MBB->getName() << "'\n");
650 // Select target instructions for the DAG.
652 // Number all nodes with a topological order and set DAGSize.
653 DAGSize = CurDAG->AssignTopologicalOrder();
655 // Create a dummy node (which is not added to allnodes), that adds
656 // a reference to the root node, preventing it from being deleted,
657 // and tracking any changes of the root.
658 HandleSDNode Dummy(CurDAG->getRoot());
659 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
662 // The AllNodes list is now topological-sorted. Visit the
663 // nodes by starting at the end of the list (the root of the
664 // graph) and preceding back toward the beginning (the entry
666 while (ISelPosition != CurDAG->allnodes_begin()) {
667 SDNode *Node = --ISelPosition;
668 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
669 // but there are currently some corner cases that it misses. Also, this
670 // makes it theoretically possible to disable the DAGCombiner.
671 if (Node->use_empty())
674 SDNode *ResNode = Select(Node);
676 // FIXME: This is pretty gross. 'Select' should be changed to not return
677 // anything at all and this code should be nuked with a tactical strike.
679 // If node should not be replaced, continue with the next one.
680 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
684 ReplaceUses(Node, ResNode);
686 // If after the replacement this node is not used any more,
687 // remove this dead node.
688 if (Node->use_empty()) { // Don't delete EntryToken, etc.
689 ISelUpdater ISU(ISelPosition);
690 CurDAG->RemoveDeadNode(Node, &ISU);
694 CurDAG->setRoot(Dummy.getValue());
697 DEBUG(errs() << "===== Instruction selection ends:\n");
699 PostprocessISelDAG();
702 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
703 /// do other setup for EH landing-pad blocks.
704 void SelectionDAGISel::PrepareEHLandingPad() {
705 // Add a label to mark the beginning of the landing pad. Deletion of the
706 // landing pad can thus be detected via the MachineModuleInfo.
707 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
709 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
710 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
713 // Mark exception register as live in.
714 unsigned Reg = TLI.getExceptionAddressRegister();
715 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
717 // Mark exception selector register as live in.
718 Reg = TLI.getExceptionSelectorRegister();
719 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
721 // FIXME: Hack around an exception handling flaw (PR1508): the personality
722 // function and list of typeids logically belong to the invoke (or, if you
723 // like, the basic block containing the invoke), and need to be associated
724 // with it in the dwarf exception handling tables. Currently however the
725 // information is provided by an intrinsic (eh.selector) that can be moved
726 // to unexpected places by the optimizers: if the unwind edge is critical,
727 // then breaking it can result in the intrinsics being in the successor of
728 // the landing pad, not the landing pad itself. This results
729 // in exceptions not being caught because no typeids are associated with
730 // the invoke. This may not be the only way things can go wrong, but it
731 // is the only way we try to work around for the moment.
732 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
733 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
735 if (Br && Br->isUnconditional()) { // Critical edge?
736 BasicBlock::const_iterator I, E;
737 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
738 if (isa<EHSelectorInst>(I))
742 // No catch info found - try to extract some from the successor.
743 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
749 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
750 /// load into the specified FoldInst. Note that we could have a sequence where
751 /// multiple LLVM IR instructions are folded into the same machineinstr. For
752 /// example we could have:
753 /// A: x = load i32 *P
754 /// B: y = icmp A, 42
757 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
758 /// any other folded instructions) because it is between A and C.
760 /// If we succeed in folding the load into the operation, return true.
762 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
763 const Instruction *FoldInst,
765 // We know that the load has a single use, but don't know what it is. If it
766 // isn't one of the folded instructions, then we can't succeed here. Handle
767 // this by scanning the single-use users of the load until we get to FoldInst.
768 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
770 const Instruction *TheUser = LI->use_back();
771 while (TheUser != FoldInst && // Scan up until we find FoldInst.
772 // Stay in the right block.
773 TheUser->getParent() == FoldInst->getParent() &&
774 --MaxUsers) { // Don't scan too far.
775 // If there are multiple or no uses of this instruction, then bail out.
776 if (!TheUser->hasOneUse())
779 TheUser = TheUser->use_back();
782 // Don't try to fold volatile loads. Target has to deal with alignment
784 if (LI->isVolatile()) return false;
786 // Figure out which vreg this is going into. If there is no assigned vreg yet
787 // then there actually was no reference to it. Perhaps the load is referenced
788 // by a dead instruction.
789 unsigned LoadReg = FastIS->getRegForValue(LI);
793 // Check to see what the uses of this vreg are. If it has no uses, or more
794 // than one use (at the machine instr level) then we can't fold it.
795 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
796 if (RI == RegInfo->reg_end())
799 // See if there is exactly one use of the vreg. If there are multiple uses,
800 // then the instruction got lowered to multiple machine instructions or the
801 // use of the loaded value ended up being multiple operands of the result, in
802 // either case, we can't fold this.
803 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
804 if (PostRI != RegInfo->reg_end())
807 assert(RI.getOperand().isUse() &&
808 "The only use of the vreg must be a use, we haven't emitted the def!");
810 MachineInstr *User = &*RI;
812 // Set the insertion point properly. Folding the load can cause generation of
813 // other random instructions (like sign extends) for addressing modes, make
814 // sure they get inserted in a logical place before the new instruction.
815 FuncInfo->InsertPt = User;
816 FuncInfo->MBB = User->getParent();
818 // Ask the target to try folding the load.
819 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
823 /// CheckLineNumbers - Check if basic block instructions follow source order
825 static void CheckLineNumbers(const BasicBlock *BB) {
828 for (BasicBlock::const_iterator BI = BB->begin(),
829 BE = BB->end(); BI != BE; ++BI) {
830 const DebugLoc DL = BI->getDebugLoc();
831 if (DL.isUnknown()) continue;
832 unsigned L = DL.getLine();
833 unsigned C = DL.getCol();
834 if (L < Line || (L == Line && C < Col)) {
835 ++NumBBWithOutOfOrderLineInfo;
843 /// CheckLineNumbers - Check if machine basic block instructions follow source
845 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
848 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
849 MBE = MBB->end(); MBI != MBE; ++MBI) {
850 const DebugLoc DL = MBI->getDebugLoc();
851 if (DL.isUnknown()) continue;
852 unsigned L = DL.getLine();
853 unsigned C = DL.getCol();
854 if (L < Line || (L == Line && C < Col)) {
855 ++NumMBBWithOutOfOrderLineInfo;
864 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
865 /// side-effect free and is either dead or folded into a generated instruction.
866 /// Return false if it needs to be emitted.
867 static bool isFoldedOrDeadInstruction(const Instruction *I,
868 FunctionLoweringInfo *FuncInfo) {
869 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
870 !isa<TerminatorInst>(I) && // Terminators aren't folded.
871 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
872 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
875 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
876 // Initialize the Fast-ISel state, if needed.
877 FastISel *FastIS = 0;
879 FastIS = TLI.createFastISel(*FuncInfo);
881 // Iterate over all basic blocks in the function.
882 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
883 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
884 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
885 const BasicBlock *LLVMBB = *I;
887 CheckLineNumbers(LLVMBB);
890 if (OptLevel != CodeGenOpt::None) {
891 bool AllPredsVisited = true;
892 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
894 if (!FuncInfo->VisitedBBs.count(*PI)) {
895 AllPredsVisited = false;
900 if (AllPredsVisited) {
901 for (BasicBlock::const_iterator I = LLVMBB->begin();
902 isa<PHINode>(I); ++I)
903 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
905 for (BasicBlock::const_iterator I = LLVMBB->begin();
906 isa<PHINode>(I); ++I)
907 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
910 FuncInfo->VisitedBBs.insert(LLVMBB);
913 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
914 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
916 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
917 BasicBlock::const_iterator const End = LLVMBB->end();
918 BasicBlock::const_iterator BI = End;
920 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
922 // Setup an EH landing-pad block.
923 if (FuncInfo->MBB->isLandingPad())
924 PrepareEHLandingPad();
926 // Lower any arguments needed in this block if this is the entry block.
927 if (LLVMBB == &Fn.getEntryBlock())
928 LowerArguments(LLVMBB);
930 // Before doing SelectionDAG ISel, see if FastISel has been requested.
932 FastIS->startNewBlock();
934 // Emit code for any incoming arguments. This must happen before
935 // beginning FastISel on the entry block.
936 if (LLVMBB == &Fn.getEntryBlock()) {
937 CurDAG->setRoot(SDB->getControlRoot());
941 // If we inserted any instructions at the beginning, make a note of
942 // where they are, so we can be sure to emit subsequent instructions
944 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
945 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
947 FastIS->setLastLocalValue(0);
950 // Do FastISel on as many instructions as possible.
951 for (; BI != Begin; --BI) {
952 const Instruction *Inst = llvm::prior(BI);
954 // If we no longer require this instruction, skip it.
955 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
958 // Bottom-up: reset the insert pos at the top, after any local-value
960 FastIS->recomputeInsertPt();
962 // Try to select the instruction with FastISel.
963 if (FastIS->SelectInstruction(Inst)) {
964 // If fast isel succeeded, skip over all the folded instructions, and
965 // then see if there is a load right before the selected instructions.
966 // Try to fold the load if so.
967 const Instruction *BeforeInst = Inst;
968 while (BeforeInst != Begin) {
969 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
970 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
973 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
974 BeforeInst->hasOneUse() &&
975 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
976 // If we succeeded, don't re-select the load.
977 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
981 // Then handle certain instructions as single-LLVM-Instruction blocks.
982 if (isa<CallInst>(Inst)) {
983 ++NumFastIselFailures;
984 if (EnableFastISelVerbose || EnableFastISelAbort) {
985 dbgs() << "FastISel missed call: ";
989 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
990 unsigned &R = FuncInfo->ValueMap[Inst];
992 R = FuncInfo->CreateRegs(Inst->getType());
995 bool HadTailCall = false;
996 SelectBasicBlock(Inst, BI, HadTailCall);
998 // If the call was emitted as a tail call, we're done with the block.
1007 // Otherwise, give up on FastISel for the rest of the block.
1008 // For now, be a little lenient about non-branch terminators.
1009 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
1010 ++NumFastIselFailures;
1011 if (EnableFastISelVerbose || EnableFastISelAbort) {
1012 dbgs() << "FastISel miss: ";
1015 if (EnableFastISelAbort)
1016 // The "fast" selector couldn't handle something and bailed.
1017 // For the purpose of debugging, just abort.
1018 llvm_unreachable("FastISel didn't select the entire block");
1023 FastIS->recomputeInsertPt();
1029 ++NumFastIselBlocks;
1032 // Run SelectionDAG instruction selection on the remainder of the block
1033 // not handled by FastISel. If FastISel is not run, this is the entire
1036 SelectBasicBlock(Begin, BI, HadTailCall);
1040 FuncInfo->PHINodesToUpdate.clear();
1045 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
1047 CheckLineNumbers(MBI);
1052 SelectionDAGISel::FinishBasicBlock() {
1054 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1055 << FuncInfo->PHINodesToUpdate.size() << "\n";
1056 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1057 dbgs() << "Node " << i << " : ("
1058 << FuncInfo->PHINodesToUpdate[i].first
1059 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1061 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1062 // PHI nodes in successors.
1063 if (SDB->SwitchCases.empty() &&
1064 SDB->JTCases.empty() &&
1065 SDB->BitTestCases.empty()) {
1066 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1067 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1068 assert(PHI->isPHI() &&
1069 "This is not a machine PHI node that we are updating!");
1070 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1073 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1074 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1079 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1080 // Lower header first, if it wasn't already lowered
1081 if (!SDB->BitTestCases[i].Emitted) {
1082 // Set the current basic block to the mbb we wish to insert the code into
1083 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1084 FuncInfo->InsertPt = FuncInfo->MBB->end();
1086 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1087 CurDAG->setRoot(SDB->getRoot());
1089 CodeGenAndEmitDAG();
1092 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1093 // Set the current basic block to the mbb we wish to insert the code into
1094 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1095 FuncInfo->InsertPt = FuncInfo->MBB->end();
1098 SDB->visitBitTestCase(SDB->BitTestCases[i],
1099 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1100 SDB->BitTestCases[i].Reg,
1101 SDB->BitTestCases[i].Cases[j],
1104 SDB->visitBitTestCase(SDB->BitTestCases[i],
1105 SDB->BitTestCases[i].Default,
1106 SDB->BitTestCases[i].Reg,
1107 SDB->BitTestCases[i].Cases[j],
1111 CurDAG->setRoot(SDB->getRoot());
1113 CodeGenAndEmitDAG();
1117 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1119 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1120 MachineBasicBlock *PHIBB = PHI->getParent();
1121 assert(PHI->isPHI() &&
1122 "This is not a machine PHI node that we are updating!");
1123 // This is "default" BB. We have two jumps to it. From "header" BB and
1124 // from last "case" BB.
1125 if (PHIBB == SDB->BitTestCases[i].Default) {
1126 PHI->addOperand(MachineOperand::
1127 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1129 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1130 PHI->addOperand(MachineOperand::
1131 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1133 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1136 // One of "cases" BB.
1137 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1139 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1140 if (cBB->isSuccessor(PHIBB)) {
1141 PHI->addOperand(MachineOperand::
1142 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1144 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1149 SDB->BitTestCases.clear();
1151 // If the JumpTable record is filled in, then we need to emit a jump table.
1152 // Updating the PHI nodes is tricky in this case, since we need to determine
1153 // whether the PHI is a successor of the range check MBB or the jump table MBB
1154 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1155 // Lower header first, if it wasn't already lowered
1156 if (!SDB->JTCases[i].first.Emitted) {
1157 // Set the current basic block to the mbb we wish to insert the code into
1158 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1159 FuncInfo->InsertPt = FuncInfo->MBB->end();
1161 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1163 CurDAG->setRoot(SDB->getRoot());
1165 CodeGenAndEmitDAG();
1168 // Set the current basic block to the mbb we wish to insert the code into
1169 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1170 FuncInfo->InsertPt = FuncInfo->MBB->end();
1172 SDB->visitJumpTable(SDB->JTCases[i].second);
1173 CurDAG->setRoot(SDB->getRoot());
1175 CodeGenAndEmitDAG();
1178 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1180 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1181 MachineBasicBlock *PHIBB = PHI->getParent();
1182 assert(PHI->isPHI() &&
1183 "This is not a machine PHI node that we are updating!");
1184 // "default" BB. We can go there only from header BB.
1185 if (PHIBB == SDB->JTCases[i].second.Default) {
1187 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1190 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1192 // JT BB. Just iterate over successors here
1193 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1195 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1197 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1201 SDB->JTCases.clear();
1203 // If the switch block involved a branch to one of the actual successors, we
1204 // need to update PHI nodes in that block.
1205 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1206 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1207 assert(PHI->isPHI() &&
1208 "This is not a machine PHI node that we are updating!");
1209 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1211 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1212 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1216 // If we generated any switch lowering information, build and codegen any
1217 // additional DAGs necessary.
1218 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1219 // Set the current basic block to the mbb we wish to insert the code into
1220 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1221 FuncInfo->InsertPt = FuncInfo->MBB->end();
1223 // Determine the unique successors.
1224 SmallVector<MachineBasicBlock *, 2> Succs;
1225 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1226 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1227 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1229 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1230 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1231 CurDAG->setRoot(SDB->getRoot());
1233 CodeGenAndEmitDAG();
1235 // Remember the last block, now that any splitting is done, for use in
1236 // populating PHI nodes in successors.
1237 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1239 // Handle any PHI nodes in successors of this chunk, as if we were coming
1240 // from the original BB before switch expansion. Note that PHI nodes can
1241 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1242 // handle them the right number of times.
1243 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1244 FuncInfo->MBB = Succs[i];
1245 FuncInfo->InsertPt = FuncInfo->MBB->end();
1246 // FuncInfo->MBB may have been removed from the CFG if a branch was
1248 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1249 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1250 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1252 // This value for this PHI node is recorded in PHINodesToUpdate.
1253 for (unsigned pn = 0; ; ++pn) {
1254 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1255 "Didn't find PHI entry!");
1256 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1257 Phi->addOperand(MachineOperand::
1258 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1260 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1268 SDB->SwitchCases.clear();
1272 /// Create the scheduler. If a specific scheduler was specified
1273 /// via the SchedulerRegistry, use it, otherwise select the
1274 /// one preferred by the target.
1276 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1277 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1281 RegisterScheduler::setDefault(Ctor);
1284 return Ctor(this, OptLevel);
1287 //===----------------------------------------------------------------------===//
1288 // Helper functions used by the generated instruction selector.
1289 //===----------------------------------------------------------------------===//
1290 // Calls to these methods are generated by tblgen.
1292 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1293 /// the dag combiner simplified the 255, we still want to match. RHS is the
1294 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1295 /// specified in the .td file (e.g. 255).
1296 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1297 int64_t DesiredMaskS) const {
1298 const APInt &ActualMask = RHS->getAPIntValue();
1299 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1301 // If the actual mask exactly matches, success!
1302 if (ActualMask == DesiredMask)
1305 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1306 if (ActualMask.intersects(~DesiredMask))
1309 // Otherwise, the DAG Combiner may have proven that the value coming in is
1310 // either already zero or is not demanded. Check for known zero input bits.
1311 APInt NeededMask = DesiredMask & ~ActualMask;
1312 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1315 // TODO: check to see if missing bits are just not demanded.
1317 // Otherwise, this pattern doesn't match.
1321 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1322 /// the dag combiner simplified the 255, we still want to match. RHS is the
1323 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1324 /// specified in the .td file (e.g. 255).
1325 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1326 int64_t DesiredMaskS) const {
1327 const APInt &ActualMask = RHS->getAPIntValue();
1328 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1330 // If the actual mask exactly matches, success!
1331 if (ActualMask == DesiredMask)
1334 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1335 if (ActualMask.intersects(~DesiredMask))
1338 // Otherwise, the DAG Combiner may have proven that the value coming in is
1339 // either already zero or is not demanded. Check for known zero input bits.
1340 APInt NeededMask = DesiredMask & ~ActualMask;
1342 APInt KnownZero, KnownOne;
1343 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1345 // If all the missing bits in the or are already known to be set, match!
1346 if ((NeededMask & KnownOne) == NeededMask)
1349 // TODO: check to see if missing bits are just not demanded.
1351 // Otherwise, this pattern doesn't match.
1356 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1357 /// by tblgen. Others should not call it.
1358 void SelectionDAGISel::
1359 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1360 std::vector<SDValue> InOps;
1361 std::swap(InOps, Ops);
1363 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1364 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1365 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1366 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1368 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1369 if (InOps[e-1].getValueType() == MVT::Glue)
1370 --e; // Don't process a glue operand if it is here.
1373 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1374 if (!InlineAsm::isMemKind(Flags)) {
1375 // Just skip over this operand, copying the operands verbatim.
1376 Ops.insert(Ops.end(), InOps.begin()+i,
1377 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1378 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1380 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1381 "Memory operand with multiple values?");
1382 // Otherwise, this is a memory operand. Ask the target to select it.
1383 std::vector<SDValue> SelOps;
1384 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1385 report_fatal_error("Could not match memory address. Inline asm"
1388 // Add this to the output node.
1390 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1391 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1392 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1397 // Add the glue input back if present.
1398 if (e != InOps.size())
1399 Ops.push_back(InOps.back());
1402 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1405 static SDNode *findGlueUse(SDNode *N) {
1406 unsigned FlagResNo = N->getNumValues()-1;
1407 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1408 SDUse &Use = I.getUse();
1409 if (Use.getResNo() == FlagResNo)
1410 return Use.getUser();
1415 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1416 /// This function recursively traverses up the operand chain, ignoring
1418 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1419 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1420 bool IgnoreChains) {
1421 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1422 // greater than all of its (recursive) operands. If we scan to a point where
1423 // 'use' is smaller than the node we're scanning for, then we know we will
1426 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1427 // happen because we scan down to newly selected nodes in the case of glue
1429 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1432 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1433 // won't fail if we scan it again.
1434 if (!Visited.insert(Use))
1437 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1438 // Ignore chain uses, they are validated by HandleMergeInputChains.
1439 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1442 SDNode *N = Use->getOperand(i).getNode();
1444 if (Use == ImmedUse || Use == Root)
1445 continue; // We are not looking for immediate use.
1450 // Traverse up the operand chain.
1451 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1457 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1458 /// operand node N of U during instruction selection that starts at Root.
1459 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1460 SDNode *Root) const {
1461 if (OptLevel == CodeGenOpt::None) return false;
1462 return N.hasOneUse();
1465 /// IsLegalToFold - Returns true if the specific operand node N of
1466 /// U can be folded during instruction selection that starts at Root.
1467 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1468 CodeGenOpt::Level OptLevel,
1469 bool IgnoreChains) {
1470 if (OptLevel == CodeGenOpt::None) return false;
1472 // If Root use can somehow reach N through a path that that doesn't contain
1473 // U then folding N would create a cycle. e.g. In the following
1474 // diagram, Root can reach N through X. If N is folded into into Root, then
1475 // X is both a predecessor and a successor of U.
1486 // * indicates nodes to be folded together.
1488 // If Root produces glue, then it gets (even more) interesting. Since it
1489 // will be "glued" together with its glue use in the scheduler, we need to
1490 // check if it might reach N.
1509 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1510 // (call it Fold), then X is a predecessor of GU and a successor of
1511 // Fold. But since Fold and GU are glued together, this will create
1512 // a cycle in the scheduling graph.
1514 // If the node has glue, walk down the graph to the "lowest" node in the
1516 EVT VT = Root->getValueType(Root->getNumValues()-1);
1517 while (VT == MVT::Glue) {
1518 SDNode *GU = findGlueUse(Root);
1522 VT = Root->getValueType(Root->getNumValues()-1);
1524 // If our query node has a glue result with a use, we've walked up it. If
1525 // the user (which has already been selected) has a chain or indirectly uses
1526 // the chain, our WalkChainUsers predicate will not consider it. Because of
1527 // this, we cannot ignore chains in this predicate.
1528 IgnoreChains = false;
1532 SmallPtrSet<SDNode*, 16> Visited;
1533 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1536 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1537 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1538 SelectInlineAsmMemoryOperands(Ops);
1540 std::vector<EVT> VTs;
1541 VTs.push_back(MVT::Other);
1542 VTs.push_back(MVT::Glue);
1543 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1544 VTs, &Ops[0], Ops.size());
1546 return New.getNode();
1549 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1550 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1553 /// GetVBR - decode a vbr encoding whose top bit is set.
1554 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1555 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1556 assert(Val >= 128 && "Not a VBR");
1557 Val &= 127; // Remove first vbr bit.
1562 NextBits = MatcherTable[Idx++];
1563 Val |= (NextBits&127) << Shift;
1565 } while (NextBits & 128);
1571 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1572 /// interior glue and chain results to use the new glue and chain results.
1573 void SelectionDAGISel::
1574 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1575 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1577 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1578 bool isMorphNodeTo) {
1579 SmallVector<SDNode*, 4> NowDeadNodes;
1581 ISelUpdater ISU(ISelPosition);
1583 // Now that all the normal results are replaced, we replace the chain and
1584 // glue results if present.
1585 if (!ChainNodesMatched.empty()) {
1586 assert(InputChain.getNode() != 0 &&
1587 "Matched input chains but didn't produce a chain");
1588 // Loop over all of the nodes we matched that produced a chain result.
1589 // Replace all the chain results with the final chain we ended up with.
1590 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1591 SDNode *ChainNode = ChainNodesMatched[i];
1593 // If this node was already deleted, don't look at it.
1594 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1597 // Don't replace the results of the root node if we're doing a
1599 if (ChainNode == NodeToMatch && isMorphNodeTo)
1602 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1603 if (ChainVal.getValueType() == MVT::Glue)
1604 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1605 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1606 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1608 // If the node became dead and we haven't already seen it, delete it.
1609 if (ChainNode->use_empty() &&
1610 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1611 NowDeadNodes.push_back(ChainNode);
1615 // If the result produces glue, update any glue results in the matched
1616 // pattern with the glue result.
1617 if (InputGlue.getNode() != 0) {
1618 // Handle any interior nodes explicitly marked.
1619 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1620 SDNode *FRN = GlueResultNodesMatched[i];
1622 // If this node was already deleted, don't look at it.
1623 if (FRN->getOpcode() == ISD::DELETED_NODE)
1626 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1627 "Doesn't have a glue result");
1628 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1631 // If the node became dead and we haven't already seen it, delete it.
1632 if (FRN->use_empty() &&
1633 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1634 NowDeadNodes.push_back(FRN);
1638 if (!NowDeadNodes.empty())
1639 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1641 DEBUG(errs() << "ISEL: Match complete!\n");
1647 CR_LeadsToInteriorNode
1650 /// WalkChainUsers - Walk down the users of the specified chained node that is
1651 /// part of the pattern we're matching, looking at all of the users we find.
1652 /// This determines whether something is an interior node, whether we have a
1653 /// non-pattern node in between two pattern nodes (which prevent folding because
1654 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1655 /// between pattern nodes (in which case the TF becomes part of the pattern).
1657 /// The walk we do here is guaranteed to be small because we quickly get down to
1658 /// already selected nodes "below" us.
1660 WalkChainUsers(SDNode *ChainedNode,
1661 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1662 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1663 ChainResult Result = CR_Simple;
1665 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1666 E = ChainedNode->use_end(); UI != E; ++UI) {
1667 // Make sure the use is of the chain, not some other value we produce.
1668 if (UI.getUse().getValueType() != MVT::Other) continue;
1672 // If we see an already-selected machine node, then we've gone beyond the
1673 // pattern that we're selecting down into the already selected chunk of the
1675 if (User->isMachineOpcode() ||
1676 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1679 if (User->getOpcode() == ISD::CopyToReg ||
1680 User->getOpcode() == ISD::CopyFromReg ||
1681 User->getOpcode() == ISD::INLINEASM ||
1682 User->getOpcode() == ISD::EH_LABEL) {
1683 // If their node ID got reset to -1 then they've already been selected.
1684 // Treat them like a MachineOpcode.
1685 if (User->getNodeId() == -1)
1689 // If we have a TokenFactor, we handle it specially.
1690 if (User->getOpcode() != ISD::TokenFactor) {
1691 // If the node isn't a token factor and isn't part of our pattern, then it
1692 // must be a random chained node in between two nodes we're selecting.
1693 // This happens when we have something like:
1698 // Because we structurally match the load/store as a read/modify/write,
1699 // but the call is chained between them. We cannot fold in this case
1700 // because it would induce a cycle in the graph.
1701 if (!std::count(ChainedNodesInPattern.begin(),
1702 ChainedNodesInPattern.end(), User))
1703 return CR_InducesCycle;
1705 // Otherwise we found a node that is part of our pattern. For example in:
1709 // This would happen when we're scanning down from the load and see the
1710 // store as a user. Record that there is a use of ChainedNode that is
1711 // part of the pattern and keep scanning uses.
1712 Result = CR_LeadsToInteriorNode;
1713 InteriorChainedNodes.push_back(User);
1717 // If we found a TokenFactor, there are two cases to consider: first if the
1718 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1719 // uses of the TF are in our pattern) we just want to ignore it. Second,
1720 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1726 // | \ DAG's like cheese
1729 // [TokenFactor] [Op]
1736 // In this case, the TokenFactor becomes part of our match and we rewrite it
1737 // as a new TokenFactor.
1739 // To distinguish these two cases, do a recursive walk down the uses.
1740 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1742 // If the uses of the TokenFactor are just already-selected nodes, ignore
1743 // it, it is "below" our pattern.
1745 case CR_InducesCycle:
1746 // If the uses of the TokenFactor lead to nodes that are not part of our
1747 // pattern that are not selected, folding would turn this into a cycle,
1749 return CR_InducesCycle;
1750 case CR_LeadsToInteriorNode:
1751 break; // Otherwise, keep processing.
1754 // Okay, we know we're in the interesting interior case. The TokenFactor
1755 // is now going to be considered part of the pattern so that we rewrite its
1756 // uses (it may have uses that are not part of the pattern) with the
1757 // ultimate chain result of the generated code. We will also add its chain
1758 // inputs as inputs to the ultimate TokenFactor we create.
1759 Result = CR_LeadsToInteriorNode;
1760 ChainedNodesInPattern.push_back(User);
1761 InteriorChainedNodes.push_back(User);
1768 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1769 /// operation for when the pattern matched at least one node with a chains. The
1770 /// input vector contains a list of all of the chained nodes that we match. We
1771 /// must determine if this is a valid thing to cover (i.e. matching it won't
1772 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1773 /// be used as the input node chain for the generated nodes.
1775 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1776 SelectionDAG *CurDAG) {
1777 // Walk all of the chained nodes we've matched, recursively scanning down the
1778 // users of the chain result. This adds any TokenFactor nodes that are caught
1779 // in between chained nodes to the chained and interior nodes list.
1780 SmallVector<SDNode*, 3> InteriorChainedNodes;
1781 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1782 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1783 InteriorChainedNodes) == CR_InducesCycle)
1784 return SDValue(); // Would induce a cycle.
1787 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1788 // that we are interested in. Form our input TokenFactor node.
1789 SmallVector<SDValue, 3> InputChains;
1790 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1791 // Add the input chain of this node to the InputChains list (which will be
1792 // the operands of the generated TokenFactor) if it's not an interior node.
1793 SDNode *N = ChainNodesMatched[i];
1794 if (N->getOpcode() != ISD::TokenFactor) {
1795 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1798 // Otherwise, add the input chain.
1799 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1800 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1801 InputChains.push_back(InChain);
1805 // If we have a token factor, we want to add all inputs of the token factor
1806 // that are not part of the pattern we're matching.
1807 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1808 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1809 N->getOperand(op).getNode()))
1810 InputChains.push_back(N->getOperand(op));
1815 if (InputChains.size() == 1)
1816 return InputChains[0];
1817 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1818 MVT::Other, &InputChains[0], InputChains.size());
1821 /// MorphNode - Handle morphing a node in place for the selector.
1822 SDNode *SelectionDAGISel::
1823 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1824 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1825 // It is possible we're using MorphNodeTo to replace a node with no
1826 // normal results with one that has a normal result (or we could be
1827 // adding a chain) and the input could have glue and chains as well.
1828 // In this case we need to shift the operands down.
1829 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1830 // than the old isel though.
1831 int OldGlueResultNo = -1, OldChainResultNo = -1;
1833 unsigned NTMNumResults = Node->getNumValues();
1834 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1835 OldGlueResultNo = NTMNumResults-1;
1836 if (NTMNumResults != 1 &&
1837 Node->getValueType(NTMNumResults-2) == MVT::Other)
1838 OldChainResultNo = NTMNumResults-2;
1839 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1840 OldChainResultNo = NTMNumResults-1;
1842 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1843 // that this deletes operands of the old node that become dead.
1844 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1846 // MorphNodeTo can operate in two ways: if an existing node with the
1847 // specified operands exists, it can just return it. Otherwise, it
1848 // updates the node in place to have the requested operands.
1850 // If we updated the node in place, reset the node ID. To the isel,
1851 // this should be just like a newly allocated machine node.
1855 unsigned ResNumResults = Res->getNumValues();
1856 // Move the glue if needed.
1857 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1858 (unsigned)OldGlueResultNo != ResNumResults-1)
1859 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1860 SDValue(Res, ResNumResults-1));
1862 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1865 // Move the chain reference if needed.
1866 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1867 (unsigned)OldChainResultNo != ResNumResults-1)
1868 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1869 SDValue(Res, ResNumResults-1));
1871 // Otherwise, no replacement happened because the node already exists. Replace
1872 // Uses of the old node with the new one.
1874 CurDAG->ReplaceAllUsesWith(Node, Res);
1879 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1880 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1881 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1883 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1884 // Accept if it is exactly the same as a previously recorded node.
1885 unsigned RecNo = MatcherTable[MatcherIndex++];
1886 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1887 return N == RecordedNodes[RecNo].first;
1890 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1891 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1892 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1893 SelectionDAGISel &SDISel) {
1894 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1897 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1898 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1899 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1900 SelectionDAGISel &SDISel, SDNode *N) {
1901 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1904 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1905 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1907 uint16_t Opc = MatcherTable[MatcherIndex++];
1908 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1909 return N->getOpcode() == Opc;
1912 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1913 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1914 SDValue N, const TargetLowering &TLI) {
1915 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1916 if (N.getValueType() == VT) return true;
1918 // Handle the case when VT is iPTR.
1919 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1922 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1923 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1924 SDValue N, const TargetLowering &TLI,
1926 if (ChildNo >= N.getNumOperands())
1927 return false; // Match fails if out of range child #.
1928 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1932 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1933 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1935 return cast<CondCodeSDNode>(N)->get() ==
1936 (ISD::CondCode)MatcherTable[MatcherIndex++];
1939 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1940 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1941 SDValue N, const TargetLowering &TLI) {
1942 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1943 if (cast<VTSDNode>(N)->getVT() == VT)
1946 // Handle the case when VT is iPTR.
1947 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1950 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1951 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1953 int64_t Val = MatcherTable[MatcherIndex++];
1955 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1958 return C != 0 && C->getSExtValue() == Val;
1961 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1962 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1963 SDValue N, SelectionDAGISel &SDISel) {
1964 int64_t Val = MatcherTable[MatcherIndex++];
1966 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1968 if (N->getOpcode() != ISD::AND) return false;
1970 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1971 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1974 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1975 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1976 SDValue N, SelectionDAGISel &SDISel) {
1977 int64_t Val = MatcherTable[MatcherIndex++];
1979 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1981 if (N->getOpcode() != ISD::OR) return false;
1983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1984 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1987 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1988 /// scope, evaluate the current node. If the current predicate is known to
1989 /// fail, set Result=true and return anything. If the current predicate is
1990 /// known to pass, set Result=false and return the MatcherIndex to continue
1991 /// with. If the current predicate is unknown, set Result=false and return the
1992 /// MatcherIndex to continue with.
1993 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1994 unsigned Index, SDValue N,
1995 bool &Result, SelectionDAGISel &SDISel,
1996 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1997 switch (Table[Index++]) {
2000 return Index-1; // Could not evaluate this predicate.
2001 case SelectionDAGISel::OPC_CheckSame:
2002 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2004 case SelectionDAGISel::OPC_CheckPatternPredicate:
2005 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2007 case SelectionDAGISel::OPC_CheckPredicate:
2008 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2010 case SelectionDAGISel::OPC_CheckOpcode:
2011 Result = !::CheckOpcode(Table, Index, N.getNode());
2013 case SelectionDAGISel::OPC_CheckType:
2014 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2016 case SelectionDAGISel::OPC_CheckChild0Type:
2017 case SelectionDAGISel::OPC_CheckChild1Type:
2018 case SelectionDAGISel::OPC_CheckChild2Type:
2019 case SelectionDAGISel::OPC_CheckChild3Type:
2020 case SelectionDAGISel::OPC_CheckChild4Type:
2021 case SelectionDAGISel::OPC_CheckChild5Type:
2022 case SelectionDAGISel::OPC_CheckChild6Type:
2023 case SelectionDAGISel::OPC_CheckChild7Type:
2024 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2025 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2027 case SelectionDAGISel::OPC_CheckCondCode:
2028 Result = !::CheckCondCode(Table, Index, N);
2030 case SelectionDAGISel::OPC_CheckValueType:
2031 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2033 case SelectionDAGISel::OPC_CheckInteger:
2034 Result = !::CheckInteger(Table, Index, N);
2036 case SelectionDAGISel::OPC_CheckAndImm:
2037 Result = !::CheckAndImm(Table, Index, N, SDISel);
2039 case SelectionDAGISel::OPC_CheckOrImm:
2040 Result = !::CheckOrImm(Table, Index, N, SDISel);
2048 /// FailIndex - If this match fails, this is the index to continue with.
2051 /// NodeStack - The node stack when the scope was formed.
2052 SmallVector<SDValue, 4> NodeStack;
2054 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2055 unsigned NumRecordedNodes;
2057 /// NumMatchedMemRefs - The number of matched memref entries.
2058 unsigned NumMatchedMemRefs;
2060 /// InputChain/InputGlue - The current chain/glue
2061 SDValue InputChain, InputGlue;
2063 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2064 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2069 SDNode *SelectionDAGISel::
2070 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2071 unsigned TableSize) {
2072 // FIXME: Should these even be selected? Handle these cases in the caller?
2073 switch (NodeToMatch->getOpcode()) {
2076 case ISD::EntryToken: // These nodes remain the same.
2077 case ISD::BasicBlock:
2079 //case ISD::VALUETYPE:
2080 //case ISD::CONDCODE:
2081 case ISD::HANDLENODE:
2082 case ISD::MDNODE_SDNODE:
2083 case ISD::TargetConstant:
2084 case ISD::TargetConstantFP:
2085 case ISD::TargetConstantPool:
2086 case ISD::TargetFrameIndex:
2087 case ISD::TargetExternalSymbol:
2088 case ISD::TargetBlockAddress:
2089 case ISD::TargetJumpTable:
2090 case ISD::TargetGlobalTLSAddress:
2091 case ISD::TargetGlobalAddress:
2092 case ISD::TokenFactor:
2093 case ISD::CopyFromReg:
2094 case ISD::CopyToReg:
2096 NodeToMatch->setNodeId(-1); // Mark selected.
2098 case ISD::AssertSext:
2099 case ISD::AssertZext:
2100 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2101 NodeToMatch->getOperand(0));
2103 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2104 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2107 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2109 // Set up the node stack with NodeToMatch as the only node on the stack.
2110 SmallVector<SDValue, 8> NodeStack;
2111 SDValue N = SDValue(NodeToMatch, 0);
2112 NodeStack.push_back(N);
2114 // MatchScopes - Scopes used when matching, if a match failure happens, this
2115 // indicates where to continue checking.
2116 SmallVector<MatchScope, 8> MatchScopes;
2118 // RecordedNodes - This is the set of nodes that have been recorded by the
2119 // state machine. The second value is the parent of the node, or null if the
2120 // root is recorded.
2121 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2123 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2125 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2127 // These are the current input chain and glue for use when generating nodes.
2128 // Various Emit operations change these. For example, emitting a copytoreg
2129 // uses and updates these.
2130 SDValue InputChain, InputGlue;
2132 // ChainNodesMatched - If a pattern matches nodes that have input/output
2133 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2134 // which ones they are. The result is captured into this list so that we can
2135 // update the chain results when the pattern is complete.
2136 SmallVector<SDNode*, 3> ChainNodesMatched;
2137 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2139 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2140 NodeToMatch->dump(CurDAG);
2143 // Determine where to start the interpreter. Normally we start at opcode #0,
2144 // but if the state machine starts with an OPC_SwitchOpcode, then we
2145 // accelerate the first lookup (which is guaranteed to be hot) with the
2146 // OpcodeOffset table.
2147 unsigned MatcherIndex = 0;
2149 if (!OpcodeOffset.empty()) {
2150 // Already computed the OpcodeOffset table, just index into it.
2151 if (N.getOpcode() < OpcodeOffset.size())
2152 MatcherIndex = OpcodeOffset[N.getOpcode()];
2153 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2155 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2156 // Otherwise, the table isn't computed, but the state machine does start
2157 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2158 // is the first time we're selecting an instruction.
2161 // Get the size of this case.
2162 unsigned CaseSize = MatcherTable[Idx++];
2164 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2165 if (CaseSize == 0) break;
2167 // Get the opcode, add the index to the table.
2168 uint16_t Opc = MatcherTable[Idx++];
2169 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2170 if (Opc >= OpcodeOffset.size())
2171 OpcodeOffset.resize((Opc+1)*2);
2172 OpcodeOffset[Opc] = Idx;
2176 // Okay, do the lookup for the first opcode.
2177 if (N.getOpcode() < OpcodeOffset.size())
2178 MatcherIndex = OpcodeOffset[N.getOpcode()];
2182 assert(MatcherIndex < TableSize && "Invalid index");
2184 unsigned CurrentOpcodeIndex = MatcherIndex;
2186 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2189 // Okay, the semantics of this operation are that we should push a scope
2190 // then evaluate the first child. However, pushing a scope only to have
2191 // the first check fail (which then pops it) is inefficient. If we can
2192 // determine immediately that the first check (or first several) will
2193 // immediately fail, don't even bother pushing a scope for them.
2197 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2198 if (NumToSkip & 128)
2199 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2200 // Found the end of the scope with no match.
2201 if (NumToSkip == 0) {
2206 FailIndex = MatcherIndex+NumToSkip;
2208 unsigned MatcherIndexOfPredicate = MatcherIndex;
2209 (void)MatcherIndexOfPredicate; // silence warning.
2211 // If we can't evaluate this predicate without pushing a scope (e.g. if
2212 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2213 // push the scope and evaluate the full predicate chain.
2215 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2216 Result, *this, RecordedNodes);
2220 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2221 << "index " << MatcherIndexOfPredicate
2222 << ", continuing at " << FailIndex << "\n");
2223 ++NumDAGIselRetries;
2225 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2226 // move to the next case.
2227 MatcherIndex = FailIndex;
2230 // If the whole scope failed to match, bail.
2231 if (FailIndex == 0) break;
2233 // Push a MatchScope which indicates where to go if the first child fails
2235 MatchScope NewEntry;
2236 NewEntry.FailIndex = FailIndex;
2237 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2238 NewEntry.NumRecordedNodes = RecordedNodes.size();
2239 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2240 NewEntry.InputChain = InputChain;
2241 NewEntry.InputGlue = InputGlue;
2242 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2243 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2244 MatchScopes.push_back(NewEntry);
2247 case OPC_RecordNode: {
2248 // Remember this node, it may end up being an operand in the pattern.
2250 if (NodeStack.size() > 1)
2251 Parent = NodeStack[NodeStack.size()-2].getNode();
2252 RecordedNodes.push_back(std::make_pair(N, Parent));
2256 case OPC_RecordChild0: case OPC_RecordChild1:
2257 case OPC_RecordChild2: case OPC_RecordChild3:
2258 case OPC_RecordChild4: case OPC_RecordChild5:
2259 case OPC_RecordChild6: case OPC_RecordChild7: {
2260 unsigned ChildNo = Opcode-OPC_RecordChild0;
2261 if (ChildNo >= N.getNumOperands())
2262 break; // Match fails if out of range child #.
2264 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2268 case OPC_RecordMemRef:
2269 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2272 case OPC_CaptureGlueInput:
2273 // If the current node has an input glue, capture it in InputGlue.
2274 if (N->getNumOperands() != 0 &&
2275 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2276 InputGlue = N->getOperand(N->getNumOperands()-1);
2279 case OPC_MoveChild: {
2280 unsigned ChildNo = MatcherTable[MatcherIndex++];
2281 if (ChildNo >= N.getNumOperands())
2282 break; // Match fails if out of range child #.
2283 N = N.getOperand(ChildNo);
2284 NodeStack.push_back(N);
2288 case OPC_MoveParent:
2289 // Pop the current node off the NodeStack.
2290 NodeStack.pop_back();
2291 assert(!NodeStack.empty() && "Node stack imbalance!");
2292 N = NodeStack.back();
2296 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2298 case OPC_CheckPatternPredicate:
2299 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2301 case OPC_CheckPredicate:
2302 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2306 case OPC_CheckComplexPat: {
2307 unsigned CPNum = MatcherTable[MatcherIndex++];
2308 unsigned RecNo = MatcherTable[MatcherIndex++];
2309 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2310 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2311 RecordedNodes[RecNo].first, CPNum,
2316 case OPC_CheckOpcode:
2317 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2321 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2324 case OPC_SwitchOpcode: {
2325 unsigned CurNodeOpcode = N.getOpcode();
2326 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2329 // Get the size of this case.
2330 CaseSize = MatcherTable[MatcherIndex++];
2332 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2333 if (CaseSize == 0) break;
2335 uint16_t Opc = MatcherTable[MatcherIndex++];
2336 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2338 // If the opcode matches, then we will execute this case.
2339 if (CurNodeOpcode == Opc)
2342 // Otherwise, skip over this case.
2343 MatcherIndex += CaseSize;
2346 // If no cases matched, bail out.
2347 if (CaseSize == 0) break;
2349 // Otherwise, execute the case we found.
2350 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2351 << " to " << MatcherIndex << "\n");
2355 case OPC_SwitchType: {
2356 MVT CurNodeVT = N.getValueType().getSimpleVT();
2357 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2360 // Get the size of this case.
2361 CaseSize = MatcherTable[MatcherIndex++];
2363 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2364 if (CaseSize == 0) break;
2366 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2367 if (CaseVT == MVT::iPTR)
2368 CaseVT = TLI.getPointerTy();
2370 // If the VT matches, then we will execute this case.
2371 if (CurNodeVT == CaseVT)
2374 // Otherwise, skip over this case.
2375 MatcherIndex += CaseSize;
2378 // If no cases matched, bail out.
2379 if (CaseSize == 0) break;
2381 // Otherwise, execute the case we found.
2382 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2383 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2386 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2387 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2388 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2389 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2390 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2391 Opcode-OPC_CheckChild0Type))
2394 case OPC_CheckCondCode:
2395 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2397 case OPC_CheckValueType:
2398 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2400 case OPC_CheckInteger:
2401 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2403 case OPC_CheckAndImm:
2404 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2406 case OPC_CheckOrImm:
2407 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2410 case OPC_CheckFoldableChainNode: {
2411 assert(NodeStack.size() != 1 && "No parent node");
2412 // Verify that all intermediate nodes between the root and this one have
2414 bool HasMultipleUses = false;
2415 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2416 if (!NodeStack[i].hasOneUse()) {
2417 HasMultipleUses = true;
2420 if (HasMultipleUses) break;
2422 // Check to see that the target thinks this is profitable to fold and that
2423 // we can fold it without inducing cycles in the graph.
2424 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2426 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2427 NodeToMatch, OptLevel,
2428 true/*We validate our own chains*/))
2433 case OPC_EmitInteger: {
2434 MVT::SimpleValueType VT =
2435 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2436 int64_t Val = MatcherTable[MatcherIndex++];
2438 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2439 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2440 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2443 case OPC_EmitRegister: {
2444 MVT::SimpleValueType VT =
2445 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2446 unsigned RegNo = MatcherTable[MatcherIndex++];
2447 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2448 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2451 case OPC_EmitRegister2: {
2452 // For targets w/ more than 256 register names, the register enum
2453 // values are stored in two bytes in the matcher table (just like
2455 MVT::SimpleValueType VT =
2456 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2457 unsigned RegNo = MatcherTable[MatcherIndex++];
2458 RegNo |= MatcherTable[MatcherIndex++] << 8;
2459 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2460 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2464 case OPC_EmitConvertToTarget: {
2465 // Convert from IMM/FPIMM to target version.
2466 unsigned RecNo = MatcherTable[MatcherIndex++];
2467 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2468 SDValue Imm = RecordedNodes[RecNo].first;
2470 if (Imm->getOpcode() == ISD::Constant) {
2471 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2472 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2473 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2474 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2475 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2478 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2482 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2483 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2484 // These are space-optimized forms of OPC_EmitMergeInputChains.
2485 assert(InputChain.getNode() == 0 &&
2486 "EmitMergeInputChains should be the first chain producing node");
2487 assert(ChainNodesMatched.empty() &&
2488 "Should only have one EmitMergeInputChains per match");
2490 // Read all of the chained nodes.
2491 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2492 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2493 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2495 // FIXME: What if other value results of the node have uses not matched
2497 if (ChainNodesMatched.back() != NodeToMatch &&
2498 !RecordedNodes[RecNo].first.hasOneUse()) {
2499 ChainNodesMatched.clear();
2503 // Merge the input chains if they are not intra-pattern references.
2504 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2506 if (InputChain.getNode() == 0)
2507 break; // Failed to merge.
2511 case OPC_EmitMergeInputChains: {
2512 assert(InputChain.getNode() == 0 &&
2513 "EmitMergeInputChains should be the first chain producing node");
2514 // This node gets a list of nodes we matched in the input that have
2515 // chains. We want to token factor all of the input chains to these nodes
2516 // together. However, if any of the input chains is actually one of the
2517 // nodes matched in this pattern, then we have an intra-match reference.
2518 // Ignore these because the newly token factored chain should not refer to
2520 unsigned NumChains = MatcherTable[MatcherIndex++];
2521 assert(NumChains != 0 && "Can't TF zero chains");
2523 assert(ChainNodesMatched.empty() &&
2524 "Should only have one EmitMergeInputChains per match");
2526 // Read all of the chained nodes.
2527 for (unsigned i = 0; i != NumChains; ++i) {
2528 unsigned RecNo = MatcherTable[MatcherIndex++];
2529 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2530 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2532 // FIXME: What if other value results of the node have uses not matched
2534 if (ChainNodesMatched.back() != NodeToMatch &&
2535 !RecordedNodes[RecNo].first.hasOneUse()) {
2536 ChainNodesMatched.clear();
2541 // If the inner loop broke out, the match fails.
2542 if (ChainNodesMatched.empty())
2545 // Merge the input chains if they are not intra-pattern references.
2546 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2548 if (InputChain.getNode() == 0)
2549 break; // Failed to merge.
2554 case OPC_EmitCopyToReg: {
2555 unsigned RecNo = MatcherTable[MatcherIndex++];
2556 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2557 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2559 if (InputChain.getNode() == 0)
2560 InputChain = CurDAG->getEntryNode();
2562 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2563 DestPhysReg, RecordedNodes[RecNo].first,
2566 InputGlue = InputChain.getValue(1);
2570 case OPC_EmitNodeXForm: {
2571 unsigned XFormNo = MatcherTable[MatcherIndex++];
2572 unsigned RecNo = MatcherTable[MatcherIndex++];
2573 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2574 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2575 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2580 case OPC_MorphNodeTo: {
2581 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2582 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2583 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2584 // Get the result VT list.
2585 unsigned NumVTs = MatcherTable[MatcherIndex++];
2586 SmallVector<EVT, 4> VTs;
2587 for (unsigned i = 0; i != NumVTs; ++i) {
2588 MVT::SimpleValueType VT =
2589 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2590 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2594 if (EmitNodeInfo & OPFL_Chain)
2595 VTs.push_back(MVT::Other);
2596 if (EmitNodeInfo & OPFL_GlueOutput)
2597 VTs.push_back(MVT::Glue);
2599 // This is hot code, so optimize the two most common cases of 1 and 2
2602 if (VTs.size() == 1)
2603 VTList = CurDAG->getVTList(VTs[0]);
2604 else if (VTs.size() == 2)
2605 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2607 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2609 // Get the operand list.
2610 unsigned NumOps = MatcherTable[MatcherIndex++];
2611 SmallVector<SDValue, 8> Ops;
2612 for (unsigned i = 0; i != NumOps; ++i) {
2613 unsigned RecNo = MatcherTable[MatcherIndex++];
2615 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2617 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2618 Ops.push_back(RecordedNodes[RecNo].first);
2621 // If there are variadic operands to add, handle them now.
2622 if (EmitNodeInfo & OPFL_VariadicInfo) {
2623 // Determine the start index to copy from.
2624 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2625 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2626 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2627 "Invalid variadic node");
2628 // Copy all of the variadic operands, not including a potential glue
2630 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2632 SDValue V = NodeToMatch->getOperand(i);
2633 if (V.getValueType() == MVT::Glue) break;
2638 // If this has chain/glue inputs, add them.
2639 if (EmitNodeInfo & OPFL_Chain)
2640 Ops.push_back(InputChain);
2641 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2642 Ops.push_back(InputGlue);
2646 if (Opcode != OPC_MorphNodeTo) {
2647 // If this is a normal EmitNode command, just create the new node and
2648 // add the results to the RecordedNodes list.
2649 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2650 VTList, Ops.data(), Ops.size());
2652 // Add all the non-glue/non-chain results to the RecordedNodes list.
2653 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2654 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2655 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2660 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2664 // If the node had chain/glue results, update our notion of the current
2666 if (EmitNodeInfo & OPFL_GlueOutput) {
2667 InputGlue = SDValue(Res, VTs.size()-1);
2668 if (EmitNodeInfo & OPFL_Chain)
2669 InputChain = SDValue(Res, VTs.size()-2);
2670 } else if (EmitNodeInfo & OPFL_Chain)
2671 InputChain = SDValue(Res, VTs.size()-1);
2673 // If the OPFL_MemRefs glue is set on this node, slap all of the
2674 // accumulated memrefs onto it.
2676 // FIXME: This is vastly incorrect for patterns with multiple outputs
2677 // instructions that access memory and for ComplexPatterns that match
2679 if (EmitNodeInfo & OPFL_MemRefs) {
2680 MachineSDNode::mmo_iterator MemRefs =
2681 MF->allocateMemRefsArray(MatchedMemRefs.size());
2682 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2683 cast<MachineSDNode>(Res)
2684 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2688 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2689 << " node: "; Res->dump(CurDAG); errs() << "\n");
2691 // If this was a MorphNodeTo then we're completely done!
2692 if (Opcode == OPC_MorphNodeTo) {
2693 // Update chain and glue uses.
2694 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2695 InputGlue, GlueResultNodesMatched, true);
2702 case OPC_MarkGlueResults: {
2703 unsigned NumNodes = MatcherTable[MatcherIndex++];
2705 // Read and remember all the glue-result nodes.
2706 for (unsigned i = 0; i != NumNodes; ++i) {
2707 unsigned RecNo = MatcherTable[MatcherIndex++];
2709 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2711 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2712 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2717 case OPC_CompleteMatch: {
2718 // The match has been completed, and any new nodes (if any) have been
2719 // created. Patch up references to the matched dag to use the newly
2721 unsigned NumResults = MatcherTable[MatcherIndex++];
2723 for (unsigned i = 0; i != NumResults; ++i) {
2724 unsigned ResSlot = MatcherTable[MatcherIndex++];
2726 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2728 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2729 SDValue Res = RecordedNodes[ResSlot].first;
2731 assert(i < NodeToMatch->getNumValues() &&
2732 NodeToMatch->getValueType(i) != MVT::Other &&
2733 NodeToMatch->getValueType(i) != MVT::Glue &&
2734 "Invalid number of results to complete!");
2735 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2736 NodeToMatch->getValueType(i) == MVT::iPTR ||
2737 Res.getValueType() == MVT::iPTR ||
2738 NodeToMatch->getValueType(i).getSizeInBits() ==
2739 Res.getValueType().getSizeInBits()) &&
2740 "invalid replacement");
2741 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2744 // If the root node defines glue, add it to the glue nodes to update list.
2745 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2746 GlueResultNodesMatched.push_back(NodeToMatch);
2748 // Update chain and glue uses.
2749 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2750 InputGlue, GlueResultNodesMatched, false);
2752 assert(NodeToMatch->use_empty() &&
2753 "Didn't replace all uses of the node?");
2755 // FIXME: We just return here, which interacts correctly with SelectRoot
2756 // above. We should fix this to not return an SDNode* anymore.
2761 // If the code reached this point, then the match failed. See if there is
2762 // another child to try in the current 'Scope', otherwise pop it until we
2763 // find a case to check.
2764 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2765 ++NumDAGIselRetries;
2767 if (MatchScopes.empty()) {
2768 CannotYetSelect(NodeToMatch);
2772 // Restore the interpreter state back to the point where the scope was
2774 MatchScope &LastScope = MatchScopes.back();
2775 RecordedNodes.resize(LastScope.NumRecordedNodes);
2777 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2778 N = NodeStack.back();
2780 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2781 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2782 MatcherIndex = LastScope.FailIndex;
2784 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2786 InputChain = LastScope.InputChain;
2787 InputGlue = LastScope.InputGlue;
2788 if (!LastScope.HasChainNodesMatched)
2789 ChainNodesMatched.clear();
2790 if (!LastScope.HasGlueResultNodesMatched)
2791 GlueResultNodesMatched.clear();
2793 // Check to see what the offset is at the new MatcherIndex. If it is zero
2794 // we have reached the end of this scope, otherwise we have another child
2795 // in the current scope to try.
2796 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2797 if (NumToSkip & 128)
2798 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2800 // If we have another child in this scope to match, update FailIndex and
2802 if (NumToSkip != 0) {
2803 LastScope.FailIndex = MatcherIndex+NumToSkip;
2807 // End of this scope, pop it and try the next child in the containing
2809 MatchScopes.pop_back();
2816 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2818 raw_string_ostream Msg(msg);
2819 Msg << "Cannot select: ";
2821 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2822 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2823 N->getOpcode() != ISD::INTRINSIC_VOID) {
2824 N->printrFull(Msg, CurDAG);
2826 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2828 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2829 if (iid < Intrinsic::num_intrinsics)
2830 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2831 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2832 Msg << "target intrinsic %" << TII->getName(iid);
2834 Msg << "unknown intrinsic #" << iid;
2836 report_fatal_error(Msg.str());
2839 char SelectionDAGISel::ID = 0;