1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64CallingConvention.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64ISelLowering.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64RegisterInfo.h"
19 #include "AArch64Subtarget.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/APInt.h"
24 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineMemOperand.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/MachineValueType.h"
41 #include "llvm/CodeGen/RuntimeLibcalls.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/CodeGen/SelectionDAGNodes.h"
44 #include "llvm/CodeGen/ValueTypes.h"
45 #include "llvm/IR/Attributes.h"
46 #include "llvm/IR/Constants.h"
47 #include "llvm/IR/DataLayout.h"
48 #include "llvm/IR/DebugLoc.h"
49 #include "llvm/IR/DerivedTypes.h"
50 #include "llvm/IR/Function.h"
51 #include "llvm/IR/GetElementPtrTypeIterator.h"
52 #include "llvm/IR/GlobalValue.h"
53 #include "llvm/IR/Instruction.h"
54 #include "llvm/IR/Instructions.h"
55 #include "llvm/IR/Intrinsics.h"
56 #include "llvm/IR/IRBuilder.h"
57 #include "llvm/IR/Module.h"
58 #include "llvm/IR/OperandTraits.h"
59 #include "llvm/IR/Type.h"
60 #include "llvm/IR/Use.h"
61 #include "llvm/IR/Value.h"
62 #include "llvm/MC/MCRegisterInfo.h"
63 #include "llvm/Support/Casting.h"
64 #include "llvm/Support/CodeGen.h"
65 #include "llvm/Support/CommandLine.h"
66 #include "llvm/Support/Compiler.h"
67 #include "llvm/Support/Debug.h"
68 #include "llvm/Support/ErrorHandling.h"
69 #include "llvm/Support/MathExtras.h"
70 #include "llvm/Support/raw_ostream.h"
71 #include "llvm/Target/TargetCallingConv.h"
72 #include "llvm/Target/TargetInstrInfo.h"
73 #include "llvm/Target/TargetMachine.h"
74 #include "llvm/Target/TargetOptions.h"
89 #define DEBUG_TYPE "aarch64-lower"
91 STATISTIC(NumTailCalls, "Number of tail calls");
92 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
95 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
96 cl::desc("Allow AArch64 SLI/SRI formation"),
99 // FIXME: The necessary dtprel relocations don't seem to be supported
100 // well in the GNU bfd and gold linkers at the moment. Therefore, by
101 // default, for now, fall back to GeneralDynamic code generation.
102 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
103 "aarch64-elf-ldtls-generation", cl::Hidden,
104 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
107 /// Value type used for condition codes.
108 static const MVT MVT_CC = MVT::i32;
110 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
111 const AArch64Subtarget &STI)
112 : TargetLowering(TM), Subtarget(&STI) {
113 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
114 // we have to make something up. Arbitrarily, choose ZeroOrOne.
115 setBooleanContents(ZeroOrOneBooleanContent);
116 // When comparing vectors the result sets the different elements in the
117 // vector to all-one or all-zero.
118 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
120 // Set up the register classes.
121 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
122 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
124 if (Subtarget->hasFPARMv8()) {
125 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
126 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
127 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
128 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
131 if (Subtarget->hasNEON()) {
132 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
133 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
134 // Someone set us up the NEON.
135 addDRTypeForNEON(MVT::v2f32);
136 addDRTypeForNEON(MVT::v8i8);
137 addDRTypeForNEON(MVT::v4i16);
138 addDRTypeForNEON(MVT::v2i32);
139 addDRTypeForNEON(MVT::v1i64);
140 addDRTypeForNEON(MVT::v1f64);
141 addDRTypeForNEON(MVT::v4f16);
143 addQRTypeForNEON(MVT::v4f32);
144 addQRTypeForNEON(MVT::v2f64);
145 addQRTypeForNEON(MVT::v16i8);
146 addQRTypeForNEON(MVT::v8i16);
147 addQRTypeForNEON(MVT::v4i32);
148 addQRTypeForNEON(MVT::v2i64);
149 addQRTypeForNEON(MVT::v8f16);
152 // Compute derived properties from the register classes
153 computeRegisterProperties(Subtarget->getRegisterInfo());
155 // Provide all sorts of operation actions
156 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
157 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
158 setOperationAction(ISD::SETCC, MVT::i32, Custom);
159 setOperationAction(ISD::SETCC, MVT::i64, Custom);
160 setOperationAction(ISD::SETCC, MVT::f32, Custom);
161 setOperationAction(ISD::SETCC, MVT::f64, Custom);
162 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
163 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
164 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
165 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
166 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
167 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
168 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
169 setOperationAction(ISD::SELECT, MVT::i32, Custom);
170 setOperationAction(ISD::SELECT, MVT::i64, Custom);
171 setOperationAction(ISD::SELECT, MVT::f32, Custom);
172 setOperationAction(ISD::SELECT, MVT::f64, Custom);
173 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
174 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
176 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
177 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
178 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
180 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
181 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
182 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
184 setOperationAction(ISD::FREM, MVT::f32, Expand);
185 setOperationAction(ISD::FREM, MVT::f64, Expand);
186 setOperationAction(ISD::FREM, MVT::f80, Expand);
188 // Custom lowering hooks are needed for XOR
189 // to fold it into CSINC/CSINV.
190 setOperationAction(ISD::XOR, MVT::i32, Custom);
191 setOperationAction(ISD::XOR, MVT::i64, Custom);
193 // Virtually no operation on f128 is legal, but LLVM can't expand them when
194 // there's a valid register class, so we need custom operations in most cases.
195 setOperationAction(ISD::FABS, MVT::f128, Expand);
196 setOperationAction(ISD::FADD, MVT::f128, Custom);
197 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
198 setOperationAction(ISD::FCOS, MVT::f128, Expand);
199 setOperationAction(ISD::FDIV, MVT::f128, Custom);
200 setOperationAction(ISD::FMA, MVT::f128, Expand);
201 setOperationAction(ISD::FMUL, MVT::f128, Custom);
202 setOperationAction(ISD::FNEG, MVT::f128, Expand);
203 setOperationAction(ISD::FPOW, MVT::f128, Expand);
204 setOperationAction(ISD::FREM, MVT::f128, Expand);
205 setOperationAction(ISD::FRINT, MVT::f128, Expand);
206 setOperationAction(ISD::FSIN, MVT::f128, Expand);
207 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
208 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
209 setOperationAction(ISD::FSUB, MVT::f128, Custom);
210 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
211 setOperationAction(ISD::SETCC, MVT::f128, Custom);
212 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
213 setOperationAction(ISD::SELECT, MVT::f128, Custom);
214 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
215 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
217 // Lowering for many of the conversions is actually specified by the non-f128
218 // type. The LowerXXX function will be trivial when f128 isn't involved.
219 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
220 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
221 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
222 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
223 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
224 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
225 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
226 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
227 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
228 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
229 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
230 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
231 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
232 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
234 // Variable arguments.
235 setOperationAction(ISD::VASTART, MVT::Other, Custom);
236 setOperationAction(ISD::VAARG, MVT::Other, Custom);
237 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
238 setOperationAction(ISD::VAEND, MVT::Other, Expand);
240 // Variable-sized objects.
241 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
242 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
245 // Constant pool entries
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
249 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
251 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
252 setOperationAction(ISD::ADDC, MVT::i32, Custom);
253 setOperationAction(ISD::ADDE, MVT::i32, Custom);
254 setOperationAction(ISD::SUBC, MVT::i32, Custom);
255 setOperationAction(ISD::SUBE, MVT::i32, Custom);
256 setOperationAction(ISD::ADDC, MVT::i64, Custom);
257 setOperationAction(ISD::ADDE, MVT::i64, Custom);
258 setOperationAction(ISD::SUBC, MVT::i64, Custom);
259 setOperationAction(ISD::SUBE, MVT::i64, Custom);
261 // AArch64 lacks both left-rotate and popcount instructions.
262 setOperationAction(ISD::ROTL, MVT::i32, Expand);
263 setOperationAction(ISD::ROTL, MVT::i64, Expand);
264 for (MVT VT : MVT::vector_valuetypes()) {
265 setOperationAction(ISD::ROTL, VT, Expand);
266 setOperationAction(ISD::ROTR, VT, Expand);
269 // AArch64 doesn't have {U|S}MUL_LOHI.
270 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
271 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
273 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
274 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
276 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
277 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
278 for (MVT VT : MVT::vector_valuetypes()) {
279 setOperationAction(ISD::SDIVREM, VT, Expand);
280 setOperationAction(ISD::UDIVREM, VT, Expand);
282 setOperationAction(ISD::SREM, MVT::i32, Expand);
283 setOperationAction(ISD::SREM, MVT::i64, Expand);
284 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
285 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UREM, MVT::i64, Expand);
289 // Custom lower Add/Sub/Mul with overflow.
290 setOperationAction(ISD::SADDO, MVT::i32, Custom);
291 setOperationAction(ISD::SADDO, MVT::i64, Custom);
292 setOperationAction(ISD::UADDO, MVT::i32, Custom);
293 setOperationAction(ISD::UADDO, MVT::i64, Custom);
294 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
295 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
296 setOperationAction(ISD::USUBO, MVT::i32, Custom);
297 setOperationAction(ISD::USUBO, MVT::i64, Custom);
298 setOperationAction(ISD::SMULO, MVT::i32, Custom);
299 setOperationAction(ISD::SMULO, MVT::i64, Custom);
300 setOperationAction(ISD::UMULO, MVT::i32, Custom);
301 setOperationAction(ISD::UMULO, MVT::i64, Custom);
303 setOperationAction(ISD::FSIN, MVT::f32, Expand);
304 setOperationAction(ISD::FSIN, MVT::f64, Expand);
305 setOperationAction(ISD::FCOS, MVT::f32, Expand);
306 setOperationAction(ISD::FCOS, MVT::f64, Expand);
307 setOperationAction(ISD::FPOW, MVT::f32, Expand);
308 setOperationAction(ISD::FPOW, MVT::f64, Expand);
309 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
310 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
312 // f16 is a storage-only type, always promote it to f32.
313 setOperationAction(ISD::SETCC, MVT::f16, Promote);
314 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
315 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
316 setOperationAction(ISD::SELECT, MVT::f16, Promote);
317 setOperationAction(ISD::FADD, MVT::f16, Promote);
318 setOperationAction(ISD::FSUB, MVT::f16, Promote);
319 setOperationAction(ISD::FMUL, MVT::f16, Promote);
320 setOperationAction(ISD::FDIV, MVT::f16, Promote);
321 setOperationAction(ISD::FREM, MVT::f16, Promote);
322 setOperationAction(ISD::FMA, MVT::f16, Promote);
323 setOperationAction(ISD::FNEG, MVT::f16, Promote);
324 setOperationAction(ISD::FABS, MVT::f16, Promote);
325 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
326 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
327 setOperationAction(ISD::FCOS, MVT::f16, Promote);
328 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
329 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
330 setOperationAction(ISD::FPOW, MVT::f16, Promote);
331 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
332 setOperationAction(ISD::FRINT, MVT::f16, Promote);
333 setOperationAction(ISD::FSIN, MVT::f16, Promote);
334 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
335 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
336 setOperationAction(ISD::FEXP, MVT::f16, Promote);
337 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
338 setOperationAction(ISD::FLOG, MVT::f16, Promote);
339 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
340 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
341 setOperationAction(ISD::FROUND, MVT::f16, Promote);
342 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
343 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
344 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
345 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
346 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
348 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
350 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
351 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
352 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
353 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
354 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
355 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
356 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
357 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
358 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
359 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
360 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
361 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
363 // Expand all other v4f16 operations.
364 // FIXME: We could generate better code by promoting some operations to
366 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
367 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
368 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
369 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
370 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
371 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
372 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
373 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
374 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
375 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
376 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
377 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
378 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
379 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
380 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
381 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
382 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
383 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
384 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
385 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
386 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
387 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
388 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
389 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
390 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
391 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
394 // v8f16 is also a storage-only type, so expand it.
395 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
396 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
397 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
398 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
399 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
400 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
401 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
402 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
403 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
404 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
405 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
406 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
407 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
408 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
409 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
410 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
411 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
412 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
413 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
414 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
415 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
416 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
417 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
418 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
419 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
420 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
421 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
422 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
423 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
424 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
425 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
427 // AArch64 has implementations of a lot of rounding-like FP operations.
428 for (MVT Ty : {MVT::f32, MVT::f64}) {
429 setOperationAction(ISD::FFLOOR, Ty, Legal);
430 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
431 setOperationAction(ISD::FCEIL, Ty, Legal);
432 setOperationAction(ISD::FRINT, Ty, Legal);
433 setOperationAction(ISD::FTRUNC, Ty, Legal);
434 setOperationAction(ISD::FROUND, Ty, Legal);
435 setOperationAction(ISD::FMINNUM, Ty, Legal);
436 setOperationAction(ISD::FMAXNUM, Ty, Legal);
437 setOperationAction(ISD::FMINNAN, Ty, Legal);
438 setOperationAction(ISD::FMAXNAN, Ty, Legal);
441 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
443 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
445 // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
446 // This requires the Performance Monitors extension.
447 if (Subtarget->hasPerfMon())
448 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
450 if (Subtarget->isTargetMachO()) {
451 // For iOS, we don't want to the normal expansion of a libcall to
452 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
454 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
455 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
457 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
458 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
461 // Make floating-point constants legal for the large code model, so they don't
462 // become loads from the constant pool.
463 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
464 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
465 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
468 // AArch64 does not have floating-point extending loads, i1 sign-extending
469 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
470 for (MVT VT : MVT::fp_valuetypes()) {
471 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
472 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
473 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
474 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
476 for (MVT VT : MVT::integer_valuetypes())
477 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
479 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
480 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
481 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
482 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
483 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
484 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
485 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
487 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
488 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
490 // Indexed loads and stores are supported.
491 for (unsigned im = (unsigned)ISD::PRE_INC;
492 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
493 setIndexedLoadAction(im, MVT::i8, Legal);
494 setIndexedLoadAction(im, MVT::i16, Legal);
495 setIndexedLoadAction(im, MVT::i32, Legal);
496 setIndexedLoadAction(im, MVT::i64, Legal);
497 setIndexedLoadAction(im, MVT::f64, Legal);
498 setIndexedLoadAction(im, MVT::f32, Legal);
499 setIndexedLoadAction(im, MVT::f16, Legal);
500 setIndexedStoreAction(im, MVT::i8, Legal);
501 setIndexedStoreAction(im, MVT::i16, Legal);
502 setIndexedStoreAction(im, MVT::i32, Legal);
503 setIndexedStoreAction(im, MVT::i64, Legal);
504 setIndexedStoreAction(im, MVT::f64, Legal);
505 setIndexedStoreAction(im, MVT::f32, Legal);
506 setIndexedStoreAction(im, MVT::f16, Legal);
510 setOperationAction(ISD::TRAP, MVT::Other, Legal);
512 // We combine OR nodes for bitfield operations.
513 setTargetDAGCombine(ISD::OR);
515 // Vector add and sub nodes may conceal a high-half opportunity.
516 // Also, try to fold ADD into CSINC/CSINV..
517 setTargetDAGCombine(ISD::ADD);
518 setTargetDAGCombine(ISD::SUB);
519 setTargetDAGCombine(ISD::SRL);
520 setTargetDAGCombine(ISD::XOR);
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::UINT_TO_FP);
524 setTargetDAGCombine(ISD::FP_TO_SINT);
525 setTargetDAGCombine(ISD::FP_TO_UINT);
526 setTargetDAGCombine(ISD::FDIV);
528 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
530 setTargetDAGCombine(ISD::ANY_EXTEND);
531 setTargetDAGCombine(ISD::ZERO_EXTEND);
532 setTargetDAGCombine(ISD::SIGN_EXTEND);
533 setTargetDAGCombine(ISD::BITCAST);
534 setTargetDAGCombine(ISD::CONCAT_VECTORS);
535 setTargetDAGCombine(ISD::STORE);
536 if (Subtarget->supportsAddressTopByteIgnored())
537 setTargetDAGCombine(ISD::LOAD);
539 setTargetDAGCombine(ISD::MUL);
541 setTargetDAGCombine(ISD::SELECT);
542 setTargetDAGCombine(ISD::VSELECT);
544 setTargetDAGCombine(ISD::INTRINSIC_VOID);
545 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
546 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
547 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
549 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
550 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
551 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
553 setStackPointerRegisterToSaveRestore(AArch64::SP);
555 setSchedulingPreference(Sched::Hybrid);
558 MaskAndBranchFoldingIsLegal = true;
559 EnableExtLdPromotion = true;
561 // Set required alignment.
562 setMinFunctionAlignment(2);
563 // Set preferred alignments.
564 setPrefFunctionAlignment(STI.getPrefFunctionAlignment());
565 setPrefLoopAlignment(STI.getPrefLoopAlignment());
567 // Only change the limit for entries in a jump table if specified by
568 // the subtarget, but not at the command line.
569 unsigned MaxJT = STI.getMaximumJumpTableSize();
570 if (MaxJT && getMaximumJumpTableSize() == 0)
571 setMaximumJumpTableSize(MaxJT);
573 setHasExtractBitsInsn(true);
575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
577 if (Subtarget->hasNEON()) {
578 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
579 // silliness like this:
580 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
581 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
582 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
583 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
584 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
585 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
586 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
587 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
588 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
589 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
590 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
591 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
592 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
593 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
594 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
595 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
596 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
597 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
598 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
599 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
600 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
601 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
602 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
603 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
604 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
606 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
607 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
608 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
609 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
610 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
612 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
614 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
615 // elements smaller than i32, so promote the input to i32 first.
616 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
617 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
618 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
619 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
620 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
621 // -> v8f16 conversions.
622 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
623 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
624 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
625 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
626 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
627 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
628 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
629 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
630 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
631 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
632 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
633 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
634 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
636 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
637 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
639 setOperationAction(ISD::CTTZ, MVT::v2i8, Expand);
640 setOperationAction(ISD::CTTZ, MVT::v4i16, Expand);
641 setOperationAction(ISD::CTTZ, MVT::v2i32, Expand);
642 setOperationAction(ISD::CTTZ, MVT::v1i64, Expand);
643 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand);
644 setOperationAction(ISD::CTTZ, MVT::v8i16, Expand);
645 setOperationAction(ISD::CTTZ, MVT::v4i32, Expand);
646 setOperationAction(ISD::CTTZ, MVT::v2i64, Expand);
648 // AArch64 doesn't have MUL.2d:
649 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
650 // Custom handling for some quad-vector types to detect MULL.
651 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
652 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
653 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
655 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
656 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
657 // Likewise, narrowing and extending vector loads/stores aren't handled
659 for (MVT VT : MVT::vector_valuetypes()) {
660 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
662 setOperationAction(ISD::MULHS, VT, Expand);
663 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
664 setOperationAction(ISD::MULHU, VT, Expand);
665 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
667 setOperationAction(ISD::BSWAP, VT, Expand);
669 for (MVT InnerVT : MVT::vector_valuetypes()) {
670 setTruncStoreAction(VT, InnerVT, Expand);
671 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
672 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
673 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
677 // AArch64 has implementations of a lot of rounding-like FP operations.
678 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
679 setOperationAction(ISD::FFLOOR, Ty, Legal);
680 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
681 setOperationAction(ISD::FCEIL, Ty, Legal);
682 setOperationAction(ISD::FRINT, Ty, Legal);
683 setOperationAction(ISD::FTRUNC, Ty, Legal);
684 setOperationAction(ISD::FROUND, Ty, Legal);
688 PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
691 void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
692 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
693 setOperationAction(ISD::LOAD, VT, Promote);
694 AddPromotedToType(ISD::LOAD, VT, MVT::v2i32);
696 setOperationAction(ISD::STORE, VT, Promote);
697 AddPromotedToType(ISD::STORE, VT, MVT::v2i32);
698 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
699 setOperationAction(ISD::LOAD, VT, Promote);
700 AddPromotedToType(ISD::LOAD, VT, MVT::v2i64);
702 setOperationAction(ISD::STORE, VT, Promote);
703 AddPromotedToType(ISD::STORE, VT, MVT::v2i64);
706 // Mark vector float intrinsics as expand.
707 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
708 setOperationAction(ISD::FSIN, VT, Expand);
709 setOperationAction(ISD::FCOS, VT, Expand);
710 setOperationAction(ISD::FPOWI, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::FLOG, VT, Expand);
713 setOperationAction(ISD::FLOG2, VT, Expand);
714 setOperationAction(ISD::FLOG10, VT, Expand);
715 setOperationAction(ISD::FEXP, VT, Expand);
716 setOperationAction(ISD::FEXP2, VT, Expand);
718 // But we do support custom-lowering for FCOPYSIGN.
719 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
723 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
724 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
725 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
727 setOperationAction(ISD::SRA, VT, Custom);
728 setOperationAction(ISD::SRL, VT, Custom);
729 setOperationAction(ISD::SHL, VT, Custom);
730 setOperationAction(ISD::AND, VT, Custom);
731 setOperationAction(ISD::OR, VT, Custom);
732 setOperationAction(ISD::SETCC, VT, Custom);
733 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
735 setOperationAction(ISD::SELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 setOperationAction(ISD::VSELECT, VT, Expand);
738 for (MVT InnerVT : MVT::all_valuetypes())
739 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
741 // CNT supports only B element sizes.
742 if (VT != MVT::v8i8 && VT != MVT::v16i8)
743 setOperationAction(ISD::CTPOP, VT, Expand);
745 setOperationAction(ISD::UDIV, VT, Expand);
746 setOperationAction(ISD::SDIV, VT, Expand);
747 setOperationAction(ISD::UREM, VT, Expand);
748 setOperationAction(ISD::SREM, VT, Expand);
749 setOperationAction(ISD::FREM, VT, Expand);
751 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
752 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
754 // [SU][MIN|MAX] are available for all NEON types apart from i64.
755 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
756 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
757 setOperationAction(Opcode, VT, Legal);
759 // F[MIN|MAX][NUM|NAN] are available for all FP NEON types (not f16 though!).
760 if (VT.isFloatingPoint() && VT.getVectorElementType() != MVT::f16)
761 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
762 ISD::FMINNUM, ISD::FMAXNUM})
763 setOperationAction(Opcode, VT, Legal);
765 if (Subtarget->isLittleEndian()) {
766 for (unsigned im = (unsigned)ISD::PRE_INC;
767 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
768 setIndexedLoadAction(im, VT, Legal);
769 setIndexedStoreAction(im, VT, Legal);
774 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
775 addRegisterClass(VT, &AArch64::FPR64RegClass);
776 addTypeForNEON(VT, MVT::v2i32);
779 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
780 addRegisterClass(VT, &AArch64::FPR128RegClass);
781 addTypeForNEON(VT, MVT::v4i32);
784 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
788 return VT.changeVectorElementTypeToInteger();
791 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
792 /// Mask are known to be either zero or one and return them in the
793 /// KnownZero/KnownOne bitsets.
794 void AArch64TargetLowering::computeKnownBitsForTargetNode(
795 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
796 const SelectionDAG &DAG, unsigned Depth) const {
797 switch (Op.getOpcode()) {
800 case AArch64ISD::CSEL: {
801 APInt KnownZero2, KnownOne2;
802 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
803 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
804 KnownZero &= KnownZero2;
805 KnownOne &= KnownOne2;
808 case ISD::INTRINSIC_W_CHAIN: {
809 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
810 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
813 case Intrinsic::aarch64_ldaxr:
814 case Intrinsic::aarch64_ldxr: {
815 unsigned BitWidth = KnownOne.getBitWidth();
816 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
817 unsigned MemBits = VT.getScalarSizeInBits();
818 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
824 case ISD::INTRINSIC_WO_CHAIN:
825 case ISD::INTRINSIC_VOID: {
826 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
830 case Intrinsic::aarch64_neon_umaxv:
831 case Intrinsic::aarch64_neon_uminv: {
832 // Figure out the datatype of the vector operand. The UMINV instruction
833 // will zero extend the result, so we can mark as known zero all the
834 // bits larger than the element datatype. 32-bit or larget doesn't need
835 // this as those are legal types and will be handled by isel directly.
836 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
837 unsigned BitWidth = KnownZero.getBitWidth();
838 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
839 assert(BitWidth >= 8 && "Unexpected width!");
840 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
842 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
843 assert(BitWidth >= 16 && "Unexpected width!");
844 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
854 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
859 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
863 if (Subtarget->requiresStrictAlign())
867 // Some CPUs are fine with unaligned stores except for 128-bit ones.
868 *Fast = !Subtarget->isMisaligned128StoreSlow() || VT.getStoreSize() != 16 ||
869 // See comments in performSTORECombine() for more details about
872 // Code that uses clang vector extensions can mark that it
873 // wants unaligned accesses to be treated as fast by
874 // underspecifying alignment to be 1 or 2.
877 // Disregard v2i64. Memcpy lowering produces those and splitting
878 // them regresses performance on micro-benchmarks and olden/bh.
885 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
886 const TargetLibraryInfo *libInfo) const {
887 return AArch64::createFastISel(funcInfo, libInfo);
890 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
891 switch ((AArch64ISD::NodeType)Opcode) {
892 case AArch64ISD::FIRST_NUMBER: break;
893 case AArch64ISD::CALL: return "AArch64ISD::CALL";
894 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
895 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
896 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
897 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
898 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
899 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
900 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
901 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
902 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
903 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
904 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
905 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
906 case AArch64ISD::ADC: return "AArch64ISD::ADC";
907 case AArch64ISD::SBC: return "AArch64ISD::SBC";
908 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
909 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
910 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
911 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
912 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
913 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
914 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
915 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
916 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
917 case AArch64ISD::DUP: return "AArch64ISD::DUP";
918 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
919 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
920 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
921 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
922 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
923 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
924 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
925 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
926 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
927 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
928 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
929 case AArch64ISD::BICi: return "AArch64ISD::BICi";
930 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
931 case AArch64ISD::BSL: return "AArch64ISD::BSL";
932 case AArch64ISD::NEG: return "AArch64ISD::NEG";
933 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
934 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
935 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
936 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
937 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
938 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
939 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
940 case AArch64ISD::REV16: return "AArch64ISD::REV16";
941 case AArch64ISD::REV32: return "AArch64ISD::REV32";
942 case AArch64ISD::REV64: return "AArch64ISD::REV64";
943 case AArch64ISD::EXT: return "AArch64ISD::EXT";
944 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
945 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
946 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
947 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
948 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
949 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
950 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
951 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
952 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
953 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
954 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
955 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
956 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
957 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
958 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
959 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
960 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
961 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
962 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
963 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
964 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
965 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
966 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
967 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
968 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
969 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
970 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
971 case AArch64ISD::NOT: return "AArch64ISD::NOT";
972 case AArch64ISD::BIT: return "AArch64ISD::BIT";
973 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
974 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
975 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
976 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
977 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
978 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
979 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
980 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
981 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
982 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
983 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
984 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
985 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
986 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
987 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
988 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
989 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
990 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
991 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
992 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
993 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
994 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
995 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
996 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
997 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
998 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
999 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
1000 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
1001 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
1002 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
1003 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
1004 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
1005 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
1006 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
1007 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
1008 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
1009 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
1010 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
1011 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
1012 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
1013 case AArch64ISD::FRECPE: return "AArch64ISD::FRECPE";
1014 case AArch64ISD::FRECPS: return "AArch64ISD::FRECPS";
1015 case AArch64ISD::FRSQRTE: return "AArch64ISD::FRSQRTE";
1016 case AArch64ISD::FRSQRTS: return "AArch64ISD::FRSQRTS";
1022 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
1023 MachineBasicBlock *MBB) const {
1024 // We materialise the F128CSEL pseudo-instruction as some control flow and a
1028 // [... previous instrs leading to comparison ...]
1034 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
1036 MachineFunction *MF = MBB->getParent();
1037 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1038 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1039 DebugLoc DL = MI.getDebugLoc();
1040 MachineFunction::iterator It = ++MBB->getIterator();
1042 unsigned DestReg = MI.getOperand(0).getReg();
1043 unsigned IfTrueReg = MI.getOperand(1).getReg();
1044 unsigned IfFalseReg = MI.getOperand(2).getReg();
1045 unsigned CondCode = MI.getOperand(3).getImm();
1046 bool NZCVKilled = MI.getOperand(4).isKill();
1048 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
1049 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
1050 MF->insert(It, TrueBB);
1051 MF->insert(It, EndBB);
1053 // Transfer rest of current basic-block to EndBB
1054 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
1056 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
1058 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
1059 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
1060 MBB->addSuccessor(TrueBB);
1061 MBB->addSuccessor(EndBB);
1063 // TrueBB falls through to the end.
1064 TrueBB->addSuccessor(EndBB);
1067 TrueBB->addLiveIn(AArch64::NZCV);
1068 EndBB->addLiveIn(AArch64::NZCV);
1071 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
1077 MI.eraseFromParent();
1081 MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
1082 MachineInstr &MI, MachineBasicBlock *BB) const {
1083 switch (MI.getOpcode()) {
1088 llvm_unreachable("Unexpected instruction for custom inserter!");
1090 case AArch64::F128CSEL:
1091 return EmitF128CSEL(MI, BB);
1093 case TargetOpcode::STACKMAP:
1094 case TargetOpcode::PATCHPOINT:
1095 return emitPatchPoint(MI, BB);
1099 //===----------------------------------------------------------------------===//
1100 // AArch64 Lowering private implementation.
1101 //===----------------------------------------------------------------------===//
1103 //===----------------------------------------------------------------------===//
1105 //===----------------------------------------------------------------------===//
1107 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1109 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1112 llvm_unreachable("Unknown condition code!");
1114 return AArch64CC::NE;
1116 return AArch64CC::EQ;
1118 return AArch64CC::GT;
1120 return AArch64CC::GE;
1122 return AArch64CC::LT;
1124 return AArch64CC::LE;
1126 return AArch64CC::HI;
1128 return AArch64CC::HS;
1130 return AArch64CC::LO;
1132 return AArch64CC::LS;
1136 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1137 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1138 AArch64CC::CondCode &CondCode,
1139 AArch64CC::CondCode &CondCode2) {
1140 CondCode2 = AArch64CC::AL;
1143 llvm_unreachable("Unknown FP condition!");
1146 CondCode = AArch64CC::EQ;
1150 CondCode = AArch64CC::GT;
1154 CondCode = AArch64CC::GE;
1157 CondCode = AArch64CC::MI;
1160 CondCode = AArch64CC::LS;
1163 CondCode = AArch64CC::MI;
1164 CondCode2 = AArch64CC::GT;
1167 CondCode = AArch64CC::VC;
1170 CondCode = AArch64CC::VS;
1173 CondCode = AArch64CC::EQ;
1174 CondCode2 = AArch64CC::VS;
1177 CondCode = AArch64CC::HI;
1180 CondCode = AArch64CC::PL;
1184 CondCode = AArch64CC::LT;
1188 CondCode = AArch64CC::LE;
1192 CondCode = AArch64CC::NE;
1197 /// Convert a DAG fp condition code to an AArch64 CC.
1198 /// This differs from changeFPCCToAArch64CC in that it returns cond codes that
1199 /// should be AND'ed instead of OR'ed.
1200 static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
1201 AArch64CC::CondCode &CondCode,
1202 AArch64CC::CondCode &CondCode2) {
1203 CondCode2 = AArch64CC::AL;
1206 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1207 assert(CondCode2 == AArch64CC::AL);
1211 // == ((a olt b) || (a ogt b))
1212 // == ((a ord b) && (a une b))
1213 CondCode = AArch64CC::VC;
1214 CondCode2 = AArch64CC::NE;
1218 // == ((a uno b) || (a oeq b))
1219 // == ((a ule b) && (a uge b))
1220 CondCode = AArch64CC::PL;
1221 CondCode2 = AArch64CC::LE;
1226 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1227 /// CC usable with the vector instructions. Fewer operations are available
1228 /// without a real NZCV register, so we have to use less efficient combinations
1229 /// to get the same effect.
1230 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1231 AArch64CC::CondCode &CondCode,
1232 AArch64CC::CondCode &CondCode2,
1237 // Mostly the scalar mappings work fine.
1238 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1244 CondCode = AArch64CC::MI;
1245 CondCode2 = AArch64CC::GE;
1252 // All of the compare-mask comparisons are ordered, but we can switch
1253 // between the two by a double inversion. E.g. ULE == !OGT.
1255 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1260 static bool isLegalArithImmed(uint64_t C) {
1261 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1262 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1265 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1266 const SDLoc &dl, SelectionDAG &DAG) {
1267 EVT VT = LHS.getValueType();
1269 if (VT.isFloatingPoint()) {
1270 assert(VT != MVT::f128);
1271 if (VT == MVT::f16) {
1272 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
1273 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
1276 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1279 // The CMP instruction is just an alias for SUBS, and representing it as
1280 // SUBS means that it's possible to get CSE with subtract operations.
1281 // A later phase can perform the optimization of setting the destination
1282 // register to WZR/XZR if it ends up being unused.
1283 unsigned Opcode = AArch64ISD::SUBS;
1285 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
1286 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1287 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1288 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1289 // can be set differently by this operation. It comes down to whether
1290 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1291 // everything is fine. If not then the optimization is wrong. Thus general
1292 // comparisons are only valid if op2 != 0.
1294 // So, finally, the only LLVM-native comparisons that don't mention C and V
1295 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1296 // the absence of information about op2.
1297 Opcode = AArch64ISD::ADDS;
1298 RHS = RHS.getOperand(1);
1299 } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
1300 !isUnsignedIntSetCC(CC)) {
1301 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1302 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1303 // of the signed comparisons.
1304 Opcode = AArch64ISD::ANDS;
1305 RHS = LHS.getOperand(1);
1306 LHS = LHS.getOperand(0);
1309 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1313 /// \defgroup AArch64CCMP CMP;CCMP matching
1315 /// These functions deal with the formation of CMP;CCMP;... sequences.
1316 /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1317 /// a comparison. They set the NZCV flags to a predefined value if their
1318 /// predicate is false. This allows to express arbitrary conjunctions, for
1319 /// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1322 /// ccmp B, inv(CB), CA
1323 /// check for CB flags
1325 /// In general we can create code for arbitrary "... (and (and A B) C)"
1326 /// sequences. We can also implement some "or" expressions, because "(or A B)"
1327 /// is equivalent to "not (and (not A) (not B))" and we can implement some
1328 /// negation operations:
1329 /// We can negate the results of a single comparison by inverting the flags
1330 /// used when the predicate fails and inverting the flags tested in the next
1331 /// instruction; We can also negate the results of the whole previous
1332 /// conditional compare sequence by inverting the flags tested in the next
1333 /// instruction. However there is no way to negate the result of a partial
1336 /// Therefore on encountering an "or" expression we can negate the subtree on
1337 /// one side and have to be able to push the negate to the leafs of the subtree
1338 /// on the other side (see also the comments in code). As complete example:
1339 /// "or (or (setCA (cmp A)) (setCB (cmp B)))
1340 /// (and (setCC (cmp C)) (setCD (cmp D)))"
1341 /// is transformed to
1342 /// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1343 /// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1344 /// and implemented as:
1346 /// ccmp D, inv(CD), CC
1347 /// ccmp A, CA, inv(CD)
1348 /// ccmp B, CB, inv(CA)
1349 /// check for CB flags
1350 /// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1351 /// by conditional compare sequences.
1354 /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1355 static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1356 ISD::CondCode CC, SDValue CCOp,
1357 AArch64CC::CondCode Predicate,
1358 AArch64CC::CondCode OutCC,
1359 const SDLoc &DL, SelectionDAG &DAG) {
1360 unsigned Opcode = 0;
1361 if (LHS.getValueType().isFloatingPoint()) {
1362 assert(LHS.getValueType() != MVT::f128);
1363 if (LHS.getValueType() == MVT::f16) {
1364 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
1365 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
1367 Opcode = AArch64ISD::FCCMP;
1368 } else if (RHS.getOpcode() == ISD::SUB) {
1369 SDValue SubOp0 = RHS.getOperand(0);
1370 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1371 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1372 Opcode = AArch64ISD::CCMN;
1373 RHS = RHS.getOperand(1);
1377 Opcode = AArch64ISD::CCMP;
1379 SDValue Condition = DAG.getConstant(Predicate, DL, MVT_CC);
1380 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1381 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1382 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1383 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1386 /// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1387 /// CanPushNegate is set to true if we can push a negate operation through
1388 /// the tree in a was that we are left with AND operations and negate operations
1389 /// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1390 /// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1391 /// brought into such a form.
1392 static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanNegate,
1393 unsigned Depth = 0) {
1394 if (!Val.hasOneUse())
1396 unsigned Opcode = Val->getOpcode();
1397 if (Opcode == ISD::SETCC) {
1398 if (Val->getOperand(0).getValueType() == MVT::f128)
1403 // Protect against exponential runtime and stack overflow.
1406 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1407 SDValue O0 = Val->getOperand(0);
1408 SDValue O1 = Val->getOperand(1);
1410 if (!isConjunctionDisjunctionTree(O0, CanNegateL, Depth+1))
1413 if (!isConjunctionDisjunctionTree(O1, CanNegateR, Depth+1))
1416 if (Opcode == ISD::OR) {
1417 // For an OR expression we need to be able to negate at least one side or
1418 // we cannot do the transformation at all.
1419 if (!CanNegateL && !CanNegateR)
1421 // We can however change a (not (or x y)) to (and (not x) (not y)) if we
1422 // can negate the x and y subtrees.
1423 CanNegate = CanNegateL && CanNegateR;
1425 // If the operands are OR expressions then we finally need to negate their
1426 // outputs, we can only do that for the operand with emitted last by
1427 // negating OutCC, not for both operands.
1428 bool NeedsNegOutL = O0->getOpcode() == ISD::OR;
1429 bool NeedsNegOutR = O1->getOpcode() == ISD::OR;
1430 if (NeedsNegOutL && NeedsNegOutR)
1432 // We cannot negate an AND operation (it would become an OR),
1440 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1441 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1442 /// Tries to transform the given i1 producing node @p Val to a series compare
1443 /// and conditional compare operations. @returns an NZCV flags producing node
1444 /// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1445 /// transformation was not possible.
1446 /// On recursive invocations @p PushNegate may be set to true to have negation
1447 /// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1448 /// for the comparisons in the current subtree; @p Depth limits the search
1449 /// depth to avoid stack overflow.
1450 static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
1451 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
1452 AArch64CC::CondCode Predicate) {
1453 // We're at a tree leaf, produce a conditional comparison operation.
1454 unsigned Opcode = Val->getOpcode();
1455 if (Opcode == ISD::SETCC) {
1456 SDValue LHS = Val->getOperand(0);
1457 SDValue RHS = Val->getOperand(1);
1458 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1459 bool isInteger = LHS.getValueType().isInteger();
1461 CC = getSetCCInverse(CC, isInteger);
1463 // Determine OutCC and handle FP special case.
1465 OutCC = changeIntCCToAArch64CC(CC);
1467 assert(LHS.getValueType().isFloatingPoint());
1468 AArch64CC::CondCode ExtraCC;
1469 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
1470 // Some floating point conditions can't be tested with a single condition
1471 // code. Construct an additional comparison in this case.
1472 if (ExtraCC != AArch64CC::AL) {
1474 if (!CCOp.getNode())
1475 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1477 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
1480 Predicate = ExtraCC;
1484 // Produce a normal comparison if we are first in the chain
1486 return emitComparison(LHS, RHS, CC, DL, DAG);
1487 // Otherwise produce a ccmp.
1488 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
1491 assert((Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) &&
1492 "Valid conjunction/disjunction tree");
1494 // Check if both sides can be transformed.
1495 SDValue LHS = Val->getOperand(0);
1496 SDValue RHS = Val->getOperand(1);
1498 // In case of an OR we need to negate our operands and the result.
1499 // (A v B) <=> not(not(A) ^ not(B))
1500 bool NegateOpsAndResult = Opcode == ISD::OR;
1501 // We can negate the results of all previous operations by inverting the
1502 // predicate flags giving us a free negation for one side. The other side
1503 // must be negatable by itself.
1504 if (NegateOpsAndResult) {
1505 // See which side we can negate.
1507 bool isValidL = isConjunctionDisjunctionTree(LHS, CanNegateL);
1508 assert(isValidL && "Valid conjunction/disjunction tree");
1513 bool isValidR = isConjunctionDisjunctionTree(RHS, CanNegateR);
1514 assert(isValidR && "Valid conjunction/disjunction tree");
1515 assert((CanNegateL || CanNegateR) && "Valid conjunction/disjunction tree");
1518 // Order the side which we cannot negate to RHS so we can emit it first.
1520 std::swap(LHS, RHS);
1522 bool NeedsNegOutL = LHS->getOpcode() == ISD::OR;
1523 assert((!NeedsNegOutL || RHS->getOpcode() != ISD::OR) &&
1524 "Valid conjunction/disjunction tree");
1525 // Order the side where we need to negate the output flags to RHS so it
1526 // gets emitted first.
1528 std::swap(LHS, RHS);
1531 // Emit RHS. If we want to negate the tree we only need to push a negate
1532 // through if we are already in a PushNegate case, otherwise we can negate
1533 // the "flags to test" afterwards.
1534 AArch64CC::CondCode RHSCC;
1535 SDValue CmpR = emitConjunctionDisjunctionTreeRec(DAG, RHS, RHSCC, Negate,
1537 if (NegateOpsAndResult && !Negate)
1538 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1539 // Emit LHS. We may need to negate it.
1540 SDValue CmpL = emitConjunctionDisjunctionTreeRec(DAG, LHS, OutCC,
1541 NegateOpsAndResult, CmpR,
1543 // If we transformed an OR to and AND then we have to negate the result
1544 // (or absorb the Negate parameter).
1545 if (NegateOpsAndResult && !Negate)
1546 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1550 /// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1551 /// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1552 /// \see emitConjunctionDisjunctionTreeRec().
1553 static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1554 AArch64CC::CondCode &OutCC) {
1556 if (!isConjunctionDisjunctionTree(Val, CanNegate))
1559 return emitConjunctionDisjunctionTreeRec(DAG, Val, OutCC, false, SDValue(),
1565 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1566 SDValue &AArch64cc, SelectionDAG &DAG,
1568 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1569 EVT VT = RHS.getValueType();
1570 uint64_t C = RHSC->getZExtValue();
1571 if (!isLegalArithImmed(C)) {
1572 // Constant does not fit, try adjusting it by one?
1578 if ((VT == MVT::i32 && C != 0x80000000 &&
1579 isLegalArithImmed((uint32_t)(C - 1))) ||
1580 (VT == MVT::i64 && C != 0x80000000ULL &&
1581 isLegalArithImmed(C - 1ULL))) {
1582 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1583 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1584 RHS = DAG.getConstant(C, dl, VT);
1589 if ((VT == MVT::i32 && C != 0 &&
1590 isLegalArithImmed((uint32_t)(C - 1))) ||
1591 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1592 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1593 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1594 RHS = DAG.getConstant(C, dl, VT);
1599 if ((VT == MVT::i32 && C != INT32_MAX &&
1600 isLegalArithImmed((uint32_t)(C + 1))) ||
1601 (VT == MVT::i64 && C != INT64_MAX &&
1602 isLegalArithImmed(C + 1ULL))) {
1603 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1604 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1605 RHS = DAG.getConstant(C, dl, VT);
1610 if ((VT == MVT::i32 && C != UINT32_MAX &&
1611 isLegalArithImmed((uint32_t)(C + 1))) ||
1612 (VT == MVT::i64 && C != UINT64_MAX &&
1613 isLegalArithImmed(C + 1ULL))) {
1614 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1615 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1616 RHS = DAG.getConstant(C, dl, VT);
1623 AArch64CC::CondCode AArch64CC;
1624 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1625 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1627 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1628 // For the i8 operand, the largest immediate is 255, so this can be easily
1629 // encoded in the compare instruction. For the i16 operand, however, the
1630 // largest immediate cannot be encoded in the compare.
1631 // Therefore, use a sign extending load and cmn to avoid materializing the
1632 // -1 constant. For example,
1634 // ldrh w0, [x0, #0]
1637 // ldrsh w0, [x0, #0]
1639 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1640 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1641 // ensure both the LHS and RHS are truly zero extended and to make sure the
1642 // transformation is profitable.
1643 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1644 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1645 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1646 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1647 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1648 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1650 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1651 DAG.getValueType(MVT::i16));
1652 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1653 RHS.getValueType()),
1655 AArch64CC = changeIntCCToAArch64CC(CC);
1659 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1660 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1661 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1662 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1668 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1669 AArch64CC = changeIntCCToAArch64CC(CC);
1671 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1675 static std::pair<SDValue, SDValue>
1676 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1677 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1678 "Unsupported value type");
1679 SDValue Value, Overflow;
1681 SDValue LHS = Op.getOperand(0);
1682 SDValue RHS = Op.getOperand(1);
1684 switch (Op.getOpcode()) {
1686 llvm_unreachable("Unknown overflow instruction!");
1688 Opc = AArch64ISD::ADDS;
1692 Opc = AArch64ISD::ADDS;
1696 Opc = AArch64ISD::SUBS;
1700 Opc = AArch64ISD::SUBS;
1703 // Multiply needs a little bit extra work.
1707 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1708 if (Op.getValueType() == MVT::i32) {
1709 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1710 // For a 32 bit multiply with overflow check we want the instruction
1711 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1712 // need to generate the following pattern:
1713 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1714 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1715 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1716 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1717 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1718 DAG.getConstant(0, DL, MVT::i64));
1719 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1720 // operation. We need to clear out the upper 32 bits, because we used a
1721 // widening multiply that wrote all 64 bits. In the end this should be a
1723 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1725 // The signed overflow check requires more than just a simple check for
1726 // any bit set in the upper 32 bits of the result. These bits could be
1727 // just the sign bits of a negative number. To perform the overflow
1728 // check we have to arithmetic shift right the 32nd bit of the result by
1729 // 31 bits. Then we compare the result to the upper 32 bits.
1730 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1731 DAG.getConstant(32, DL, MVT::i64));
1732 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1733 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1734 DAG.getConstant(31, DL, MVT::i64));
1735 // It is important that LowerBits is last, otherwise the arithmetic
1736 // shift will not be folded into the compare (SUBS).
1737 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1738 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1741 // The overflow check for unsigned multiply is easy. We only need to
1742 // check if any of the upper 32 bits are set. This can be done with a
1743 // CMP (shifted register). For that we need to generate the following
1745 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1746 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1747 DAG.getConstant(32, DL, MVT::i64));
1748 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1750 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1751 DAG.getConstant(0, DL, MVT::i64),
1752 UpperBits).getValue(1);
1756 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1757 // For the 64 bit multiply
1758 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1760 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1761 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1762 DAG.getConstant(63, DL, MVT::i64));
1763 // It is important that LowerBits is last, otherwise the arithmetic
1764 // shift will not be folded into the compare (SUBS).
1765 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1766 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1769 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1770 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1772 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1773 DAG.getConstant(0, DL, MVT::i64),
1774 UpperBits).getValue(1);
1781 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1783 // Emit the AArch64 operation with overflow check.
1784 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1785 Overflow = Value.getValue(1);
1787 return std::make_pair(Value, Overflow);
1790 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1791 RTLIB::Libcall Call) const {
1792 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1793 return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first;
1796 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1797 SDValue Sel = Op.getOperand(0);
1798 SDValue Other = Op.getOperand(1);
1800 // If neither operand is a SELECT_CC, give up.
1801 if (Sel.getOpcode() != ISD::SELECT_CC)
1802 std::swap(Sel, Other);
1803 if (Sel.getOpcode() != ISD::SELECT_CC)
1806 // The folding we want to perform is:
1807 // (xor x, (select_cc a, b, cc, 0, -1) )
1809 // (csel x, (xor x, -1), cc ...)
1811 // The latter will get matched to a CSINV instruction.
1813 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1814 SDValue LHS = Sel.getOperand(0);
1815 SDValue RHS = Sel.getOperand(1);
1816 SDValue TVal = Sel.getOperand(2);
1817 SDValue FVal = Sel.getOperand(3);
1820 // FIXME: This could be generalized to non-integer comparisons.
1821 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1824 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1825 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1827 // The values aren't constants, this isn't the pattern we're looking for.
1828 if (!CFVal || !CTVal)
1831 // We can commute the SELECT_CC by inverting the condition. This
1832 // might be needed to make this fit into a CSINV pattern.
1833 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1834 std::swap(TVal, FVal);
1835 std::swap(CTVal, CFVal);
1836 CC = ISD::getSetCCInverse(CC, true);
1839 // If the constants line up, perform the transform!
1840 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1842 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1845 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1846 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1848 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1855 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1856 EVT VT = Op.getValueType();
1858 // Let legalize expand this if it isn't a legal type yet.
1859 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1862 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1865 bool ExtraOp = false;
1866 switch (Op.getOpcode()) {
1868 llvm_unreachable("Invalid code");
1870 Opc = AArch64ISD::ADDS;
1873 Opc = AArch64ISD::SUBS;
1876 Opc = AArch64ISD::ADCS;
1880 Opc = AArch64ISD::SBCS;
1886 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1887 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1891 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1892 // Let legalize expand this if it isn't a legal type yet.
1893 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1897 AArch64CC::CondCode CC;
1898 // The actual operation that sets the overflow or carry flag.
1899 SDValue Value, Overflow;
1900 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1902 // We use 0 and 1 as false and true values.
1903 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1904 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1906 // We use an inverted condition, because the conditional select is inverted
1907 // too. This will allow it to be selected to a single instruction:
1908 // CSINC Wd, WZR, WZR, invert(cond).
1909 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1910 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1913 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1914 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1917 // Prefetch operands are:
1918 // 1: Address to prefetch
1920 // 3: int locality (0 = no locality ... 3 = extreme locality)
1921 // 4: bool isDataCache
1922 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1924 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1925 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1926 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1928 bool IsStream = !Locality;
1929 // When the locality number is set
1931 // The front-end should have filtered out the out-of-range values
1932 assert(Locality <= 3 && "Prefetch locality out-of-range");
1933 // The locality degree is the opposite of the cache speed.
1934 // Put the number the other way around.
1935 // The encoding starts at 0 for level 1
1936 Locality = 3 - Locality;
1939 // built the mask value encoding the expected behavior.
1940 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1941 (!IsData << 3) | // IsDataCache bit
1942 (Locality << 1) | // Cache level bits
1943 (unsigned)IsStream; // Stream bit
1944 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1945 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1948 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1949 SelectionDAG &DAG) const {
1950 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1953 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1955 return LowerF128Call(Op, DAG, LC);
1958 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1959 SelectionDAG &DAG) const {
1960 if (Op.getOperand(0).getValueType() != MVT::f128) {
1961 // It's legal except when f128 is involved
1966 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1968 // FP_ROUND node has a second operand indicating whether it is known to be
1969 // precise. That doesn't take part in the LibCall so we can't directly use
1971 SDValue SrcVal = Op.getOperand(0);
1972 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
1976 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1977 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1978 // Any additional optimization in this function should be recorded
1979 // in the cost tables.
1980 EVT InVT = Op.getOperand(0).getValueType();
1981 EVT VT = Op.getValueType();
1982 unsigned NumElts = InVT.getVectorNumElements();
1984 // f16 vectors are promoted to f32 before a conversion.
1985 if (InVT.getVectorElementType() == MVT::f16) {
1986 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
1989 Op.getOpcode(), dl, Op.getValueType(),
1990 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
1993 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1996 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1998 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
2001 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
2004 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
2005 VT.getVectorNumElements());
2006 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
2007 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
2010 // Type changing conversions are illegal.
2014 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
2015 SelectionDAG &DAG) const {
2016 if (Op.getOperand(0).getValueType().isVector())
2017 return LowerVectorFP_TO_INT(Op, DAG);
2019 // f16 conversions are promoted to f32.
2020 if (Op.getOperand(0).getValueType() == MVT::f16) {
2023 Op.getOpcode(), dl, Op.getValueType(),
2024 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
2027 if (Op.getOperand(0).getValueType() != MVT::f128) {
2028 // It's legal except when f128 is involved
2033 if (Op.getOpcode() == ISD::FP_TO_SINT)
2034 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2036 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2038 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2039 return makeLibCall(DAG, LC, Op.getValueType(), Ops, false, SDLoc(Op)).first;
2042 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2043 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
2044 // Any additional optimization in this function should be recorded
2045 // in the cost tables.
2046 EVT VT = Op.getValueType();
2048 SDValue In = Op.getOperand(0);
2049 EVT InVT = In.getValueType();
2051 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
2053 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
2054 InVT.getVectorNumElements());
2055 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
2056 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
2059 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
2061 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2062 EVT CastVT = VT.changeVectorElementTypeToInteger();
2063 In = DAG.getNode(CastOpc, dl, CastVT, In);
2064 return DAG.getNode(Op.getOpcode(), dl, VT, In);
2070 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
2071 SelectionDAG &DAG) const {
2072 if (Op.getValueType().isVector())
2073 return LowerVectorINT_TO_FP(Op, DAG);
2075 // f16 conversions are promoted to f32.
2076 if (Op.getValueType() == MVT::f16) {
2079 ISD::FP_ROUND, dl, MVT::f16,
2080 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
2081 DAG.getIntPtrConstant(0, dl));
2084 // i128 conversions are libcalls.
2085 if (Op.getOperand(0).getValueType() == MVT::i128)
2088 // Other conversions are legal, unless it's to the completely software-based
2090 if (Op.getValueType() != MVT::f128)
2094 if (Op.getOpcode() == ISD::SINT_TO_FP)
2095 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2097 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2099 return LowerF128Call(Op, DAG, LC);
2102 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
2103 SelectionDAG &DAG) const {
2104 // For iOS, we want to call an alternative entry point: __sincos_stret,
2105 // which returns the values in two S / D registers.
2107 SDValue Arg = Op.getOperand(0);
2108 EVT ArgVT = Arg.getValueType();
2109 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2116 Entry.isSExt = false;
2117 Entry.isZExt = false;
2118 Args.push_back(Entry);
2120 const char *LibcallName =
2121 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
2123 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
2125 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
2126 TargetLowering::CallLoweringInfo CLI(DAG);
2127 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2128 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args));
2130 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2131 return CallResult.first;
2134 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
2135 if (Op.getValueType() != MVT::f16)
2138 assert(Op.getOperand(0).getValueType() == MVT::i16);
2141 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
2142 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
2144 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
2145 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
2149 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
2150 if (OrigVT.getSizeInBits() >= 64)
2153 assert(OrigVT.isSimple() && "Expecting a simple value type");
2155 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
2156 switch (OrigSimpleTy) {
2157 default: llvm_unreachable("Unexpected Vector Type");
2166 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
2169 unsigned ExtOpcode) {
2170 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
2171 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
2172 // 64-bits we need to insert a new extension so that it will be 64-bits.
2173 assert(ExtTy.is128BitVector() && "Unexpected extension size");
2174 if (OrigTy.getSizeInBits() >= 64)
2177 // Must extend size to at least 64 bits to be used as an operand for VMULL.
2178 EVT NewVT = getExtensionTo64Bits(OrigTy);
2180 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2183 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2185 EVT VT = N->getValueType(0);
2187 if (N->getOpcode() != ISD::BUILD_VECTOR)
2190 for (const SDValue &Elt : N->op_values()) {
2191 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2192 unsigned EltSize = VT.getScalarSizeInBits();
2193 unsigned HalfSize = EltSize / 2;
2195 if (!isIntN(HalfSize, C->getSExtValue()))
2198 if (!isUIntN(HalfSize, C->getZExtValue()))
2209 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2210 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2211 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2212 N->getOperand(0)->getValueType(0),
2216 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2217 EVT VT = N->getValueType(0);
2219 unsigned EltSize = VT.getScalarSizeInBits() / 2;
2220 unsigned NumElts = VT.getVectorNumElements();
2221 MVT TruncVT = MVT::getIntegerVT(EltSize);
2222 SmallVector<SDValue, 8> Ops;
2223 for (unsigned i = 0; i != NumElts; ++i) {
2224 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2225 const APInt &CInt = C->getAPIntValue();
2226 // Element types smaller than 32 bits are not legal, so use i32 elements.
2227 // The values are implicitly truncated so sext vs. zext doesn't matter.
2228 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2230 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops);
2233 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2234 if (N->getOpcode() == ISD::SIGN_EXTEND)
2236 if (isExtendedBUILD_VECTOR(N, DAG, true))
2241 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2242 if (N->getOpcode() == ISD::ZERO_EXTEND)
2244 if (isExtendedBUILD_VECTOR(N, DAG, false))
2249 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2250 unsigned Opcode = N->getOpcode();
2251 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2252 SDNode *N0 = N->getOperand(0).getNode();
2253 SDNode *N1 = N->getOperand(1).getNode();
2254 return N0->hasOneUse() && N1->hasOneUse() &&
2255 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2260 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2261 unsigned Opcode = N->getOpcode();
2262 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2263 SDNode *N0 = N->getOperand(0).getNode();
2264 SDNode *N1 = N->getOperand(1).getNode();
2265 return N0->hasOneUse() && N1->hasOneUse() &&
2266 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2271 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2272 // Multiplications are only custom-lowered for 128-bit vectors so that
2273 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2274 EVT VT = Op.getValueType();
2275 assert(VT.is128BitVector() && VT.isInteger() &&
2276 "unexpected type for custom-lowering ISD::MUL");
2277 SDNode *N0 = Op.getOperand(0).getNode();
2278 SDNode *N1 = Op.getOperand(1).getNode();
2279 unsigned NewOpc = 0;
2281 bool isN0SExt = isSignExtended(N0, DAG);
2282 bool isN1SExt = isSignExtended(N1, DAG);
2283 if (isN0SExt && isN1SExt)
2284 NewOpc = AArch64ISD::SMULL;
2286 bool isN0ZExt = isZeroExtended(N0, DAG);
2287 bool isN1ZExt = isZeroExtended(N1, DAG);
2288 if (isN0ZExt && isN1ZExt)
2289 NewOpc = AArch64ISD::UMULL;
2290 else if (isN1SExt || isN1ZExt) {
2291 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2292 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2293 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2294 NewOpc = AArch64ISD::SMULL;
2296 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2297 NewOpc = AArch64ISD::UMULL;
2299 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2301 NewOpc = AArch64ISD::UMULL;
2307 if (VT == MVT::v2i64)
2308 // Fall through to expand this. It is not legal.
2311 // Other vector multiplications are legal.
2316 // Legalize to a S/UMULL instruction
2319 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2321 Op0 = skipExtensionForVectorMULL(N0, DAG);
2322 assert(Op0.getValueType().is64BitVector() &&
2323 Op1.getValueType().is64BitVector() &&
2324 "unexpected types for extended operands to VMULL");
2325 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2327 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2328 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2329 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2330 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2331 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2332 EVT Op1VT = Op1.getValueType();
2333 return DAG.getNode(N0->getOpcode(), DL, VT,
2334 DAG.getNode(NewOpc, DL, VT,
2335 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2336 DAG.getNode(NewOpc, DL, VT,
2337 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2340 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2341 SelectionDAG &DAG) const {
2342 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2345 default: return SDValue(); // Don't custom lower most intrinsics.
2346 case Intrinsic::thread_pointer: {
2347 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2348 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2350 case Intrinsic::aarch64_neon_smax:
2351 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
2352 Op.getOperand(1), Op.getOperand(2));
2353 case Intrinsic::aarch64_neon_umax:
2354 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
2355 Op.getOperand(1), Op.getOperand(2));
2356 case Intrinsic::aarch64_neon_smin:
2357 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
2358 Op.getOperand(1), Op.getOperand(2));
2359 case Intrinsic::aarch64_neon_umin:
2360 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(),
2361 Op.getOperand(1), Op.getOperand(2));
2365 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2366 SelectionDAG &DAG) const {
2367 switch (Op.getOpcode()) {
2369 llvm_unreachable("unimplemented operand");
2372 return LowerBITCAST(Op, DAG);
2373 case ISD::GlobalAddress:
2374 return LowerGlobalAddress(Op, DAG);
2375 case ISD::GlobalTLSAddress:
2376 return LowerGlobalTLSAddress(Op, DAG);
2378 return LowerSETCC(Op, DAG);
2380 return LowerBR_CC(Op, DAG);
2382 return LowerSELECT(Op, DAG);
2383 case ISD::SELECT_CC:
2384 return LowerSELECT_CC(Op, DAG);
2385 case ISD::JumpTable:
2386 return LowerJumpTable(Op, DAG);
2387 case ISD::ConstantPool:
2388 return LowerConstantPool(Op, DAG);
2389 case ISD::BlockAddress:
2390 return LowerBlockAddress(Op, DAG);
2392 return LowerVASTART(Op, DAG);
2394 return LowerVACOPY(Op, DAG);
2396 return LowerVAARG(Op, DAG);
2401 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2408 return LowerXALUO(Op, DAG);
2410 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2412 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2414 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2416 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2418 return LowerFP_ROUND(Op, DAG);
2419 case ISD::FP_EXTEND:
2420 return LowerFP_EXTEND(Op, DAG);
2421 case ISD::FRAMEADDR:
2422 return LowerFRAMEADDR(Op, DAG);
2423 case ISD::RETURNADDR:
2424 return LowerRETURNADDR(Op, DAG);
2425 case ISD::INSERT_VECTOR_ELT:
2426 return LowerINSERT_VECTOR_ELT(Op, DAG);
2427 case ISD::EXTRACT_VECTOR_ELT:
2428 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2429 case ISD::BUILD_VECTOR:
2430 return LowerBUILD_VECTOR(Op, DAG);
2431 case ISD::VECTOR_SHUFFLE:
2432 return LowerVECTOR_SHUFFLE(Op, DAG);
2433 case ISD::EXTRACT_SUBVECTOR:
2434 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2438 return LowerVectorSRA_SRL_SHL(Op, DAG);
2439 case ISD::SHL_PARTS:
2440 return LowerShiftLeftParts(Op, DAG);
2441 case ISD::SRL_PARTS:
2442 case ISD::SRA_PARTS:
2443 return LowerShiftRightParts(Op, DAG);
2445 return LowerCTPOP(Op, DAG);
2446 case ISD::FCOPYSIGN:
2447 return LowerFCOPYSIGN(Op, DAG);
2449 return LowerVectorAND(Op, DAG);
2451 return LowerVectorOR(Op, DAG);
2453 return LowerXOR(Op, DAG);
2455 return LowerPREFETCH(Op, DAG);
2456 case ISD::SINT_TO_FP:
2457 case ISD::UINT_TO_FP:
2458 return LowerINT_TO_FP(Op, DAG);
2459 case ISD::FP_TO_SINT:
2460 case ISD::FP_TO_UINT:
2461 return LowerFP_TO_INT(Op, DAG);
2463 return LowerFSINCOS(Op, DAG);
2465 return LowerMUL(Op, DAG);
2466 case ISD::INTRINSIC_WO_CHAIN:
2467 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2471 //===----------------------------------------------------------------------===//
2472 // Calling Convention Implementation
2473 //===----------------------------------------------------------------------===//
2475 #include "AArch64GenCallingConv.inc"
2477 /// Selects the correct CCAssignFn for a given CallingConvention value.
2478 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2479 bool IsVarArg) const {
2482 llvm_unreachable("Unsupported calling convention.");
2483 case CallingConv::WebKit_JS:
2484 return CC_AArch64_WebKit_JS;
2485 case CallingConv::GHC:
2486 return CC_AArch64_GHC;
2487 case CallingConv::C:
2488 case CallingConv::Fast:
2489 case CallingConv::PreserveMost:
2490 case CallingConv::CXX_FAST_TLS:
2491 case CallingConv::Swift:
2492 if (!Subtarget->isTargetDarwin())
2493 return CC_AArch64_AAPCS;
2494 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2499 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
2500 return CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
2501 : RetCC_AArch64_AAPCS;
2504 SDValue AArch64TargetLowering::LowerFormalArguments(
2505 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2506 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2507 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2508 MachineFunction &MF = DAG.getMachineFunction();
2509 MachineFrameInfo &MFI = MF.getFrameInfo();
2511 // Assign locations to all of the incoming arguments.
2512 SmallVector<CCValAssign, 16> ArgLocs;
2513 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2516 // At this point, Ins[].VT may already be promoted to i32. To correctly
2517 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2518 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2519 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2520 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2522 unsigned NumArgs = Ins.size();
2523 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2524 unsigned CurArgIdx = 0;
2525 for (unsigned i = 0; i != NumArgs; ++i) {
2526 MVT ValVT = Ins[i].VT;
2527 if (Ins[i].isOrigArg()) {
2528 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2529 CurArgIdx = Ins[i].getOrigArgIndex();
2531 // Get type of the original argument.
2532 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2533 /*AllowUnknown*/ true);
2534 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2535 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2536 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2538 else if (ActualMVT == MVT::i16)
2541 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2543 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2544 assert(!Res && "Call operand has unhandled type");
2547 assert(ArgLocs.size() == Ins.size());
2548 SmallVector<SDValue, 16> ArgValues;
2549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2550 CCValAssign &VA = ArgLocs[i];
2552 if (Ins[i].Flags.isByVal()) {
2553 // Byval is used for HFAs in the PCS, but the system should work in a
2554 // non-compliant manner for larger structs.
2555 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2556 int Size = Ins[i].Flags.getByValSize();
2557 unsigned NumRegs = (Size + 7) / 8;
2559 // FIXME: This works on big-endian for composite byvals, which are the common
2560 // case. It should also work for fundamental types too.
2562 MFI.CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2563 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2564 InVals.push_back(FrameIdxN);
2569 if (VA.isRegLoc()) {
2570 // Arguments stored in registers.
2571 EVT RegVT = VA.getLocVT();
2574 const TargetRegisterClass *RC;
2576 if (RegVT == MVT::i32)
2577 RC = &AArch64::GPR32RegClass;
2578 else if (RegVT == MVT::i64)
2579 RC = &AArch64::GPR64RegClass;
2580 else if (RegVT == MVT::f16)
2581 RC = &AArch64::FPR16RegClass;
2582 else if (RegVT == MVT::f32)
2583 RC = &AArch64::FPR32RegClass;
2584 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2585 RC = &AArch64::FPR64RegClass;
2586 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2587 RC = &AArch64::FPR128RegClass;
2589 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2591 // Transform the arguments in physical registers into virtual ones.
2592 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2593 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2595 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2596 // to 64 bits. Insert an assert[sz]ext to capture this, then
2597 // truncate to the right size.
2598 switch (VA.getLocInfo()) {
2600 llvm_unreachable("Unknown loc info!");
2601 case CCValAssign::Full:
2603 case CCValAssign::BCvt:
2604 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2606 case CCValAssign::AExt:
2607 case CCValAssign::SExt:
2608 case CCValAssign::ZExt:
2609 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2610 // nodes after our lowering.
2611 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2615 InVals.push_back(ArgValue);
2617 } else { // VA.isRegLoc()
2618 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2619 unsigned ArgOffset = VA.getLocMemOffset();
2620 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2622 uint32_t BEAlign = 0;
2623 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2624 !Ins[i].Flags.isInConsecutiveRegs())
2625 BEAlign = 8 - ArgSize;
2627 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2629 // Create load nodes to retrieve arguments from the stack.
2630 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2633 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2634 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2635 MVT MemVT = VA.getValVT();
2637 switch (VA.getLocInfo()) {
2640 case CCValAssign::BCvt:
2641 MemVT = VA.getLocVT();
2643 case CCValAssign::SExt:
2644 ExtType = ISD::SEXTLOAD;
2646 case CCValAssign::ZExt:
2647 ExtType = ISD::ZEXTLOAD;
2649 case CCValAssign::AExt:
2650 ExtType = ISD::EXTLOAD;
2654 ArgValue = DAG.getExtLoad(
2655 ExtType, DL, VA.getLocVT(), Chain, FIN,
2656 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
2659 InVals.push_back(ArgValue);
2664 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2666 if (!Subtarget->isTargetDarwin()) {
2667 // The AAPCS variadic function ABI is identical to the non-variadic
2668 // one. As a result there may be more arguments in registers and we should
2669 // save them for future reference.
2670 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2673 // This will point to the next argument passed via stack.
2674 unsigned StackOffset = CCInfo.getNextStackOffset();
2675 // We currently pass all varargs at 8-byte alignment.
2676 StackOffset = ((StackOffset + 7) & ~7);
2677 FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
2680 unsigned StackArgSize = CCInfo.getNextStackOffset();
2681 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2682 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2683 // This is a non-standard ABI so by fiat I say we're allowed to make full
2684 // use of the stack area to be popped, which must be aligned to 16 bytes in
2686 StackArgSize = alignTo(StackArgSize, 16);
2688 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2689 // a multiple of 16.
2690 FuncInfo->setArgumentStackToRestore(StackArgSize);
2692 // This realignment carries over to the available bytes below. Our own
2693 // callers will guarantee the space is free by giving an aligned value to
2696 // Even if we're not expected to free up the space, it's useful to know how
2697 // much is there while considering tail calls (because we can reuse it).
2698 FuncInfo->setBytesInStackArgArea(StackArgSize);
2703 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2706 SDValue &Chain) const {
2707 MachineFunction &MF = DAG.getMachineFunction();
2708 MachineFrameInfo &MFI = MF.getFrameInfo();
2709 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2710 auto PtrVT = getPointerTy(DAG.getDataLayout());
2712 SmallVector<SDValue, 8> MemOps;
2714 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2715 AArch64::X3, AArch64::X4, AArch64::X5,
2716 AArch64::X6, AArch64::X7 };
2717 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2718 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2720 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2722 if (GPRSaveSize != 0) {
2723 GPRIdx = MFI.CreateStackObject(GPRSaveSize, 8, false);
2725 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2727 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2728 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2729 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2730 SDValue Store = DAG.getStore(
2731 Val.getValue(1), DL, Val, FIN,
2732 MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 8));
2733 MemOps.push_back(Store);
2735 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2738 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2739 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2741 if (Subtarget->hasFPARMv8()) {
2742 static const MCPhysReg FPRArgRegs[] = {
2743 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2744 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2745 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2746 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2748 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2750 if (FPRSaveSize != 0) {
2751 FPRIdx = MFI.CreateStackObject(FPRSaveSize, 16, false);
2753 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2755 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2756 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2757 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2759 SDValue Store = DAG.getStore(
2760 Val.getValue(1), DL, Val, FIN,
2761 MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 16));
2762 MemOps.push_back(Store);
2763 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2764 DAG.getConstant(16, DL, PtrVT));
2767 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2768 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2771 if (!MemOps.empty()) {
2772 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2776 /// LowerCallResult - Lower the result values of a call into the
2777 /// appropriate copies out of appropriate physical registers.
2778 SDValue AArch64TargetLowering::LowerCallResult(
2779 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2780 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2781 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2782 SDValue ThisVal) const {
2783 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2784 ? RetCC_AArch64_WebKit_JS
2785 : RetCC_AArch64_AAPCS;
2786 // Assign locations to each value returned by this call.
2787 SmallVector<CCValAssign, 16> RVLocs;
2788 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2790 CCInfo.AnalyzeCallResult(Ins, RetCC);
2792 // Copy all of the result registers out of their specified physreg.
2793 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2794 CCValAssign VA = RVLocs[i];
2796 // Pass 'this' value directly from the argument to return value, to avoid
2797 // reg unit interference
2798 if (i == 0 && isThisReturn) {
2799 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2800 "unexpected return calling convention register assignment");
2801 InVals.push_back(ThisVal);
2806 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2807 Chain = Val.getValue(1);
2808 InFlag = Val.getValue(2);
2810 switch (VA.getLocInfo()) {
2812 llvm_unreachable("Unknown loc info!");
2813 case CCValAssign::Full:
2815 case CCValAssign::BCvt:
2816 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2820 InVals.push_back(Val);
2826 /// Return true if the calling convention is one that we can guarantee TCO for.
2827 static bool canGuaranteeTCO(CallingConv::ID CC) {
2828 return CC == CallingConv::Fast;
2831 /// Return true if we might ever do TCO for calls with this calling convention.
2832 static bool mayTailCallThisCC(CallingConv::ID CC) {
2834 case CallingConv::C:
2835 case CallingConv::PreserveMost:
2836 case CallingConv::Swift:
2839 return canGuaranteeTCO(CC);
2843 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2844 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2845 const SmallVectorImpl<ISD::OutputArg> &Outs,
2846 const SmallVectorImpl<SDValue> &OutVals,
2847 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2848 if (!mayTailCallThisCC(CalleeCC))
2851 MachineFunction &MF = DAG.getMachineFunction();
2852 const Function *CallerF = MF.getFunction();
2853 CallingConv::ID CallerCC = CallerF->getCallingConv();
2854 bool CCMatch = CallerCC == CalleeCC;
2856 // Byval parameters hand the function a pointer directly into the stack area
2857 // we want to reuse during a tail call. Working around this *is* possible (see
2858 // X86) but less efficient and uglier in LowerCall.
2859 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2860 e = CallerF->arg_end();
2862 if (i->hasByValAttr())
2865 if (getTargetMachine().Options.GuaranteedTailCallOpt)
2866 return canGuaranteeTCO(CalleeCC) && CCMatch;
2868 // Externally-defined functions with weak linkage should not be
2869 // tail-called on AArch64 when the OS does not support dynamic
2870 // pre-emption of symbols, as the AAELF spec requires normal calls
2871 // to undefined weak functions to be replaced with a NOP or jump to the
2872 // next instruction. The behaviour of branch instructions in this
2873 // situation (as used for tail calls) is implementation-defined, so we
2874 // cannot rely on the linker replacing the tail call with a return.
2875 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2876 const GlobalValue *GV = G->getGlobal();
2877 const Triple &TT = getTargetMachine().getTargetTriple();
2878 if (GV->hasExternalWeakLinkage() &&
2879 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2883 // Now we search for cases where we can use a tail call without changing the
2884 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2887 // I want anyone implementing a new calling convention to think long and hard
2888 // about this assert.
2889 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2890 "Unexpected variadic calling convention");
2892 LLVMContext &C = *DAG.getContext();
2893 if (isVarArg && !Outs.empty()) {
2894 // At least two cases here: if caller is fastcc then we can't have any
2895 // memory arguments (we'd be expected to clean up the stack afterwards). If
2896 // caller is C then we could potentially use its argument area.
2898 // FIXME: for now we take the most conservative of these in both cases:
2899 // disallow all variadic memory operands.
2900 SmallVector<CCValAssign, 16> ArgLocs;
2901 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2903 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2904 for (const CCValAssign &ArgLoc : ArgLocs)
2905 if (!ArgLoc.isRegLoc())
2909 // Check that the call results are passed in the same way.
2910 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2911 CCAssignFnForCall(CalleeCC, isVarArg),
2912 CCAssignFnForCall(CallerCC, isVarArg)))
2914 // The callee has to preserve all registers the caller needs to preserve.
2915 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2916 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2918 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2919 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2923 // Nothing more to check if the callee is taking no arguments
2927 SmallVector<CCValAssign, 16> ArgLocs;
2928 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2930 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2932 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2934 // If the stack arguments for this call do not fit into our own save area then
2935 // the call cannot be made tail.
2936 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2939 const MachineRegisterInfo &MRI = MF.getRegInfo();
2940 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2946 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2948 MachineFrameInfo &MFI,
2949 int ClobberedFI) const {
2950 SmallVector<SDValue, 8> ArgChains;
2951 int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
2952 int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
2954 // Include the original chain at the beginning of the list. When this is
2955 // used by target LowerCall hooks, this helps legalize find the
2956 // CALLSEQ_BEGIN node.
2957 ArgChains.push_back(Chain);
2959 // Add a chain value for each stack argument corresponding
2960 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2961 UE = DAG.getEntryNode().getNode()->use_end();
2963 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2964 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2965 if (FI->getIndex() < 0) {
2966 int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
2967 int64_t InLastByte = InFirstByte;
2968 InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
2970 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2971 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2972 ArgChains.push_back(SDValue(L, 1));
2975 // Build a tokenfactor for all the chains.
2976 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2979 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2980 bool TailCallOpt) const {
2981 return CallCC == CallingConv::Fast && TailCallOpt;
2984 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2985 /// and add input and output parameter nodes.
2987 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2988 SmallVectorImpl<SDValue> &InVals) const {
2989 SelectionDAG &DAG = CLI.DAG;
2991 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2992 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2993 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2994 SDValue Chain = CLI.Chain;
2995 SDValue Callee = CLI.Callee;
2996 bool &IsTailCall = CLI.IsTailCall;
2997 CallingConv::ID CallConv = CLI.CallConv;
2998 bool IsVarArg = CLI.IsVarArg;
3000 MachineFunction &MF = DAG.getMachineFunction();
3001 bool IsThisReturn = false;
3003 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3004 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
3005 bool IsSibCall = false;
3008 // Check if it's really possible to do a tail call.
3009 IsTailCall = isEligibleForTailCallOptimization(
3010 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
3011 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
3012 report_fatal_error("failed to perform tail call elimination on a call "
3013 "site marked musttail");
3015 // A sibling call is one where we're under the usual C ABI and not planning
3016 // to change that but can still do a tail call:
3017 if (!TailCallOpt && IsTailCall)
3024 // Analyze operands of the call, assigning locations to each operand.
3025 SmallVector<CCValAssign, 16> ArgLocs;
3026 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3030 // Handle fixed and variable vector arguments differently.
3031 // Variable vector arguments always go into memory.
3032 unsigned NumArgs = Outs.size();
3034 for (unsigned i = 0; i != NumArgs; ++i) {
3035 MVT ArgVT = Outs[i].VT;
3036 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3037 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
3038 /*IsVarArg=*/ !Outs[i].IsFixed);
3039 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3040 assert(!Res && "Call operand has unhandled type");
3044 // At this point, Outs[].VT may already be promoted to i32. To correctly
3045 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
3046 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
3047 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
3048 // we use a special version of AnalyzeCallOperands to pass in ValVT and
3050 unsigned NumArgs = Outs.size();
3051 for (unsigned i = 0; i != NumArgs; ++i) {
3052 MVT ValVT = Outs[i].VT;
3053 // Get type of the original argument.
3054 EVT ActualVT = getValueType(DAG.getDataLayout(),
3055 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
3056 /*AllowUnknown*/ true);
3057 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
3058 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3059 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
3060 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3062 else if (ActualMVT == MVT::i16)
3065 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
3066 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
3067 assert(!Res && "Call operand has unhandled type");
3072 // Get a count of how many bytes are to be pushed on the stack.
3073 unsigned NumBytes = CCInfo.getNextStackOffset();
3076 // Since we're not changing the ABI to make this a tail call, the memory
3077 // operands are already available in the caller's incoming argument space.
3081 // FPDiff is the byte offset of the call's argument area from the callee's.
3082 // Stores to callee stack arguments will be placed in FixedStackSlots offset
3083 // by this amount for a tail call. In a sibling call it must be 0 because the
3084 // caller will deallocate the entire stack and the callee still expects its
3085 // arguments to begin at SP+0. Completely unused for non-tail calls.
3088 if (IsTailCall && !IsSibCall) {
3089 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
3091 // Since callee will pop argument stack as a tail call, we must keep the
3092 // popped size 16-byte aligned.
3093 NumBytes = alignTo(NumBytes, 16);
3095 // FPDiff will be negative if this tail call requires more space than we
3096 // would automatically have in our incoming argument space. Positive if we
3097 // can actually shrink the stack.
3098 FPDiff = NumReusableBytes - NumBytes;
3100 // The stack pointer must be 16-byte aligned at all times it's used for a
3101 // memory operation, which in practice means at *all* times and in
3102 // particular across call boundaries. Therefore our own arguments started at
3103 // a 16-byte aligned SP and the delta applied for the tail call should
3104 // satisfy the same constraint.
3105 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
3108 // Adjust the stack pointer for the new arguments...
3109 // These operations are automatically eliminated by the prolog/epilog pass
3111 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
3115 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
3116 getPointerTy(DAG.getDataLayout()));
3118 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3119 SmallVector<SDValue, 8> MemOpChains;
3120 auto PtrVT = getPointerTy(DAG.getDataLayout());
3122 // Walk the register/memloc assignments, inserting copies/loads.
3123 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
3124 ++i, ++realArgIdx) {
3125 CCValAssign &VA = ArgLocs[i];
3126 SDValue Arg = OutVals[realArgIdx];
3127 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3129 // Promote the value if needed.
3130 switch (VA.getLocInfo()) {
3132 llvm_unreachable("Unknown loc info!");
3133 case CCValAssign::Full:
3135 case CCValAssign::SExt:
3136 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3138 case CCValAssign::ZExt:
3139 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3141 case CCValAssign::AExt:
3142 if (Outs[realArgIdx].ArgVT == MVT::i1) {
3143 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
3144 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3145 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
3147 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3149 case CCValAssign::BCvt:
3150 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3152 case CCValAssign::FPExt:
3153 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3157 if (VA.isRegLoc()) {
3158 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
3159 assert(VA.getLocVT() == MVT::i64 &&
3160 "unexpected calling convention register assignment");
3161 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
3162 "unexpected use of 'returned'");
3163 IsThisReturn = true;
3165 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3167 assert(VA.isMemLoc());
3170 MachinePointerInfo DstInfo;
3172 // FIXME: This works on big-endian for composite byvals, which are the
3173 // common case. It should also work for fundamental types too.
3174 uint32_t BEAlign = 0;
3175 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
3176 : VA.getValVT().getSizeInBits();
3177 OpSize = (OpSize + 7) / 8;
3178 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
3179 !Flags.isInConsecutiveRegs()) {
3181 BEAlign = 8 - OpSize;
3183 unsigned LocMemOffset = VA.getLocMemOffset();
3184 int32_t Offset = LocMemOffset + BEAlign;
3185 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3186 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3189 Offset = Offset + FPDiff;
3190 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
3192 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3194 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
3196 // Make sure any stack arguments overlapping with where we're storing
3197 // are loaded before this eventual operation. Otherwise they'll be
3199 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3201 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3203 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3204 DstInfo = MachinePointerInfo::getStack(DAG.getMachineFunction(),
3208 if (Outs[i].Flags.isByVal()) {
3210 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3211 SDValue Cpy = DAG.getMemcpy(
3212 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3213 /*isVol = */ false, /*AlwaysInline = */ false,
3214 /*isTailCall = */ false,
3215 DstInfo, MachinePointerInfo());
3217 MemOpChains.push_back(Cpy);
3219 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3220 // promoted to a legal register type i32, we should truncate Arg back to
3222 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3223 VA.getValVT() == MVT::i16)
3224 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3226 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo);
3227 MemOpChains.push_back(Store);
3232 if (!MemOpChains.empty())
3233 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3235 // Build a sequence of copy-to-reg nodes chained together with token chain
3236 // and flag operands which copy the outgoing args into the appropriate regs.
3238 for (auto &RegToPass : RegsToPass) {
3239 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3240 RegToPass.second, InFlag);
3241 InFlag = Chain.getValue(1);
3244 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3245 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3246 // node so that legalize doesn't hack it.
3247 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3248 Subtarget->isTargetMachO()) {
3249 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3250 const GlobalValue *GV = G->getGlobal();
3251 bool InternalLinkage = GV->hasInternalLinkage();
3252 if (InternalLinkage)
3253 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3256 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3257 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3259 } else if (ExternalSymbolSDNode *S =
3260 dyn_cast<ExternalSymbolSDNode>(Callee)) {
3261 const char *Sym = S->getSymbol();
3262 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3263 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3265 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3266 const GlobalValue *GV = G->getGlobal();
3267 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3268 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3269 const char *Sym = S->getSymbol();
3270 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3273 // We don't usually want to end the call-sequence here because we would tidy
3274 // the frame up *after* the call, however in the ABI-changing tail-call case
3275 // we've carefully laid out the parameters so that when sp is reset they'll be
3276 // in the correct location.
3277 if (IsTailCall && !IsSibCall) {
3278 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3279 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3280 InFlag = Chain.getValue(1);
3283 std::vector<SDValue> Ops;
3284 Ops.push_back(Chain);
3285 Ops.push_back(Callee);
3288 // Each tail call may have to adjust the stack by a different amount, so
3289 // this information must travel along with the operation for eventual
3290 // consumption by emitEpilogue.
3291 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3294 // Add argument registers to the end of the list so that they are known live
3296 for (auto &RegToPass : RegsToPass)
3297 Ops.push_back(DAG.getRegister(RegToPass.first,
3298 RegToPass.second.getValueType()));
3300 // Add a register mask operand representing the call-preserved registers.
3301 const uint32_t *Mask;
3302 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3304 // For 'this' returns, use the X0-preserving mask if applicable
3305 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3307 IsThisReturn = false;
3308 Mask = TRI->getCallPreservedMask(MF, CallConv);
3311 Mask = TRI->getCallPreservedMask(MF, CallConv);
3313 assert(Mask && "Missing call preserved mask for calling convention");
3314 Ops.push_back(DAG.getRegisterMask(Mask));
3316 if (InFlag.getNode())
3317 Ops.push_back(InFlag);
3319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3321 // If we're doing a tall call, use a TC_RETURN here rather than an
3322 // actual call instruction.
3324 MF.getFrameInfo().setHasTailCall();
3325 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3328 // Returns a chain and a flag for retval copy to use.
3329 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3330 InFlag = Chain.getValue(1);
3332 uint64_t CalleePopBytes =
3333 DoesCalleeRestoreStack(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : 0;
3335 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3336 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3339 InFlag = Chain.getValue(1);
3341 // Handle result values, copying them out of physregs into vregs that we
3343 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3344 InVals, IsThisReturn,
3345 IsThisReturn ? OutVals[0] : SDValue());
3348 bool AArch64TargetLowering::CanLowerReturn(
3349 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3350 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3351 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3352 ? RetCC_AArch64_WebKit_JS
3353 : RetCC_AArch64_AAPCS;
3354 SmallVector<CCValAssign, 16> RVLocs;
3355 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3356 return CCInfo.CheckReturn(Outs, RetCC);
3360 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3362 const SmallVectorImpl<ISD::OutputArg> &Outs,
3363 const SmallVectorImpl<SDValue> &OutVals,
3364 const SDLoc &DL, SelectionDAG &DAG) const {
3365 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3366 ? RetCC_AArch64_WebKit_JS
3367 : RetCC_AArch64_AAPCS;
3368 SmallVector<CCValAssign, 16> RVLocs;
3369 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3371 CCInfo.AnalyzeReturn(Outs, RetCC);
3373 // Copy the result values into the output registers.
3375 SmallVector<SDValue, 4> RetOps(1, Chain);
3376 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3377 ++i, ++realRVLocIdx) {
3378 CCValAssign &VA = RVLocs[i];
3379 assert(VA.isRegLoc() && "Can only return in registers!");
3380 SDValue Arg = OutVals[realRVLocIdx];
3382 switch (VA.getLocInfo()) {
3384 llvm_unreachable("Unknown loc info!");
3385 case CCValAssign::Full:
3386 if (Outs[i].ArgVT == MVT::i1) {
3387 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3388 // value. This is strictly redundant on Darwin (which uses "zeroext
3389 // i1"), but will be optimised out before ISel.
3390 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3391 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3394 case CCValAssign::BCvt:
3395 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3399 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3400 Flag = Chain.getValue(1);
3401 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3403 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3404 const MCPhysReg *I =
3405 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3408 if (AArch64::GPR64RegClass.contains(*I))
3409 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
3410 else if (AArch64::FPR64RegClass.contains(*I))
3411 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3413 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
3417 RetOps[0] = Chain; // Update chain.
3419 // Add the flag if we have it.
3421 RetOps.push_back(Flag);
3423 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3426 //===----------------------------------------------------------------------===//
3427 // Other Lowering Code
3428 //===----------------------------------------------------------------------===//
3430 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3431 SelectionDAG &DAG) const {
3432 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3434 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3435 const GlobalValue *GV = GN->getGlobal();
3436 unsigned char OpFlags =
3437 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3439 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
3440 "unexpected offset in global node");
3442 // This also catched the large code model case for Darwin.
3443 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3444 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
3445 // FIXME: Once remat is capable of dealing with instructions with register
3446 // operands, expand this into two nodes instead of using a wrapper node.
3447 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3450 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3451 const unsigned char MO_NC = AArch64II::MO_NC;
3453 AArch64ISD::WrapperLarge, DL, PtrVT,
3454 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3455 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3456 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3457 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3459 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3460 // the only correct model on Darwin.
3461 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3462 OpFlags | AArch64II::MO_PAGE);
3463 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3464 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3466 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3467 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3471 /// \brief Convert a TLS address reference into the correct sequence of loads
3472 /// and calls to compute the variable's address (for Darwin, currently) and
3473 /// return an SDValue containing the final node.
3475 /// Darwin only has one TLS scheme which must be capable of dealing with the
3476 /// fully general situation, in the worst case. This means:
3477 /// + "extern __thread" declaration.
3478 /// + Defined in a possibly unknown dynamic library.
3480 /// The general system is that each __thread variable has a [3 x i64] descriptor
3481 /// which contains information used by the runtime to calculate the address. The
3482 /// only part of this the compiler needs to know about is the first xword, which
3483 /// contains a function pointer that must be called with the address of the
3484 /// entire descriptor in "x0".
3486 /// Since this descriptor may be in a different unit, in general even the
3487 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3489 /// adrp x0, _var@TLVPPAGE
3490 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3491 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3492 /// ; the function pointer
3493 /// blr x1 ; Uses descriptor address in x0
3494 /// ; Address of _var is now in x0.
3496 /// If the address of _var's descriptor *is* known to the linker, then it can
3497 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3498 /// a slight efficiency gain.
3500 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3501 SelectionDAG &DAG) const {
3502 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3505 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3506 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3509 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3510 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3512 // The first entry in the descriptor is a function pointer that we must call
3513 // to obtain the address of the variable.
3514 SDValue Chain = DAG.getEntryNode();
3515 SDValue FuncTLVGet = DAG.getLoad(
3516 MVT::i64, DL, Chain, DescAddr,
3517 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
3518 /* Alignment = */ 8,
3519 MachineMemOperand::MONonTemporal | MachineMemOperand::MOInvariant |
3520 MachineMemOperand::MODereferenceable);
3521 Chain = FuncTLVGet.getValue(1);
3523 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3524 MFI.setAdjustsStack(true);
3526 // TLS calls preserve all registers except those that absolutely must be
3527 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3529 const uint32_t *Mask =
3530 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3532 // Finally, we can make the call. This is just a degenerate version of a
3533 // normal AArch64 call node: x0 takes the address of the descriptor, and
3534 // returns the address of the variable in this thread.
3535 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3537 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3538 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3539 DAG.getRegisterMask(Mask), Chain.getValue(1));
3540 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3543 /// When accessing thread-local variables under either the general-dynamic or
3544 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3545 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3546 /// is a function pointer to carry out the resolution.
3548 /// The sequence is:
3549 /// adrp x0, :tlsdesc:var
3550 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3551 /// add x0, x0, #:tlsdesc_lo12:var
3552 /// .tlsdesccall var
3554 /// (TPIDR_EL0 offset now in x0)
3556 /// The above sequence must be produced unscheduled, to enable the linker to
3557 /// optimize/relax this sequence.
3558 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3559 /// above sequence, and expanded really late in the compilation flow, to ensure
3560 /// the sequence is produced as per above.
3561 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
3563 SelectionDAG &DAG) const {
3564 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3566 SDValue Chain = DAG.getEntryNode();
3567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3570 DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr});
3571 SDValue Glue = Chain.getValue(1);
3573 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3577 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3578 SelectionDAG &DAG) const {
3579 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3580 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3581 "ELF TLS only supported in small memory model");
3582 // Different choices can be made for the maximum size of the TLS area for a
3583 // module. For the small address model, the default TLS size is 16MiB and the
3584 // maximum TLS size is 4GiB.
3585 // FIXME: add -mtls-size command line option and make it control the 16MiB
3586 // vs. 4GiB code sequence generation.
3587 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3589 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3591 if (DAG.getTarget().Options.EmulatedTLS)
3592 return LowerToTLSEmulatedModel(GA, DAG);
3594 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3595 if (Model == TLSModel::LocalDynamic)
3596 Model = TLSModel::GeneralDynamic;
3600 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3602 const GlobalValue *GV = GA->getGlobal();
3604 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3606 if (Model == TLSModel::LocalExec) {
3607 SDValue HiVar = DAG.getTargetGlobalAddress(
3608 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3609 SDValue LoVar = DAG.getTargetGlobalAddress(
3611 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3613 SDValue TPWithOff_lo =
3614 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3616 DAG.getTargetConstant(0, DL, MVT::i32)),
3619 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3621 DAG.getTargetConstant(0, DL, MVT::i32)),
3624 } else if (Model == TLSModel::InitialExec) {
3625 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3626 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3627 } else if (Model == TLSModel::LocalDynamic) {
3628 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3629 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3630 // the beginning of the module's TLS region, followed by a DTPREL offset
3633 // These accesses will need deduplicating if there's more than one.
3634 AArch64FunctionInfo *MFI =
3635 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3636 MFI->incNumLocalDynamicTLSAccesses();
3638 // The call needs a relocation too for linker relaxation. It doesn't make
3639 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3641 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3644 // Now we can calculate the offset from TPIDR_EL0 to this module's
3645 // thread-local area.
3646 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3648 // Now use :dtprel_whatever: operations to calculate this variable's offset
3649 // in its thread-storage area.
3650 SDValue HiVar = DAG.getTargetGlobalAddress(
3651 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3652 SDValue LoVar = DAG.getTargetGlobalAddress(
3653 GV, DL, MVT::i64, 0,
3654 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3656 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3657 DAG.getTargetConstant(0, DL, MVT::i32)),
3659 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3660 DAG.getTargetConstant(0, DL, MVT::i32)),
3662 } else if (Model == TLSModel::GeneralDynamic) {
3663 // The call needs a relocation too for linker relaxation. It doesn't make
3664 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3667 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3669 // Finally we can make a call to calculate the offset from tpidr_el0.
3670 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3672 llvm_unreachable("Unsupported ELF TLS access model");
3674 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3677 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3678 SelectionDAG &DAG) const {
3679 if (Subtarget->isTargetDarwin())
3680 return LowerDarwinGlobalTLSAddress(Op, DAG);
3681 else if (Subtarget->isTargetELF())
3682 return LowerELFGlobalTLSAddress(Op, DAG);
3684 llvm_unreachable("Unexpected platform trying to use TLS");
3687 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3688 SDValue Chain = Op.getOperand(0);
3689 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3690 SDValue LHS = Op.getOperand(2);
3691 SDValue RHS = Op.getOperand(3);
3692 SDValue Dest = Op.getOperand(4);
3695 // Handle f128 first, since lowering it will result in comparing the return
3696 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3697 // is expecting to deal with.
3698 if (LHS.getValueType() == MVT::f128) {
3699 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3701 // If softenSetCCOperands returned a scalar, we need to compare the result
3702 // against zero to select between true and false values.
3703 if (!RHS.getNode()) {
3704 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3709 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3711 unsigned Opc = LHS.getOpcode();
3712 if (LHS.getResNo() == 1 && isOneConstant(RHS) &&
3713 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3714 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3715 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3716 "Unexpected condition code.");
3717 // Only lower legal XALUO ops.
3718 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3721 // The actual operation with overflow check.
3722 AArch64CC::CondCode OFCC;
3723 SDValue Value, Overflow;
3724 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3726 if (CC == ISD::SETNE)
3727 OFCC = getInvertedCondCode(OFCC);
3728 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3730 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3734 if (LHS.getValueType().isInteger()) {
3735 assert((LHS.getValueType() == RHS.getValueType()) &&
3736 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3738 // If the RHS of the comparison is zero, we can potentially fold this
3739 // to a specialized branch.
3740 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3741 if (RHSC && RHSC->getZExtValue() == 0) {
3742 if (CC == ISD::SETEQ) {
3743 // See if we can use a TBZ to fold in an AND as well.
3744 // TBZ has a smaller branch displacement than CBZ. If the offset is
3745 // out of bounds, a late MI-layer pass rewrites branches.
3746 // 403.gcc is an example that hits this case.
3747 if (LHS.getOpcode() == ISD::AND &&
3748 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3749 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3750 SDValue Test = LHS.getOperand(0);
3751 uint64_t Mask = LHS.getConstantOperandVal(1);
3752 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3753 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3757 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3758 } else if (CC == ISD::SETNE) {
3759 // See if we can use a TBZ to fold in an AND as well.
3760 // TBZ has a smaller branch displacement than CBZ. If the offset is
3761 // out of bounds, a late MI-layer pass rewrites branches.
3762 // 403.gcc is an example that hits this case.
3763 if (LHS.getOpcode() == ISD::AND &&
3764 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3765 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3766 SDValue Test = LHS.getOperand(0);
3767 uint64_t Mask = LHS.getConstantOperandVal(1);
3768 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3769 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3773 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3774 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3775 // Don't combine AND since emitComparison converts the AND to an ANDS
3776 // (a.k.a. TST) and the test in the test bit and branch instruction
3777 // becomes redundant. This would also increase register pressure.
3778 uint64_t Mask = LHS.getValueSizeInBits() - 1;
3779 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3780 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3783 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3784 LHS.getOpcode() != ISD::AND) {
3785 // Don't combine AND since emitComparison converts the AND to an ANDS
3786 // (a.k.a. TST) and the test in the test bit and branch instruction
3787 // becomes redundant. This would also increase register pressure.
3788 uint64_t Mask = LHS.getValueSizeInBits() - 1;
3789 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3790 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3794 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3795 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3799 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3801 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3802 // clean. Some of them require two branches to implement.
3803 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3804 AArch64CC::CondCode CC1, CC2;
3805 changeFPCCToAArch64CC(CC, CC1, CC2);
3806 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3808 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3809 if (CC2 != AArch64CC::AL) {
3810 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3811 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3818 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3819 SelectionDAG &DAG) const {
3820 EVT VT = Op.getValueType();
3823 SDValue In1 = Op.getOperand(0);
3824 SDValue In2 = Op.getOperand(1);
3825 EVT SrcVT = In2.getValueType();
3827 if (SrcVT.bitsLT(VT))
3828 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3829 else if (SrcVT.bitsGT(VT))
3830 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
3835 SDValue VecVal1, VecVal2;
3836 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3838 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3839 EltMask = 0x80000000ULL;
3841 if (!VT.isVector()) {
3842 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3843 DAG.getUNDEF(VecVT), In1);
3844 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3845 DAG.getUNDEF(VecVT), In2);
3847 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3848 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3850 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3854 // We want to materialize a mask with the high bit set, but the AdvSIMD
3855 // immediate moves cannot materialize that in a single instruction for
3856 // 64-bit elements. Instead, materialize zero and then negate it.
3859 if (!VT.isVector()) {
3860 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3861 DAG.getUNDEF(VecVT), In1);
3862 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3863 DAG.getUNDEF(VecVT), In2);
3865 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3866 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3869 llvm_unreachable("Invalid type for copysign!");
3872 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3874 // If we couldn't materialize the mask above, then the mask vector will be
3875 // the zero vector, and we need to negate it here.
3876 if (VT == MVT::f64 || VT == MVT::v2f64) {
3877 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3878 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3879 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3883 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3886 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3887 else if (VT == MVT::f64)
3888 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3890 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3893 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3894 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3895 Attribute::NoImplicitFloat))
3898 if (!Subtarget->hasNEON())
3901 // While there is no integer popcount instruction, it can
3902 // be more efficiently lowered to the following sequence that uses
3903 // AdvSIMD registers/instructions as long as the copies to/from
3904 // the AdvSIMD registers are cheap.
3905 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3906 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3907 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3908 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3909 SDValue Val = Op.getOperand(0);
3911 EVT VT = Op.getValueType();
3914 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3915 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3917 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3918 SDValue UaddLV = DAG.getNode(
3919 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3920 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3923 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3927 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3929 if (Op.getValueType().isVector())
3930 return LowerVSETCC(Op, DAG);
3932 SDValue LHS = Op.getOperand(0);
3933 SDValue RHS = Op.getOperand(1);
3934 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3937 // We chose ZeroOrOneBooleanContents, so use zero and one.
3938 EVT VT = Op.getValueType();
3939 SDValue TVal = DAG.getConstant(1, dl, VT);
3940 SDValue FVal = DAG.getConstant(0, dl, VT);
3942 // Handle f128 first, since one possible outcome is a normal integer
3943 // comparison which gets picked up by the next if statement.
3944 if (LHS.getValueType() == MVT::f128) {
3945 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3947 // If softenSetCCOperands returned a scalar, use it.
3948 if (!RHS.getNode()) {
3949 assert(LHS.getValueType() == Op.getValueType() &&
3950 "Unexpected setcc expansion!");
3955 if (LHS.getValueType().isInteger()) {
3958 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3960 // Note that we inverted the condition above, so we reverse the order of
3961 // the true and false operands here. This will allow the setcc to be
3962 // matched to a single CSINC instruction.
3963 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3966 // Now we know we're dealing with FP values.
3967 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3969 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3970 // and do the comparison.
3971 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3973 AArch64CC::CondCode CC1, CC2;
3974 changeFPCCToAArch64CC(CC, CC1, CC2);
3975 if (CC2 == AArch64CC::AL) {
3976 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3977 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3979 // Note that we inverted the condition above, so we reverse the order of
3980 // the true and false operands here. This will allow the setcc to be
3981 // matched to a single CSINC instruction.
3982 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3984 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3985 // totally clean. Some of them require two CSELs to implement. As is in
3986 // this case, we emit the first CSEL and then emit a second using the output
3987 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3989 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3990 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3992 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3994 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3995 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3999 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
4000 SDValue RHS, SDValue TVal,
4001 SDValue FVal, const SDLoc &dl,
4002 SelectionDAG &DAG) const {
4003 // Handle f128 first, because it will result in a comparison of some RTLIB
4004 // call result against zero.
4005 if (LHS.getValueType() == MVT::f128) {
4006 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4008 // If softenSetCCOperands returned a scalar, we need to compare the result
4009 // against zero to select between true and false values.
4010 if (!RHS.getNode()) {
4011 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4016 // Also handle f16, for which we need to do a f32 comparison.
4017 if (LHS.getValueType() == MVT::f16) {
4018 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
4019 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
4022 // Next, handle integers.
4023 if (LHS.getValueType().isInteger()) {
4024 assert((LHS.getValueType() == RHS.getValueType()) &&
4025 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
4027 unsigned Opcode = AArch64ISD::CSEL;
4029 // If both the TVal and the FVal are constants, see if we can swap them in
4030 // order to for a CSINV or CSINC out of them.
4031 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
4032 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
4034 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
4035 std::swap(TVal, FVal);
4036 std::swap(CTVal, CFVal);
4037 CC = ISD::getSetCCInverse(CC, true);
4038 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
4039 std::swap(TVal, FVal);
4040 std::swap(CTVal, CFVal);
4041 CC = ISD::getSetCCInverse(CC, true);
4042 } else if (TVal.getOpcode() == ISD::XOR) {
4043 // If TVal is a NOT we want to swap TVal and FVal so that we can match
4044 // with a CSINV rather than a CSEL.
4045 if (isAllOnesConstant(TVal.getOperand(1))) {
4046 std::swap(TVal, FVal);
4047 std::swap(CTVal, CFVal);
4048 CC = ISD::getSetCCInverse(CC, true);
4050 } else if (TVal.getOpcode() == ISD::SUB) {
4051 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
4052 // that we can match with a CSNEG rather than a CSEL.
4053 if (isNullConstant(TVal.getOperand(0))) {
4054 std::swap(TVal, FVal);
4055 std::swap(CTVal, CFVal);
4056 CC = ISD::getSetCCInverse(CC, true);
4058 } else if (CTVal && CFVal) {
4059 const int64_t TrueVal = CTVal->getSExtValue();
4060 const int64_t FalseVal = CFVal->getSExtValue();
4063 // If both TVal and FVal are constants, see if FVal is the
4064 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
4065 // instead of a CSEL in that case.
4066 if (TrueVal == ~FalseVal) {
4067 Opcode = AArch64ISD::CSINV;
4068 } else if (TrueVal == -FalseVal) {
4069 Opcode = AArch64ISD::CSNEG;
4070 } else if (TVal.getValueType() == MVT::i32) {
4071 // If our operands are only 32-bit wide, make sure we use 32-bit
4072 // arithmetic for the check whether we can use CSINC. This ensures that
4073 // the addition in the check will wrap around properly in case there is
4074 // an overflow (which would not be the case if we do the check with
4075 // 64-bit arithmetic).
4076 const uint32_t TrueVal32 = CTVal->getZExtValue();
4077 const uint32_t FalseVal32 = CFVal->getZExtValue();
4079 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
4080 Opcode = AArch64ISD::CSINC;
4082 if (TrueVal32 > FalseVal32) {
4086 // 64-bit check whether we can use CSINC.
4087 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
4088 Opcode = AArch64ISD::CSINC;
4090 if (TrueVal > FalseVal) {
4095 // Swap TVal and FVal if necessary.
4097 std::swap(TVal, FVal);
4098 std::swap(CTVal, CFVal);
4099 CC = ISD::getSetCCInverse(CC, true);
4102 if (Opcode != AArch64ISD::CSEL) {
4103 // Drop FVal since we can get its value by simply inverting/negating
4109 // Avoid materializing a constant when possible by reusing a known value in
4110 // a register. However, don't perform this optimization if the known value
4111 // is one, zero or negative one in the case of a CSEL. We can always
4112 // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
4113 // FVal, respectively.
4114 ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
4115 if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
4116 !RHSVal->isNullValue() && !RHSVal->isAllOnesValue()) {
4117 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
4118 // Transform "a == C ? C : x" to "a == C ? a : x" and "a != C ? x : C" to
4119 // "a != C ? x : a" to avoid materializing C.
4120 if (CTVal && CTVal == RHSVal && AArch64CC == AArch64CC::EQ)
4122 else if (CFVal && CFVal == RHSVal && AArch64CC == AArch64CC::NE)
4124 } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) {
4125 assert (CTVal && CFVal && "Expected constant operands for CSNEG.");
4126 // Use a CSINV to transform "a == C ? 1 : -1" to "a == C ? a : -1" to
4127 // avoid materializing C.
4128 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
4129 if (CTVal == RHSVal && AArch64CC == AArch64CC::EQ) {
4130 Opcode = AArch64ISD::CSINV;
4132 FVal = DAG.getConstant(0, dl, FVal.getValueType());
4137 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
4139 EVT VT = TVal.getValueType();
4140 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
4143 // Now we know we're dealing with FP values.
4144 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
4145 assert(LHS.getValueType() == RHS.getValueType());
4146 EVT VT = TVal.getValueType();
4147 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
4149 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
4150 // clean. Some of them require two CSELs to implement.
4151 AArch64CC::CondCode CC1, CC2;
4152 changeFPCCToAArch64CC(CC, CC1, CC2);
4154 if (DAG.getTarget().Options.UnsafeFPMath) {
4155 // Transform "a == 0.0 ? 0.0 : x" to "a == 0.0 ? a : x" and
4156 // "a != 0.0 ? x : 0.0" to "a != 0.0 ? x : a" to avoid materializing 0.0.
4157 ConstantFPSDNode *RHSVal = dyn_cast<ConstantFPSDNode>(RHS);
4158 if (RHSVal && RHSVal->isZero()) {
4159 ConstantFPSDNode *CFVal = dyn_cast<ConstantFPSDNode>(FVal);
4160 ConstantFPSDNode *CTVal = dyn_cast<ConstantFPSDNode>(TVal);
4162 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) &&
4163 CTVal && CTVal->isZero() && TVal.getValueType() == LHS.getValueType())
4165 else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) &&
4166 CFVal && CFVal->isZero() &&
4167 FVal.getValueType() == LHS.getValueType())
4172 // Emit first, and possibly only, CSEL.
4173 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4174 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4176 // If we need a second CSEL, emit it, using the output of the first as the
4177 // RHS. We're effectively OR'ing the two CC's together.
4178 if (CC2 != AArch64CC::AL) {
4179 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4180 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4183 // Otherwise, return the output of the first CSEL.
4187 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
4188 SelectionDAG &DAG) const {
4189 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4190 SDValue LHS = Op.getOperand(0);
4191 SDValue RHS = Op.getOperand(1);
4192 SDValue TVal = Op.getOperand(2);
4193 SDValue FVal = Op.getOperand(3);
4195 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4198 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
4199 SelectionDAG &DAG) const {
4200 SDValue CCVal = Op->getOperand(0);
4201 SDValue TVal = Op->getOperand(1);
4202 SDValue FVal = Op->getOperand(2);
4205 unsigned Opc = CCVal.getOpcode();
4206 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4208 if (CCVal.getResNo() == 1 &&
4209 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4210 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4211 // Only lower legal XALUO ops.
4212 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4215 AArch64CC::CondCode OFCC;
4216 SDValue Value, Overflow;
4217 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4218 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4220 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4224 // Lower it the same way as we would lower a SELECT_CC node.
4227 if (CCVal.getOpcode() == ISD::SETCC) {
4228 LHS = CCVal.getOperand(0);
4229 RHS = CCVal.getOperand(1);
4230 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4233 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4236 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4239 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4240 SelectionDAG &DAG) const {
4241 // Jump table entries as PC relative offsets. No additional tweaking
4242 // is necessary here. Just get the address of the jump table.
4243 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4244 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4247 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4248 !Subtarget->isTargetMachO()) {
4249 const unsigned char MO_NC = AArch64II::MO_NC;
4251 AArch64ISD::WrapperLarge, DL, PtrVT,
4252 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
4253 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
4254 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
4255 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4256 AArch64II::MO_G0 | MO_NC));
4260 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
4261 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
4262 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4263 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4264 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4267 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4268 SelectionDAG &DAG) const {
4269 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4270 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4273 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4274 // Use the GOT for the large code model on iOS.
4275 if (Subtarget->isTargetMachO()) {
4276 SDValue GotAddr = DAG.getTargetConstantPool(
4277 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4279 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
4282 const unsigned char MO_NC = AArch64II::MO_NC;
4284 AArch64ISD::WrapperLarge, DL, PtrVT,
4285 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4286 CP->getOffset(), AArch64II::MO_G3),
4287 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4288 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
4289 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4290 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
4291 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4292 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
4294 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4295 // ELF, the only valid one on Darwin.
4297 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
4298 CP->getOffset(), AArch64II::MO_PAGE);
4299 SDValue Lo = DAG.getTargetConstantPool(
4300 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
4301 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
4303 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4304 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4308 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4309 SelectionDAG &DAG) const {
4310 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4311 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4313 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4314 !Subtarget->isTargetMachO()) {
4315 const unsigned char MO_NC = AArch64II::MO_NC;
4317 AArch64ISD::WrapperLarge, DL, PtrVT,
4318 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
4319 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
4320 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
4321 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
4323 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
4324 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
4326 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
4327 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
4331 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4332 SelectionDAG &DAG) const {
4333 AArch64FunctionInfo *FuncInfo =
4334 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4337 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4338 getPointerTy(DAG.getDataLayout()));
4339 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4340 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4341 MachinePointerInfo(SV));
4344 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4345 SelectionDAG &DAG) const {
4346 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4347 // Standard, section B.3.
4348 MachineFunction &MF = DAG.getMachineFunction();
4349 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4350 auto PtrVT = getPointerTy(DAG.getDataLayout());
4353 SDValue Chain = Op.getOperand(0);
4354 SDValue VAList = Op.getOperand(1);
4355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4356 SmallVector<SDValue, 4> MemOps;
4358 // void *__stack at offset 0
4359 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4360 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4361 MachinePointerInfo(SV), /* Alignment = */ 8));
4363 // void *__gr_top at offset 8
4364 int GPRSize = FuncInfo->getVarArgsGPRSize();
4366 SDValue GRTop, GRTopAddr;
4369 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4371 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4372 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4373 DAG.getConstant(GPRSize, DL, PtrVT));
4375 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4376 MachinePointerInfo(SV, 8),
4377 /* Alignment = */ 8));
4380 // void *__vr_top at offset 16
4381 int FPRSize = FuncInfo->getVarArgsFPRSize();
4383 SDValue VRTop, VRTopAddr;
4384 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4385 DAG.getConstant(16, DL, PtrVT));
4387 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4388 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4389 DAG.getConstant(FPRSize, DL, PtrVT));
4391 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4392 MachinePointerInfo(SV, 16),
4393 /* Alignment = */ 8));
4396 // int __gr_offs at offset 24
4397 SDValue GROffsAddr =
4398 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4399 MemOps.push_back(DAG.getStore(
4400 Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32), GROffsAddr,
4401 MachinePointerInfo(SV, 24), /* Alignment = */ 4));
4403 // int __vr_offs at offset 28
4404 SDValue VROffsAddr =
4405 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4406 MemOps.push_back(DAG.getStore(
4407 Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32), VROffsAddr,
4408 MachinePointerInfo(SV, 28), /* Alignment = */ 4));
4410 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4413 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4414 SelectionDAG &DAG) const {
4415 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
4416 : LowerAAPCS_VASTART(Op, DAG);
4419 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4420 SelectionDAG &DAG) const {
4421 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4424 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
4425 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4426 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4428 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4430 DAG.getConstant(VaListSize, DL, MVT::i32),
4431 8, false, false, false, MachinePointerInfo(DestSV),
4432 MachinePointerInfo(SrcSV));
4435 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4436 assert(Subtarget->isTargetDarwin() &&
4437 "automatic va_arg instruction only works on Darwin");
4439 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4440 EVT VT = Op.getValueType();
4442 SDValue Chain = Op.getOperand(0);
4443 SDValue Addr = Op.getOperand(1);
4444 unsigned Align = Op.getConstantOperandVal(3);
4445 auto PtrVT = getPointerTy(DAG.getDataLayout());
4447 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V));
4448 Chain = VAList.getValue(1);
4451 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4452 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4453 DAG.getConstant(Align - 1, DL, PtrVT));
4454 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4455 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4458 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4459 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4461 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4462 // up to 64 bits. At the very least, we have to increase the striding of the
4463 // vaargs list to match this, and for FP values we need to introduce
4464 // FP_ROUND nodes as well.
4465 if (VT.isInteger() && !VT.isVector())
4467 bool NeedFPTrunc = false;
4468 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4473 // Increment the pointer, VAList, to the next vaarg
4474 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4475 DAG.getConstant(ArgSize, DL, PtrVT));
4476 // Store the incremented VAList to the legalized pointer
4478 DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V));
4480 // Load the actual argument out of the pointer VAList
4482 // Load the value as an f64.
4484 DAG.getLoad(MVT::f64, DL, APStore, VAList, MachinePointerInfo());
4485 // Round the value down to an f32.
4486 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4487 DAG.getIntPtrConstant(1, DL));
4488 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4489 // Merge the rounded value with the chain output of the load.
4490 return DAG.getMergeValues(Ops, DL);
4493 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo());
4496 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4497 SelectionDAG &DAG) const {
4498 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
4499 MFI.setFrameAddressIsTaken(true);
4501 EVT VT = Op.getValueType();
4503 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4505 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4507 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4508 MachinePointerInfo());
4512 // FIXME? Maybe this could be a TableGen attribute on some registers and
4513 // this table could be generated automatically from RegInfo.
4514 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4515 SelectionDAG &DAG) const {
4516 unsigned Reg = StringSwitch<unsigned>(RegName)
4517 .Case("sp", AArch64::SP)
4521 report_fatal_error(Twine("Invalid register name \""
4522 + StringRef(RegName) + "\"."));
4525 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4526 SelectionDAG &DAG) const {
4527 MachineFunction &MF = DAG.getMachineFunction();
4528 MachineFrameInfo &MFI = MF.getFrameInfo();
4529 MFI.setReturnAddressIsTaken(true);
4531 EVT VT = Op.getValueType();
4533 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4535 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4536 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4537 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4538 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4539 MachinePointerInfo());
4542 // Return LR, which contains the return address. Mark it an implicit live-in.
4543 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4544 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4547 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4548 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4549 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4550 SelectionDAG &DAG) const {
4551 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4552 EVT VT = Op.getValueType();
4553 unsigned VTBits = VT.getSizeInBits();
4555 SDValue ShOpLo = Op.getOperand(0);
4556 SDValue ShOpHi = Op.getOperand(1);
4557 SDValue ShAmt = Op.getOperand(2);
4558 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4560 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4562 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4563 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4564 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4566 // Unfortunately, if ShAmt == 0, we just calculated "(SHL ShOpHi, 64)" which
4567 // is "undef". We wanted 0, so CSEL it directly.
4568 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64),
4569 ISD::SETEQ, dl, DAG);
4570 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);
4572 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4573 HiBitsForLo, CCVal, Cmp);
4575 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4576 DAG.getConstant(VTBits, dl, MVT::i64));
4578 SDValue LoBitsForLo = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4579 SDValue LoForNormalShift =
4580 DAG.getNode(ISD::OR, dl, VT, LoBitsForLo, HiBitsForLo);
4582 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
4584 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4585 SDValue LoForBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4586 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4587 LoForNormalShift, CCVal, Cmp);
4589 // AArch64 shifts larger than the register width are wrapped rather than
4590 // clamped, so we can't just emit "hi >> x".
4591 SDValue HiForNormalShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4592 SDValue HiForBigShift =
4594 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4595 DAG.getConstant(VTBits - 1, dl, MVT::i64))
4596 : DAG.getConstant(0, dl, VT);
4597 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4598 HiForNormalShift, CCVal, Cmp);
4600 SDValue Ops[2] = { Lo, Hi };
4601 return DAG.getMergeValues(Ops, dl);
4604 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4605 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4606 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4607 SelectionDAG &DAG) const {
4608 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4609 EVT VT = Op.getValueType();
4610 unsigned VTBits = VT.getSizeInBits();
4612 SDValue ShOpLo = Op.getOperand(0);
4613 SDValue ShOpHi = Op.getOperand(1);
4614 SDValue ShAmt = Op.getOperand(2);
4616 assert(Op.getOpcode() == ISD::SHL_PARTS);
4617 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4618 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4619 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4621 // Unfortunately, if ShAmt == 0, we just calculated "(SRL ShOpLo, 64)" which
4622 // is "undef". We wanted 0, so CSEL it directly.
4623 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64),
4624 ISD::SETEQ, dl, DAG);
4625 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);
4627 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4628 LoBitsForHi, CCVal, Cmp);
4630 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4631 DAG.getConstant(VTBits, dl, MVT::i64));
4632 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4633 SDValue HiForNormalShift =
4634 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
4636 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4638 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
4640 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4641 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4642 HiForNormalShift, CCVal, Cmp);
4644 // AArch64 shifts of larger than register sizes are wrapped rather than
4645 // clamped, so we can't just emit "lo << a" if a is too big.
4646 SDValue LoForBigShift = DAG.getConstant(0, dl, VT);
4647 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4648 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4649 LoForNormalShift, CCVal, Cmp);
4651 SDValue Ops[2] = { Lo, Hi };
4652 return DAG.getMergeValues(Ops, dl);
4655 bool AArch64TargetLowering::isOffsetFoldingLegal(
4656 const GlobalAddressSDNode *GA) const {
4657 // The AArch64 target doesn't support folding offsets into global addresses.
4661 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4662 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4663 // FIXME: We should be able to handle f128 as well with a clever lowering.
4664 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4668 return AArch64_AM::getFP64Imm(Imm) != -1;
4669 else if (VT == MVT::f32)
4670 return AArch64_AM::getFP32Imm(Imm) != -1;
4674 //===----------------------------------------------------------------------===//
4675 // AArch64 Optimization Hooks
4676 //===----------------------------------------------------------------------===//
4678 static SDValue getEstimate(const AArch64Subtarget *ST, unsigned Opcode,
4679 SDValue Operand, SelectionDAG &DAG,
4681 EVT VT = Operand.getValueType();
4682 if (ST->hasNEON() &&
4683 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 ||
4684 VT == MVT::f32 || VT == MVT::v1f32 ||
4685 VT == MVT::v2f32 || VT == MVT::v4f32)) {
4686 if (ExtraSteps == TargetLoweringBase::ReciprocalEstimate::Unspecified)
4687 // For the reciprocal estimates, convergence is quadratic, so the number
4688 // of digits is doubled after each iteration. In ARMv8, the accuracy of
4689 // the initial estimate is 2^-8. Thus the number of extra steps to refine
4690 // the result for float (23 mantissa bits) is 2 and for double (52
4691 // mantissa bits) is 3.
4692 ExtraSteps = VT == MVT::f64 ? 3 : 2;
4694 return DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);
4700 SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,
4701 SelectionDAG &DAG, int Enabled,
4704 bool Reciprocal) const {
4705 if (Enabled == ReciprocalEstimate::Enabled ||
4706 (Enabled == ReciprocalEstimate::Unspecified && Subtarget->useRSqrt()))
4707 if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRSQRTE, Operand,
4710 EVT VT = Operand.getValueType();
4713 Flags.setUnsafeAlgebra(true);
4715 // Newton reciprocal square root iteration: E * 0.5 * (3 - X * E^2)
4716 // AArch64 reciprocal square root iteration instruction: 0.5 * (3 - M * N)
4717 for (int i = ExtraSteps; i > 0; --i) {
4718 SDValue Step = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Estimate,
4720 Step = DAG.getNode(AArch64ISD::FRSQRTS, DL, VT, Operand, Step, &Flags);
4721 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, &Flags);
4725 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
4727 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT);
4728 SDValue Eq = DAG.getSetCC(DL, CCVT, Operand, FPZero, ISD::SETEQ);
4730 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate, &Flags);
4731 // Correct the result if the operand is 0.0.
4732 Estimate = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL,
4733 VT, Eq, Operand, Estimate);
4743 SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
4744 SelectionDAG &DAG, int Enabled,
4745 int &ExtraSteps) const {
4746 if (Enabled == ReciprocalEstimate::Enabled)
4747 if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRECPE, Operand,
4750 EVT VT = Operand.getValueType();
4753 Flags.setUnsafeAlgebra(true);
4755 // Newton reciprocal iteration: E * (2 - X * E)
4756 // AArch64 reciprocal iteration instruction: (2 - M * N)
4757 for (int i = ExtraSteps; i > 0; --i) {
4758 SDValue Step = DAG.getNode(AArch64ISD::FRECPS, DL, VT, Operand,
4760 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, &Flags);
4770 //===----------------------------------------------------------------------===//
4771 // AArch64 Inline Assembly Support
4772 //===----------------------------------------------------------------------===//
4774 // Table of Constraints
4775 // TODO: This is the current set of constraints supported by ARM for the
4776 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4778 // r - A general register
4779 // w - An FP/SIMD register of some size in the range v0-v31
4780 // x - An FP/SIMD register of some size in the range v0-v15
4781 // I - Constant that can be used with an ADD instruction
4782 // J - Constant that can be used with a SUB instruction
4783 // K - Constant that can be used with a 32-bit logical instruction
4784 // L - Constant that can be used with a 64-bit logical instruction
4785 // M - Constant that can be used as a 32-bit MOV immediate
4786 // N - Constant that can be used as a 64-bit MOV immediate
4787 // Q - A memory reference with base register and no offset
4788 // S - A symbolic address
4789 // Y - Floating point constant zero
4790 // Z - Integer constant zero
4792 // Note that general register operands will be output using their 64-bit x
4793 // register name, whatever the size of the variable, unless the asm operand
4794 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4795 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4797 const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
4798 // At this point, we have to lower this constraint to something else, so we
4799 // lower it to an "r" or "w". However, by doing this we will force the result
4800 // to be in register, while the X constraint is much more permissive.
4802 // Although we are correct (we are free to emit anything, without
4803 // constraints), we might break use cases that would expect us to be more
4804 // efficient and emit something else.
4805 if (!Subtarget->hasFPARMv8())
4808 if (ConstraintVT.isFloatingPoint())
4811 if (ConstraintVT.isVector() &&
4812 (ConstraintVT.getSizeInBits() == 64 ||
4813 ConstraintVT.getSizeInBits() == 128))
4819 /// getConstraintType - Given a constraint letter, return the type of
4820 /// constraint it is for this target.
4821 AArch64TargetLowering::ConstraintType
4822 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4823 if (Constraint.size() == 1) {
4824 switch (Constraint[0]) {
4831 return C_RegisterClass;
4832 // An address with a single base register. Due to the way we
4833 // currently handle addresses it is the same as 'r'.
4838 return TargetLowering::getConstraintType(Constraint);
4841 /// Examine constraint type and operand type and determine a weight value.
4842 /// This object must already have been set up with the operand type
4843 /// and the current alternative constraint selected.
4844 TargetLowering::ConstraintWeight
4845 AArch64TargetLowering::getSingleConstraintMatchWeight(
4846 AsmOperandInfo &info, const char *constraint) const {
4847 ConstraintWeight weight = CW_Invalid;
4848 Value *CallOperandVal = info.CallOperandVal;
4849 // If we don't have a value, we can't do a match,
4850 // but allow it at the lowest weight.
4851 if (!CallOperandVal)
4853 Type *type = CallOperandVal->getType();
4854 // Look at the constraint type.
4855 switch (*constraint) {
4857 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4861 if (type->isFloatingPointTy() || type->isVectorTy())
4862 weight = CW_Register;
4865 weight = CW_Constant;
4871 std::pair<unsigned, const TargetRegisterClass *>
4872 AArch64TargetLowering::getRegForInlineAsmConstraint(
4873 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4874 if (Constraint.size() == 1) {
4875 switch (Constraint[0]) {
4877 if (VT.getSizeInBits() == 64)
4878 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4879 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4881 if (VT.getSizeInBits() == 16)
4882 return std::make_pair(0U, &AArch64::FPR16RegClass);
4883 if (VT.getSizeInBits() == 32)
4884 return std::make_pair(0U, &AArch64::FPR32RegClass);
4885 if (VT.getSizeInBits() == 64)
4886 return std::make_pair(0U, &AArch64::FPR64RegClass);
4887 if (VT.getSizeInBits() == 128)
4888 return std::make_pair(0U, &AArch64::FPR128RegClass);
4890 // The instructions that this constraint is designed for can
4891 // only take 128-bit registers so just use that regclass.
4893 if (VT.getSizeInBits() == 128)
4894 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4898 if (StringRef("{cc}").equals_lower(Constraint))
4899 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4901 // Use the default implementation in TargetLowering to convert the register
4902 // constraint into a member of a register class.
4903 std::pair<unsigned, const TargetRegisterClass *> Res;
4904 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4906 // Not found as a standard register?
4908 unsigned Size = Constraint.size();
4909 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4910 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4912 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4913 if (!Failed && RegNo >= 0 && RegNo <= 31) {
4914 // v0 - v31 are aliases of q0 - q31 or d0 - d31 depending on size.
4915 // By default we'll emit v0-v31 for this unless there's a modifier where
4916 // we'll emit the correct register as well.
4917 if (VT != MVT::Other && VT.getSizeInBits() == 64) {
4918 Res.first = AArch64::FPR64RegClass.getRegister(RegNo);
4919 Res.second = &AArch64::FPR64RegClass;
4921 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4922 Res.second = &AArch64::FPR128RegClass;
4931 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4932 /// vector. If it is invalid, don't add anything to Ops.
4933 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4934 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4935 SelectionDAG &DAG) const {
4938 // Currently only support length 1 constraints.
4939 if (Constraint.length() != 1)
4942 char ConstraintLetter = Constraint[0];
4943 switch (ConstraintLetter) {
4947 // This set of constraints deal with valid constants for various instructions.
4948 // Validate and return a target constant for them if we can.
4950 // 'z' maps to xzr or wzr so it needs an input of 0.
4951 if (!isNullConstant(Op))
4954 if (Op.getValueType() == MVT::i64)
4955 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4957 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4967 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4971 // Grab the value and do some validation.
4972 uint64_t CVal = C->getZExtValue();
4973 switch (ConstraintLetter) {
4974 // The I constraint applies only to simple ADD or SUB immediate operands:
4975 // i.e. 0 to 4095 with optional shift by 12
4976 // The J constraint applies only to ADD or SUB immediates that would be
4977 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4978 // instruction [or vice versa], in other words -1 to -4095 with optional
4979 // left shift by 12.
4981 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4985 uint64_t NVal = -C->getSExtValue();
4986 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4987 CVal = C->getSExtValue();
4992 // The K and L constraints apply *only* to logical immediates, including
4993 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4994 // been removed and MOV should be used). So these constraints have to
4995 // distinguish between bit patterns that are valid 32-bit or 64-bit
4996 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4997 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
5000 if (AArch64_AM::isLogicalImmediate(CVal, 32))
5004 if (AArch64_AM::isLogicalImmediate(CVal, 64))
5007 // The M and N constraints are a superset of K and L respectively, for use
5008 // with the MOV (immediate) alias. As well as the logical immediates they
5009 // also match 32 or 64-bit immediates that can be loaded either using a
5010 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
5011 // (M) or 64-bit 0x1234000000000000 (N) etc.
5012 // As a note some of this code is liberally stolen from the asm parser.
5014 if (!isUInt<32>(CVal))
5016 if (AArch64_AM::isLogicalImmediate(CVal, 32))
5018 if ((CVal & 0xFFFF) == CVal)
5020 if ((CVal & 0xFFFF0000ULL) == CVal)
5022 uint64_t NCVal = ~(uint32_t)CVal;
5023 if ((NCVal & 0xFFFFULL) == NCVal)
5025 if ((NCVal & 0xFFFF0000ULL) == NCVal)
5030 if (AArch64_AM::isLogicalImmediate(CVal, 64))
5032 if ((CVal & 0xFFFFULL) == CVal)
5034 if ((CVal & 0xFFFF0000ULL) == CVal)
5036 if ((CVal & 0xFFFF00000000ULL) == CVal)
5038 if ((CVal & 0xFFFF000000000000ULL) == CVal)
5040 uint64_t NCVal = ~CVal;
5041 if ((NCVal & 0xFFFFULL) == NCVal)
5043 if ((NCVal & 0xFFFF0000ULL) == NCVal)
5045 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
5047 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
5055 // All assembler immediates are 64-bit integers.
5056 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
5060 if (Result.getNode()) {
5061 Ops.push_back(Result);
5065 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5068 //===----------------------------------------------------------------------===//
5069 // AArch64 Advanced SIMD Support
5070 //===----------------------------------------------------------------------===//
5072 /// WidenVector - Given a value in the V64 register class, produce the
5073 /// equivalent value in the V128 register class.
5074 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
5075 EVT VT = V64Reg.getValueType();
5076 unsigned NarrowSize = VT.getVectorNumElements();
5077 MVT EltTy = VT.getVectorElementType().getSimpleVT();
5078 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
5081 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
5082 V64Reg, DAG.getConstant(0, DL, MVT::i32));
5085 /// getExtFactor - Determine the adjustment factor for the position when
5086 /// generating an "extract from vector registers" instruction.
5087 static unsigned getExtFactor(SDValue &V) {
5088 EVT EltType = V.getValueType().getVectorElementType();
5089 return EltType.getSizeInBits() / 8;
5092 /// NarrowVector - Given a value in the V128 register class, produce the
5093 /// equivalent value in the V64 register class.
5094 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
5095 EVT VT = V128Reg.getValueType();
5096 unsigned WideSize = VT.getVectorNumElements();
5097 MVT EltTy = VT.getVectorElementType().getSimpleVT();
5098 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
5101 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
5104 // Gather data to see if the operation can be modelled as a
5105 // shuffle in combination with VEXTs.
5106 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
5107 SelectionDAG &DAG) const {
5108 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5110 EVT VT = Op.getValueType();
5111 unsigned NumElts = VT.getVectorNumElements();
5113 struct ShuffleSourceInfo {
5118 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
5119 // be compatible with the shuffle we intend to construct. As a result
5120 // ShuffleVec will be some sliding window into the original Vec.
5123 // Code should guarantee that element i in Vec starts at element "WindowBase
5124 // + i * WindowScale in ShuffleVec".
5128 ShuffleSourceInfo(SDValue Vec)
5129 : Vec(Vec), MinElt(std::numeric_limits<unsigned>::max()), MaxElt(0),
5130 ShuffleVec(Vec), WindowBase(0), WindowScale(1) {}
5132 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
5135 // First gather all vectors used as an immediate source for this BUILD_VECTOR
5137 SmallVector<ShuffleSourceInfo, 2> Sources;
5138 for (unsigned i = 0; i < NumElts; ++i) {
5139 SDValue V = Op.getOperand(i);
5142 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5143 !isa<ConstantSDNode>(V.getOperand(1))) {
5144 // A shuffle can only come from building a vector from various
5145 // elements of other vectors, provided their indices are constant.
5149 // Add this element source to the list if it's not already there.
5150 SDValue SourceVec = V.getOperand(0);
5151 auto Source = find(Sources, SourceVec);
5152 if (Source == Sources.end())
5153 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
5155 // Update the minimum and maximum lane number seen.
5156 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5157 Source->MinElt = std::min(Source->MinElt, EltNo);
5158 Source->MaxElt = std::max(Source->MaxElt, EltNo);
5161 // Currently only do something sane when at most two source vectors
5163 if (Sources.size() > 2)
5166 // Find out the smallest element size among result and two sources, and use
5167 // it as element size to build the shuffle_vector.
5168 EVT SmallestEltTy = VT.getVectorElementType();
5169 for (auto &Source : Sources) {
5170 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
5171 if (SrcEltTy.bitsLT(SmallestEltTy)) {
5172 SmallestEltTy = SrcEltTy;
5175 unsigned ResMultiplier =
5176 VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits();
5177 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
5178 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
5180 // If the source vector is too wide or too narrow, we may nevertheless be able
5181 // to construct a compatible shuffle either by concatenating it with UNDEF or
5182 // extracting a suitable range of elements.
5183 for (auto &Src : Sources) {
5184 EVT SrcVT = Src.ShuffleVec.getValueType();
5186 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
5189 // This stage of the search produces a source with the same element type as
5190 // the original, but with a total width matching the BUILD_VECTOR output.
5191 EVT EltVT = SrcVT.getVectorElementType();
5192 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
5193 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
5195 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
5196 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
5197 // We can pad out the smaller vector for free, so if it's part of a
5200 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5201 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
5205 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
5207 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
5208 // Span too large for a VEXT to cope
5212 if (Src.MinElt >= NumSrcElts) {
5213 // The extraction can just take the second half
5215 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5216 DAG.getConstant(NumSrcElts, dl, MVT::i64));
5217 Src.WindowBase = -NumSrcElts;
5218 } else if (Src.MaxElt < NumSrcElts) {
5219 // The extraction can just take the first half
5221 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5222 DAG.getConstant(0, dl, MVT::i64));
5224 // An actual VEXT is needed
5226 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5227 DAG.getConstant(0, dl, MVT::i64));
5229 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5230 DAG.getConstant(NumSrcElts, dl, MVT::i64));
5231 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
5233 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
5235 DAG.getConstant(Imm, dl, MVT::i32));
5236 Src.WindowBase = -Src.MinElt;
5240 // Another possible incompatibility occurs from the vector element types. We
5241 // can fix this by bitcasting the source vectors to the same type we intend
5243 for (auto &Src : Sources) {
5244 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
5245 if (SrcEltTy == SmallestEltTy)
5247 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
5248 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
5249 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
5250 Src.WindowBase *= Src.WindowScale;
5253 // Final sanity check before we try to actually produce a shuffle.
5255 for (auto Src : Sources)
5256 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
5259 // The stars all align, our next step is to produce the mask for the shuffle.
5260 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
5261 int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits();
5262 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
5263 SDValue Entry = Op.getOperand(i);
5264 if (Entry.isUndef())
5267 auto Src = find(Sources, Entry.getOperand(0));
5268 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
5270 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
5271 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
5273 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
5275 std::min(OrigEltTy.getSizeInBits(), VT.getScalarSizeInBits());
5276 int LanesDefined = BitsDefined / BitsPerShuffleLane;
5278 // This source is expected to fill ResMultiplier lanes of the final shuffle,
5279 // starting at the appropriate offset.
5280 int *LaneMask = &Mask[i * ResMultiplier];
5282 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
5283 ExtractBase += NumElts * (Src - Sources.begin());
5284 for (int j = 0; j < LanesDefined; ++j)
5285 LaneMask[j] = ExtractBase + j;
5288 // Final check before we try to produce nonsense...
5289 if (!isShuffleMaskLegal(Mask, ShuffleVT))
5292 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
5293 for (unsigned i = 0; i < Sources.size(); ++i)
5294 ShuffleOps[i] = Sources[i].ShuffleVec;
5296 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
5297 ShuffleOps[1], Mask);
5298 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
5301 // check if an EXT instruction can handle the shuffle mask when the
5302 // vector sources of the shuffle are the same.
5303 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
5304 unsigned NumElts = VT.getVectorNumElements();
5306 // Assume that the first shuffle index is not UNDEF. Fail if it is.
5312 // If this is a VEXT shuffle, the immediate value is the index of the first
5313 // element. The other shuffle indices must be the successive elements after
5315 unsigned ExpectedElt = Imm;
5316 for (unsigned i = 1; i < NumElts; ++i) {
5317 // Increment the expected index. If it wraps around, just follow it
5318 // back to index zero and keep going.
5320 if (ExpectedElt == NumElts)
5324 continue; // ignore UNDEF indices
5325 if (ExpectedElt != static_cast<unsigned>(M[i]))
5332 // check if an EXT instruction can handle the shuffle mask when the
5333 // vector sources of the shuffle are different.
5334 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
5336 // Look for the first non-undef element.
5337 const int *FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
5339 // Benefit form APInt to handle overflow when calculating expected element.
5340 unsigned NumElts = VT.getVectorNumElements();
5341 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5342 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5343 // The following shuffle indices must be the successive elements after the
5344 // first real element.
5345 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5346 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5347 if (FirstWrongElt != M.end())
5350 // The index of an EXT is the first element if it is not UNDEF.
5351 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5352 // value of the first element. E.g.
5353 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5354 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5355 // ExpectedElt is the last mask index plus 1.
5356 Imm = ExpectedElt.getZExtValue();
5358 // There are two difference cases requiring to reverse input vectors.
5359 // For example, for vector <4 x i32> we have the following cases,
5360 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5361 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5362 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5363 // to reverse two input vectors.
5372 /// isREVMask - Check if a vector shuffle corresponds to a REV
5373 /// instruction with the specified blocksize. (The order of the elements
5374 /// within each block of the vector is reversed.)
5375 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5376 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
5377 "Only possible block sizes for REV are: 16, 32, 64");
5379 unsigned EltSz = VT.getScalarSizeInBits();
5383 unsigned NumElts = VT.getVectorNumElements();
5384 unsigned BlockElts = M[0] + 1;
5385 // If the first shuffle index is UNDEF, be optimistic.
5387 BlockElts = BlockSize / EltSz;
5389 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5392 for (unsigned i = 0; i < NumElts; ++i) {
5394 continue; // ignore UNDEF indices
5395 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5402 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5403 unsigned NumElts = VT.getVectorNumElements();
5404 WhichResult = (M[0] == 0 ? 0 : 1);
5405 unsigned Idx = WhichResult * NumElts / 2;
5406 for (unsigned i = 0; i != NumElts; i += 2) {
5407 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5408 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5416 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5417 unsigned NumElts = VT.getVectorNumElements();
5418 WhichResult = (M[0] == 0 ? 0 : 1);
5419 for (unsigned i = 0; i != NumElts; ++i) {
5421 continue; // ignore UNDEF indices
5422 if ((unsigned)M[i] != 2 * i + WhichResult)
5429 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5430 unsigned NumElts = VT.getVectorNumElements();
5431 WhichResult = (M[0] == 0 ? 0 : 1);
5432 for (unsigned i = 0; i < NumElts; i += 2) {
5433 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5434 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5440 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5441 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5442 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5443 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5444 unsigned NumElts = VT.getVectorNumElements();
5445 WhichResult = (M[0] == 0 ? 0 : 1);
5446 unsigned Idx = WhichResult * NumElts / 2;
5447 for (unsigned i = 0; i != NumElts; i += 2) {
5448 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5449 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5457 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5458 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5459 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5460 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5461 unsigned Half = VT.getVectorNumElements() / 2;
5462 WhichResult = (M[0] == 0 ? 0 : 1);
5463 for (unsigned j = 0; j != 2; ++j) {
5464 unsigned Idx = WhichResult;
5465 for (unsigned i = 0; i != Half; ++i) {
5466 int MIdx = M[i + j * Half];
5467 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5476 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5477 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5478 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5479 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5480 unsigned NumElts = VT.getVectorNumElements();
5481 WhichResult = (M[0] == 0 ? 0 : 1);
5482 for (unsigned i = 0; i < NumElts; i += 2) {
5483 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5484 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5490 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5491 bool &DstIsLeft, int &Anomaly) {
5492 if (M.size() != static_cast<size_t>(NumInputElements))
5495 int NumLHSMatch = 0, NumRHSMatch = 0;
5496 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5498 for (int i = 0; i < NumInputElements; ++i) {
5508 LastLHSMismatch = i;
5510 if (M[i] == i + NumInputElements)
5513 LastRHSMismatch = i;
5516 if (NumLHSMatch == NumInputElements - 1) {
5518 Anomaly = LastLHSMismatch;
5520 } else if (NumRHSMatch == NumInputElements - 1) {
5522 Anomaly = LastRHSMismatch;
5529 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5530 if (VT.getSizeInBits() != 128)
5533 unsigned NumElts = VT.getVectorNumElements();
5535 for (int I = 0, E = NumElts / 2; I != E; I++) {
5540 int Offset = NumElts / 2;
5541 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5542 if (Mask[I] != I + SplitLHS * Offset)
5549 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5551 EVT VT = Op.getValueType();
5552 SDValue V0 = Op.getOperand(0);
5553 SDValue V1 = Op.getOperand(1);
5554 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5556 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5557 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5560 bool SplitV0 = V0.getValueSizeInBits() == 128;
5562 if (!isConcatMask(Mask, VT, SplitV0))
5565 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5566 VT.getVectorNumElements() / 2);
5568 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5569 DAG.getConstant(0, DL, MVT::i64));
5571 if (V1.getValueSizeInBits() == 128) {
5572 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5573 DAG.getConstant(0, DL, MVT::i64));
5575 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5578 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5579 /// the specified operations to build the shuffle.
5580 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5581 SDValue RHS, SelectionDAG &DAG,
5583 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5584 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5585 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5588 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5597 OP_VUZPL, // VUZP, left result
5598 OP_VUZPR, // VUZP, right result
5599 OP_VZIPL, // VZIP, left result
5600 OP_VZIPR, // VZIP, right result
5601 OP_VTRNL, // VTRN, left result
5602 OP_VTRNR // VTRN, right result
5605 if (OpNum == OP_COPY) {
5606 if (LHSID == (1 * 9 + 2) * 9 + 3)
5608 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5612 SDValue OpLHS, OpRHS;
5613 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5614 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5615 EVT VT = OpLHS.getValueType();
5619 llvm_unreachable("Unknown shuffle opcode!");
5621 // VREV divides the vector in half and swaps within the half.
5622 if (VT.getVectorElementType() == MVT::i32 ||
5623 VT.getVectorElementType() == MVT::f32)
5624 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5625 // vrev <4 x i16> -> REV32
5626 if (VT.getVectorElementType() == MVT::i16 ||
5627 VT.getVectorElementType() == MVT::f16)
5628 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5629 // vrev <4 x i8> -> REV16
5630 assert(VT.getVectorElementType() == MVT::i8);
5631 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5636 EVT EltTy = VT.getVectorElementType();
5638 if (EltTy == MVT::i8)
5639 Opcode = AArch64ISD::DUPLANE8;
5640 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5641 Opcode = AArch64ISD::DUPLANE16;
5642 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5643 Opcode = AArch64ISD::DUPLANE32;
5644 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5645 Opcode = AArch64ISD::DUPLANE64;
5647 llvm_unreachable("Invalid vector element type?");
5649 if (VT.getSizeInBits() == 64)
5650 OpLHS = WidenVector(OpLHS, DAG);
5651 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5652 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5657 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5658 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5659 DAG.getConstant(Imm, dl, MVT::i32));
5662 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5665 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5668 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5671 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5674 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5677 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5682 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5683 SelectionDAG &DAG) {
5684 // Check to see if we can use the TBL instruction.
5685 SDValue V1 = Op.getOperand(0);
5686 SDValue V2 = Op.getOperand(1);
5689 EVT EltVT = Op.getValueType().getVectorElementType();
5690 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5692 SmallVector<SDValue, 8> TBLMask;
5693 for (int Val : ShuffleMask) {
5694 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5695 unsigned Offset = Byte + Val * BytesPerElt;
5696 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5700 MVT IndexVT = MVT::v8i8;
5701 unsigned IndexLen = 8;
5702 if (Op.getValueSizeInBits() == 128) {
5703 IndexVT = MVT::v16i8;
5707 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5708 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5711 if (V2.getNode()->isUndef()) {
5713 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5714 Shuffle = DAG.getNode(
5715 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5716 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5717 DAG.getBuildVector(IndexVT, DL,
5718 makeArrayRef(TBLMask.data(), IndexLen)));
5720 if (IndexLen == 8) {
5721 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5722 Shuffle = DAG.getNode(
5723 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5724 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5725 DAG.getBuildVector(IndexVT, DL,
5726 makeArrayRef(TBLMask.data(), IndexLen)));
5728 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5729 // cannot currently represent the register constraints on the input
5731 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5732 // DAG.getBuildVector(IndexVT, DL, &TBLMask[0],
5734 Shuffle = DAG.getNode(
5735 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5736 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32), V1Cst,
5737 V2Cst, DAG.getBuildVector(IndexVT, DL,
5738 makeArrayRef(TBLMask.data(), IndexLen)));
5741 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5744 static unsigned getDUPLANEOp(EVT EltType) {
5745 if (EltType == MVT::i8)
5746 return AArch64ISD::DUPLANE8;
5747 if (EltType == MVT::i16 || EltType == MVT::f16)
5748 return AArch64ISD::DUPLANE16;
5749 if (EltType == MVT::i32 || EltType == MVT::f32)
5750 return AArch64ISD::DUPLANE32;
5751 if (EltType == MVT::i64 || EltType == MVT::f64)
5752 return AArch64ISD::DUPLANE64;
5754 llvm_unreachable("Invalid vector element type?");
5757 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5758 SelectionDAG &DAG) const {
5760 EVT VT = Op.getValueType();
5762 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5764 // Convert shuffles that are directly supported on NEON to target-specific
5765 // DAG nodes, instead of keeping them as shuffles and matching them again
5766 // during code selection. This is more efficient and avoids the possibility
5767 // of inconsistencies between legalization and selection.
5768 ArrayRef<int> ShuffleMask = SVN->getMask();
5770 SDValue V1 = Op.getOperand(0);
5771 SDValue V2 = Op.getOperand(1);
5773 if (SVN->isSplat()) {
5774 int Lane = SVN->getSplatIndex();
5775 // If this is undef splat, generate it via "just" vdup, if possible.
5779 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5780 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5782 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5783 // constant. If so, we can just reference the lane's definition directly.
5784 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5785 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5786 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5788 // Otherwise, duplicate from the lane of the input vector.
5789 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5791 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5792 // to make a vector of the same size as this SHUFFLE. We can ignore the
5793 // extract entirely, and canonicalise the concat using WidenVector.
5794 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5795 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5796 V1 = V1.getOperand(0);
5797 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5798 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5799 Lane -= Idx * VT.getVectorNumElements() / 2;
5800 V1 = WidenVector(V1.getOperand(Idx), DAG);
5801 } else if (VT.getSizeInBits() == 64)
5802 V1 = WidenVector(V1, DAG);
5804 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5807 if (isREVMask(ShuffleMask, VT, 64))
5808 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5809 if (isREVMask(ShuffleMask, VT, 32))
5810 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5811 if (isREVMask(ShuffleMask, VT, 16))
5812 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5814 bool ReverseEXT = false;
5816 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5819 Imm *= getExtFactor(V1);
5820 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5821 DAG.getConstant(Imm, dl, MVT::i32));
5822 } else if (V2->isUndef() && isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5823 Imm *= getExtFactor(V1);
5824 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5825 DAG.getConstant(Imm, dl, MVT::i32));
5828 unsigned WhichResult;
5829 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5830 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5831 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5833 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5834 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5835 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5837 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5838 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5839 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5842 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5843 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5844 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5846 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5847 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5848 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5850 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5851 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5852 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5855 if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG))
5860 int NumInputElements = V1.getValueType().getVectorNumElements();
5861 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5862 SDValue DstVec = DstIsLeft ? V1 : V2;
5863 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5865 SDValue SrcVec = V1;
5866 int SrcLane = ShuffleMask[Anomaly];
5867 if (SrcLane >= NumInputElements) {
5869 SrcLane -= VT.getVectorNumElements();
5871 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5873 EVT ScalarVT = VT.getVectorElementType();
5875 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5876 ScalarVT = MVT::i32;
5879 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5880 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5884 // If the shuffle is not directly supported and it has 4 elements, use
5885 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5886 unsigned NumElts = VT.getVectorNumElements();
5888 unsigned PFIndexes[4];
5889 for (unsigned i = 0; i != 4; ++i) {
5890 if (ShuffleMask[i] < 0)
5893 PFIndexes[i] = ShuffleMask[i];
5896 // Compute the index in the perfect shuffle table.
5897 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5898 PFIndexes[2] * 9 + PFIndexes[3];
5899 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5900 unsigned Cost = (PFEntry >> 30);
5903 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5906 return GenerateTBL(Op, ShuffleMask, DAG);
5909 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5911 EVT VT = BVN->getValueType(0);
5912 APInt SplatBits, SplatUndef;
5913 unsigned SplatBitSize;
5915 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5916 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5918 for (unsigned i = 0; i < NumSplats; ++i) {
5919 CnstBits <<= SplatBitSize;
5920 UndefBits <<= SplatBitSize;
5921 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5922 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5931 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5932 SelectionDAG &DAG) const {
5933 BuildVectorSDNode *BVN =
5934 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5935 SDValue LHS = Op.getOperand(0);
5937 EVT VT = Op.getValueType();
5942 APInt CnstBits(VT.getSizeInBits(), 0);
5943 APInt UndefBits(VT.getSizeInBits(), 0);
5944 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5945 // We only have BIC vector immediate instruction, which is and-not.
5946 CnstBits = ~CnstBits;
5948 // We make use of a little bit of goto ickiness in order to avoid having to
5949 // duplicate the immediate matching logic for the undef toggled case.
5950 bool SecondTry = false;
5953 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5954 CnstBits = CnstBits.zextOrTrunc(64);
5955 uint64_t CnstVal = CnstBits.getZExtValue();
5957 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5958 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5959 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5960 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5961 DAG.getConstant(CnstVal, dl, MVT::i32),
5962 DAG.getConstant(0, dl, MVT::i32));
5963 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5966 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5967 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5968 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5969 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5970 DAG.getConstant(CnstVal, dl, MVT::i32),
5971 DAG.getConstant(8, dl, MVT::i32));
5972 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5975 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5976 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5977 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5978 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5979 DAG.getConstant(CnstVal, dl, MVT::i32),
5980 DAG.getConstant(16, dl, MVT::i32));
5981 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5984 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5985 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5986 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5987 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5988 DAG.getConstant(CnstVal, dl, MVT::i32),
5989 DAG.getConstant(24, dl, MVT::i32));
5990 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5993 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5994 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5995 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5996 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5997 DAG.getConstant(CnstVal, dl, MVT::i32),
5998 DAG.getConstant(0, dl, MVT::i32));
5999 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6002 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6003 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6004 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6005 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
6006 DAG.getConstant(CnstVal, dl, MVT::i32),
6007 DAG.getConstant(8, dl, MVT::i32));
6008 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6015 CnstBits = ~UndefBits;
6019 // We can always fall back to a non-immediate AND.
6024 // Specialized code to quickly find if PotentialBVec is a BuildVector that
6025 // consists of only the same constant int value, returned in reference arg
6027 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
6028 uint64_t &ConstVal) {
6029 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
6032 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
6035 EVT VT = Bvec->getValueType(0);
6036 unsigned NumElts = VT.getVectorNumElements();
6037 for (unsigned i = 1; i < NumElts; ++i)
6038 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
6040 ConstVal = FirstElt->getZExtValue();
6044 static unsigned getIntrinsicID(const SDNode *N) {
6045 unsigned Opcode = N->getOpcode();
6048 return Intrinsic::not_intrinsic;
6049 case ISD::INTRINSIC_WO_CHAIN: {
6050 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6051 if (IID < Intrinsic::num_intrinsics)
6053 return Intrinsic::not_intrinsic;
6058 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
6059 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
6060 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
6061 // Also, logical shift right -> sri, with the same structure.
6062 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
6063 EVT VT = N->getValueType(0);
6070 // Is the first op an AND?
6071 const SDValue And = N->getOperand(0);
6072 if (And.getOpcode() != ISD::AND)
6075 // Is the second op an shl or lshr?
6076 SDValue Shift = N->getOperand(1);
6077 // This will have been turned into: AArch64ISD::VSHL vector, #shift
6078 // or AArch64ISD::VLSHR vector, #shift
6079 unsigned ShiftOpc = Shift.getOpcode();
6080 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
6082 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
6084 // Is the shift amount constant?
6085 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
6089 // Is the and mask vector all constant?
6091 if (!isAllConstantBuildVector(And.getOperand(1), C1))
6094 // Is C1 == ~C2, taking into account how much one can shift elements of a
6096 uint64_t C2 = C2node->getZExtValue();
6097 unsigned ElemSizeInBits = VT.getScalarSizeInBits();
6098 if (C2 > ElemSizeInBits)
6100 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
6101 if ((C1 & ElemMask) != (~C2 & ElemMask))
6104 SDValue X = And.getOperand(0);
6105 SDValue Y = Shift.getOperand(0);
6108 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
6110 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6111 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
6112 Shift.getOperand(1));
6114 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
6115 DEBUG(N->dump(&DAG));
6116 DEBUG(dbgs() << "into: \n");
6117 DEBUG(ResultSLI->dump(&DAG));
6123 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
6124 SelectionDAG &DAG) const {
6125 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
6126 if (EnableAArch64SlrGeneration) {
6127 if (SDValue Res = tryLowerToSLI(Op.getNode(), DAG))
6131 BuildVectorSDNode *BVN =
6132 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
6133 SDValue LHS = Op.getOperand(1);
6135 EVT VT = Op.getValueType();
6137 // OR commutes, so try swapping the operands.
6139 LHS = Op.getOperand(0);
6140 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
6145 APInt CnstBits(VT.getSizeInBits(), 0);
6146 APInt UndefBits(VT.getSizeInBits(), 0);
6147 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
6148 // We make use of a little bit of goto ickiness in order to avoid having to
6149 // duplicate the immediate matching logic for the undef toggled case.
6150 bool SecondTry = false;
6153 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
6154 CnstBits = CnstBits.zextOrTrunc(64);
6155 uint64_t CnstVal = CnstBits.getZExtValue();
6157 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6158 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6159 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6160 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6161 DAG.getConstant(CnstVal, dl, MVT::i32),
6162 DAG.getConstant(0, dl, MVT::i32));
6163 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6166 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6167 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6168 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6169 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6170 DAG.getConstant(CnstVal, dl, MVT::i32),
6171 DAG.getConstant(8, dl, MVT::i32));
6172 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6175 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6176 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6177 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6178 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6179 DAG.getConstant(CnstVal, dl, MVT::i32),
6180 DAG.getConstant(16, dl, MVT::i32));
6181 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6184 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6185 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6186 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6187 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6188 DAG.getConstant(CnstVal, dl, MVT::i32),
6189 DAG.getConstant(24, dl, MVT::i32));
6190 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6193 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6194 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6195 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6196 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6197 DAG.getConstant(CnstVal, dl, MVT::i32),
6198 DAG.getConstant(0, dl, MVT::i32));
6199 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6202 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6203 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6204 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6205 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
6206 DAG.getConstant(CnstVal, dl, MVT::i32),
6207 DAG.getConstant(8, dl, MVT::i32));
6208 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6215 CnstBits = UndefBits;
6219 // We can always fall back to a non-immediate OR.
6224 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
6225 // be truncated to fit element width.
6226 static SDValue NormalizeBuildVector(SDValue Op,
6227 SelectionDAG &DAG) {
6228 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6230 EVT VT = Op.getValueType();
6231 EVT EltTy= VT.getVectorElementType();
6233 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
6236 SmallVector<SDValue, 16> Ops;
6237 for (SDValue Lane : Op->ops()) {
6238 if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
6239 APInt LowBits(EltTy.getSizeInBits(),
6240 CstLane->getZExtValue());
6241 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
6243 Ops.push_back(Lane);
6245 return DAG.getBuildVector(VT, dl, Ops);
6248 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
6249 SelectionDAG &DAG) const {
6251 EVT VT = Op.getValueType();
6252 Op = NormalizeBuildVector(Op, DAG);
6253 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
6255 APInt CnstBits(VT.getSizeInBits(), 0);
6256 APInt UndefBits(VT.getSizeInBits(), 0);
6257 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
6258 // We make use of a little bit of goto ickiness in order to avoid having to
6259 // duplicate the immediate matching logic for the undef toggled case.
6260 bool SecondTry = false;
6263 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
6264 CnstBits = CnstBits.zextOrTrunc(64);
6265 uint64_t CnstVal = CnstBits.getZExtValue();
6267 // Certain magic vector constants (used to express things like NOT
6268 // and NEG) are passed through unmodified. This allows codegen patterns
6269 // for these operations to match. Special-purpose patterns will lower
6270 // these immediates to MOVIs if it proves necessary.
6271 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
6274 // The many faces of MOVI...
6275 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
6276 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
6277 if (VT.getSizeInBits() == 128) {
6278 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
6279 DAG.getConstant(CnstVal, dl, MVT::i32));
6280 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6283 // Support the V64 version via subregister insertion.
6284 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
6285 DAG.getConstant(CnstVal, dl, MVT::i32));
6286 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6289 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6290 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6291 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6292 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6293 DAG.getConstant(CnstVal, dl, MVT::i32),
6294 DAG.getConstant(0, dl, MVT::i32));
6295 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6298 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6299 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6300 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6301 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6302 DAG.getConstant(CnstVal, dl, MVT::i32),
6303 DAG.getConstant(8, dl, MVT::i32));
6304 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6307 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6308 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6309 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6310 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6311 DAG.getConstant(CnstVal, dl, MVT::i32),
6312 DAG.getConstant(16, dl, MVT::i32));
6313 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6316 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6317 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6318 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6319 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6320 DAG.getConstant(CnstVal, dl, MVT::i32),
6321 DAG.getConstant(24, dl, MVT::i32));
6322 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6325 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6326 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6327 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6328 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6329 DAG.getConstant(CnstVal, dl, MVT::i32),
6330 DAG.getConstant(0, dl, MVT::i32));
6331 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6334 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6335 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6336 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6337 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
6338 DAG.getConstant(CnstVal, dl, MVT::i32),
6339 DAG.getConstant(8, dl, MVT::i32));
6340 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6343 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6344 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6345 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6346 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6347 DAG.getConstant(CnstVal, dl, MVT::i32),
6348 DAG.getConstant(264, dl, MVT::i32));
6349 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6352 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6353 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6354 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6355 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
6356 DAG.getConstant(CnstVal, dl, MVT::i32),
6357 DAG.getConstant(272, dl, MVT::i32));
6358 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6361 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
6362 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
6363 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6364 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
6365 DAG.getConstant(CnstVal, dl, MVT::i32));
6366 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6369 // The few faces of FMOV...
6370 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
6371 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
6372 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6373 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
6374 DAG.getConstant(CnstVal, dl, MVT::i32));
6375 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6378 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
6379 VT.getSizeInBits() == 128) {
6380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
6381 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
6382 DAG.getConstant(CnstVal, dl, MVT::i32));
6383 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6386 // The many faces of MVNI...
6388 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
6389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
6390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6391 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6392 DAG.getConstant(CnstVal, dl, MVT::i32),
6393 DAG.getConstant(0, dl, MVT::i32));
6394 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6397 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
6398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
6399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6400 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6401 DAG.getConstant(CnstVal, dl, MVT::i32),
6402 DAG.getConstant(8, dl, MVT::i32));
6403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6406 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
6407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
6408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6409 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6410 DAG.getConstant(CnstVal, dl, MVT::i32),
6411 DAG.getConstant(16, dl, MVT::i32));
6412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6415 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
6416 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
6417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6418 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6419 DAG.getConstant(CnstVal, dl, MVT::i32),
6420 DAG.getConstant(24, dl, MVT::i32));
6421 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6424 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
6425 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
6426 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6427 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6428 DAG.getConstant(CnstVal, dl, MVT::i32),
6429 DAG.getConstant(0, dl, MVT::i32));
6430 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6433 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
6434 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
6435 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6436 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
6437 DAG.getConstant(CnstVal, dl, MVT::i32),
6438 DAG.getConstant(8, dl, MVT::i32));
6439 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6442 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
6443 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
6444 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6445 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6446 DAG.getConstant(CnstVal, dl, MVT::i32),
6447 DAG.getConstant(264, dl, MVT::i32));
6448 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6451 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
6452 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
6453 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6454 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
6455 DAG.getConstant(CnstVal, dl, MVT::i32),
6456 DAG.getConstant(272, dl, MVT::i32));
6457 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6464 CnstBits = UndefBits;
6469 // Scan through the operands to find some interesting properties we can
6471 // 1) If only one value is used, we can use a DUP, or
6472 // 2) if only the low element is not undef, we can just insert that, or
6473 // 3) if only one constant value is used (w/ some non-constant lanes),
6474 // we can splat the constant value into the whole vector then fill
6475 // in the non-constant lanes.
6476 // 4) FIXME: If different constant values are used, but we can intelligently
6477 // select the values we'll be overwriting for the non-constant
6478 // lanes such that we can directly materialize the vector
6479 // some other way (MOVI, e.g.), we can be sneaky.
6480 unsigned NumElts = VT.getVectorNumElements();
6481 bool isOnlyLowElement = true;
6482 bool usesOnlyOneValue = true;
6483 bool usesOnlyOneConstantValue = true;
6484 bool isConstant = true;
6485 unsigned NumConstantLanes = 0;
6487 SDValue ConstantValue;
6488 for (unsigned i = 0; i < NumElts; ++i) {
6489 SDValue V = Op.getOperand(i);
6493 isOnlyLowElement = false;
6494 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
6497 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
6499 if (!ConstantValue.getNode())
6501 else if (ConstantValue != V)
6502 usesOnlyOneConstantValue = false;
6505 if (!Value.getNode())
6507 else if (V != Value)
6508 usesOnlyOneValue = false;
6511 if (!Value.getNode())
6512 return DAG.getUNDEF(VT);
6514 if (isOnlyLowElement)
6515 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6517 // Use DUP for non-constant splats. For f32 constant splats, reduce to
6518 // i32 and try again.
6519 if (usesOnlyOneValue) {
6521 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6522 Value.getValueType() != VT)
6523 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6525 // This is actually a DUPLANExx operation, which keeps everything vectory.
6527 // DUPLANE works on 128-bit vectors, widen it if necessary.
6528 SDValue Lane = Value.getOperand(1);
6529 Value = Value.getOperand(0);
6530 if (Value.getValueSizeInBits() == 64)
6531 Value = WidenVector(Value, DAG);
6533 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6534 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6537 if (VT.getVectorElementType().isFloatingPoint()) {
6538 SmallVector<SDValue, 8> Ops;
6539 EVT EltTy = VT.getVectorElementType();
6540 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
6541 "Unsupported floating-point vector type");
6542 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
6543 for (unsigned i = 0; i < NumElts; ++i)
6544 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
6545 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
6546 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops);
6547 Val = LowerBUILD_VECTOR(Val, DAG);
6549 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6553 // If there was only one constant value used and for more than one lane,
6554 // start by splatting that value, then replace the non-constant lanes. This
6555 // is better than the default, which will perform a separate initialization
6557 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
6558 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6559 // Now insert the non-constant lanes.
6560 for (unsigned i = 0; i < NumElts; ++i) {
6561 SDValue V = Op.getOperand(i);
6562 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6563 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
6564 // Note that type legalization likely mucked about with the VT of the
6565 // source operand, so we may have to convert it here before inserting.
6566 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6572 // If all elements are constants and the case above didn't get hit, fall back
6573 // to the default expansion, which will generate a load from the constant
6578 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
6580 if (SDValue shuffle = ReconstructShuffle(Op, DAG))
6584 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
6585 // know the default expansion would otherwise fall back on something even
6586 // worse. For a vector with one or two non-undef values, that's
6587 // scalar_to_vector for the elements followed by a shuffle (provided the
6588 // shuffle is valid for the target) and materialization element by element
6589 // on the stack followed by a load for everything else.
6590 if (!isConstant && !usesOnlyOneValue) {
6591 SDValue Vec = DAG.getUNDEF(VT);
6592 SDValue Op0 = Op.getOperand(0);
6593 unsigned ElemSize = VT.getScalarSizeInBits();
6595 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6596 // a) Avoid a RMW dependency on the full vector register, and
6597 // b) Allow the register coalescer to fold away the copy if the
6598 // value is already in an S or D register.
6599 // Do not do this for UNDEF/LOAD nodes because we have better patterns
6600 // for those avoiding the SCALAR_TO_VECTOR/BUILD_VECTOR.
6601 if (!Op0.isUndef() && Op0.getOpcode() != ISD::LOAD &&
6602 (ElemSize == 32 || ElemSize == 64)) {
6603 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6605 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6606 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6607 Vec = SDValue(N, 0);
6610 for (; i < NumElts; ++i) {
6611 SDValue V = Op.getOperand(i);
6614 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6615 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6620 // Just use the default expansion. We failed to find a better alternative.
6624 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6625 SelectionDAG &DAG) const {
6626 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6628 // Check for non-constant or out of range lane.
6629 EVT VT = Op.getOperand(0).getValueType();
6630 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6631 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6635 // Insertion/extraction are legal for V128 types.
6636 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6637 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6641 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6642 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6645 // For V64 types, we perform insertion by expanding the value
6646 // to a V128 type and perform the insertion on that.
6648 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6649 EVT WideTy = WideVec.getValueType();
6651 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6652 Op.getOperand(1), Op.getOperand(2));
6653 // Re-narrow the resultant vector.
6654 return NarrowVector(Node, DAG);
6658 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6659 SelectionDAG &DAG) const {
6660 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6662 // Check for non-constant or out of range lane.
6663 EVT VT = Op.getOperand(0).getValueType();
6664 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6665 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6669 // Insertion/extraction are legal for V128 types.
6670 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6671 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6675 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6676 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6679 // For V64 types, we perform extraction by expanding the value
6680 // to a V128 type and perform the extraction on that.
6682 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6683 EVT WideTy = WideVec.getValueType();
6685 EVT ExtrTy = WideTy.getVectorElementType();
6686 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6689 // For extractions, we just return the result directly.
6690 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6694 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6695 SelectionDAG &DAG) const {
6696 EVT VT = Op.getOperand(0).getValueType();
6702 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6705 unsigned Val = Cst->getZExtValue();
6707 unsigned Size = Op.getValueSizeInBits();
6709 // This will get lowered to an appropriate EXTRACT_SUBREG in ISel.
6713 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6715 if (Size == 64 && Val * VT.getScalarSizeInBits() == 64)
6721 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6723 if (VT.getVectorNumElements() == 4 &&
6724 (VT.is128BitVector() || VT.is64BitVector())) {
6725 unsigned PFIndexes[4];
6726 for (unsigned i = 0; i != 4; ++i) {
6730 PFIndexes[i] = M[i];
6733 // Compute the index in the perfect shuffle table.
6734 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6735 PFIndexes[2] * 9 + PFIndexes[3];
6736 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6737 unsigned Cost = (PFEntry >> 30);
6745 unsigned DummyUnsigned;
6747 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6748 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6749 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6750 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6751 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6752 isZIPMask(M, VT, DummyUnsigned) ||
6753 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6754 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6755 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6756 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6757 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6760 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6761 /// operand of a vector shift operation, where all the elements of the
6762 /// build_vector must have the same constant integer value.
6763 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6764 // Ignore bit_converts.
6765 while (Op.getOpcode() == ISD::BITCAST)
6766 Op = Op.getOperand(0);
6767 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6768 APInt SplatBits, SplatUndef;
6769 unsigned SplatBitSize;
6771 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6772 HasAnyUndefs, ElementBits) ||
6773 SplatBitSize > ElementBits)
6775 Cnt = SplatBits.getSExtValue();
6779 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6780 /// operand of a vector shift left operation. That value must be in the range:
6781 /// 0 <= Value < ElementBits for a left shift; or
6782 /// 0 <= Value <= ElementBits for a long left shift.
6783 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6784 assert(VT.isVector() && "vector shift count is not a vector type");
6785 int64_t ElementBits = VT.getScalarSizeInBits();
6786 if (!getVShiftImm(Op, ElementBits, Cnt))
6788 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6791 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6792 /// operand of a vector shift right operation. The value must be in the range:
6793 /// 1 <= Value <= ElementBits for a right shift; or
6794 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6795 assert(VT.isVector() && "vector shift count is not a vector type");
6796 int64_t ElementBits = VT.getScalarSizeInBits();
6797 if (!getVShiftImm(Op, ElementBits, Cnt))
6799 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6802 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6803 SelectionDAG &DAG) const {
6804 EVT VT = Op.getValueType();
6808 if (!Op.getOperand(1).getValueType().isVector())
6810 unsigned EltSize = VT.getScalarSizeInBits();
6812 switch (Op.getOpcode()) {
6814 llvm_unreachable("unexpected shift opcode");
6817 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6818 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6819 DAG.getConstant(Cnt, DL, MVT::i32));
6820 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6821 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6823 Op.getOperand(0), Op.getOperand(1));
6826 // Right shift immediate
6827 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6829 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6830 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6831 DAG.getConstant(Cnt, DL, MVT::i32));
6834 // Right shift register. Note, there is not a shift right register
6835 // instruction, but the shift left register instruction takes a signed
6836 // value, where negative numbers specify a right shift.
6837 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6838 : Intrinsic::aarch64_neon_ushl;
6839 // negate the shift amount
6840 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6841 SDValue NegShiftLeft =
6842 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6843 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6845 return NegShiftLeft;
6851 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6852 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6853 const SDLoc &dl, SelectionDAG &DAG) {
6854 EVT SrcVT = LHS.getValueType();
6855 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6856 "function only supposed to emit natural comparisons");
6858 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6859 APInt CnstBits(VT.getSizeInBits(), 0);
6860 APInt UndefBits(VT.getSizeInBits(), 0);
6861 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6862 bool IsZero = IsCnst && (CnstBits == 0);
6864 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6868 case AArch64CC::NE: {
6871 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6873 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6874 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6878 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6879 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6882 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6883 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6886 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6887 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6890 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6891 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6895 // If we ignore NaNs then we can use to the MI implementation.
6899 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6900 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6907 case AArch64CC::NE: {
6910 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6912 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6913 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6917 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6918 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6921 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6922 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6925 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6926 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6929 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6930 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6932 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6934 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6937 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6938 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6940 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6942 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6946 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6947 SelectionDAG &DAG) const {
6948 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6949 SDValue LHS = Op.getOperand(0);
6950 SDValue RHS = Op.getOperand(1);
6951 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6954 if (LHS.getValueType().getVectorElementType().isInteger()) {
6955 assert(LHS.getValueType() == RHS.getValueType());
6956 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6958 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6959 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6962 if (LHS.getValueType().getVectorElementType() == MVT::f16)
6965 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6966 LHS.getValueType().getVectorElementType() == MVT::f64);
6968 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6969 // clean. Some of them require two branches to implement.
6970 AArch64CC::CondCode CC1, CC2;
6972 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6974 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6976 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6980 if (CC2 != AArch64CC::AL) {
6982 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6983 if (!Cmp2.getNode())
6986 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6989 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6992 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6997 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6998 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6999 /// specified in the intrinsic calls.
7000 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7002 unsigned Intrinsic) const {
7003 auto &DL = I.getModule()->getDataLayout();
7004 switch (Intrinsic) {
7005 case Intrinsic::aarch64_neon_ld2:
7006 case Intrinsic::aarch64_neon_ld3:
7007 case Intrinsic::aarch64_neon_ld4:
7008 case Intrinsic::aarch64_neon_ld1x2:
7009 case Intrinsic::aarch64_neon_ld1x3:
7010 case Intrinsic::aarch64_neon_ld1x4:
7011 case Intrinsic::aarch64_neon_ld2lane:
7012 case Intrinsic::aarch64_neon_ld3lane:
7013 case Intrinsic::aarch64_neon_ld4lane:
7014 case Intrinsic::aarch64_neon_ld2r:
7015 case Intrinsic::aarch64_neon_ld3r:
7016 case Intrinsic::aarch64_neon_ld4r: {
7017 Info.opc = ISD::INTRINSIC_W_CHAIN;
7018 // Conservatively set memVT to the entire set of vectors loaded.
7019 uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
7020 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7021 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
7024 Info.vol = false; // volatile loads with NEON intrinsics not supported
7025 Info.readMem = true;
7026 Info.writeMem = false;
7029 case Intrinsic::aarch64_neon_st2:
7030 case Intrinsic::aarch64_neon_st3:
7031 case Intrinsic::aarch64_neon_st4:
7032 case Intrinsic::aarch64_neon_st1x2:
7033 case Intrinsic::aarch64_neon_st1x3:
7034 case Intrinsic::aarch64_neon_st1x4:
7035 case Intrinsic::aarch64_neon_st2lane:
7036 case Intrinsic::aarch64_neon_st3lane:
7037 case Intrinsic::aarch64_neon_st4lane: {
7038 Info.opc = ISD::INTRINSIC_VOID;
7039 // Conservatively set memVT to the entire set of vectors stored.
7040 unsigned NumElts = 0;
7041 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7042 Type *ArgTy = I.getArgOperand(ArgI)->getType();
7043 if (!ArgTy->isVectorTy())
7045 NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
7047 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7048 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
7051 Info.vol = false; // volatile stores with NEON intrinsics not supported
7052 Info.readMem = false;
7053 Info.writeMem = true;
7056 case Intrinsic::aarch64_ldaxr:
7057 case Intrinsic::aarch64_ldxr: {
7058 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
7059 Info.opc = ISD::INTRINSIC_W_CHAIN;
7060 Info.memVT = MVT::getVT(PtrTy->getElementType());
7061 Info.ptrVal = I.getArgOperand(0);
7063 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
7065 Info.readMem = true;
7066 Info.writeMem = false;
7069 case Intrinsic::aarch64_stlxr:
7070 case Intrinsic::aarch64_stxr: {
7071 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
7072 Info.opc = ISD::INTRINSIC_W_CHAIN;
7073 Info.memVT = MVT::getVT(PtrTy->getElementType());
7074 Info.ptrVal = I.getArgOperand(1);
7076 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
7078 Info.readMem = false;
7079 Info.writeMem = true;
7082 case Intrinsic::aarch64_ldaxp:
7083 case Intrinsic::aarch64_ldxp:
7084 Info.opc = ISD::INTRINSIC_W_CHAIN;
7085 Info.memVT = MVT::i128;
7086 Info.ptrVal = I.getArgOperand(0);
7090 Info.readMem = true;
7091 Info.writeMem = false;
7093 case Intrinsic::aarch64_stlxp:
7094 case Intrinsic::aarch64_stxp:
7095 Info.opc = ISD::INTRINSIC_W_CHAIN;
7096 Info.memVT = MVT::i128;
7097 Info.ptrVal = I.getArgOperand(2);
7101 Info.readMem = false;
7102 Info.writeMem = true;
7111 // Truncations from 64-bit GPR to 32-bit GPR is free.
7112 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
7113 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7115 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7116 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7117 return NumBits1 > NumBits2;
7119 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7120 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
7122 unsigned NumBits1 = VT1.getSizeInBits();
7123 unsigned NumBits2 = VT2.getSizeInBits();
7124 return NumBits1 > NumBits2;
7127 /// Check if it is profitable to hoist instruction in then/else to if.
7128 /// Not profitable if I and it's user can form a FMA instruction
7129 /// because we prefer FMSUB/FMADD.
7130 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
7131 if (I->getOpcode() != Instruction::FMul)
7134 if (I->getNumUses() != 1)
7137 Instruction *User = I->user_back();
7140 !(User->getOpcode() == Instruction::FSub ||
7141 User->getOpcode() == Instruction::FAdd))
7144 const TargetOptions &Options = getTargetMachine().Options;
7145 const DataLayout &DL = I->getModule()->getDataLayout();
7146 EVT VT = getValueType(DL, User->getOperand(0)->getType());
7148 return !(isFMAFasterThanFMulAndFAdd(VT) &&
7149 isOperationLegalOrCustom(ISD::FMA, VT) &&
7150 (Options.AllowFPOpFusion == FPOpFusion::Fast ||
7151 Options.UnsafeFPMath));
7154 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
7156 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
7157 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7159 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7160 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7161 return NumBits1 == 32 && NumBits2 == 64;
7163 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7164 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
7166 unsigned NumBits1 = VT1.getSizeInBits();
7167 unsigned NumBits2 = VT2.getSizeInBits();
7168 return NumBits1 == 32 && NumBits2 == 64;
7171 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
7172 EVT VT1 = Val.getValueType();
7173 if (isZExtFree(VT1, VT2)) {
7177 if (Val.getOpcode() != ISD::LOAD)
7180 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
7181 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
7182 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
7183 VT1.getSizeInBits() <= 32);
7186 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
7187 if (isa<FPExtInst>(Ext))
7190 // Vector types are next free.
7191 if (Ext->getType()->isVectorTy())
7194 for (const Use &U : Ext->uses()) {
7195 // The extension is free if we can fold it with a left shift in an
7196 // addressing mode or an arithmetic operation: add, sub, and cmp.
7198 // Is there a shift?
7199 const Instruction *Instr = cast<Instruction>(U.getUser());
7201 // Is this a constant shift?
7202 switch (Instr->getOpcode()) {
7203 case Instruction::Shl:
7204 if (!isa<ConstantInt>(Instr->getOperand(1)))
7207 case Instruction::GetElementPtr: {
7208 gep_type_iterator GTI = gep_type_begin(Instr);
7209 auto &DL = Ext->getModule()->getDataLayout();
7210 std::advance(GTI, U.getOperandNo()-1);
7211 Type *IdxTy = GTI.getIndexedType();
7212 // This extension will end up with a shift because of the scaling factor.
7213 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
7214 // Get the shift amount based on the scaling factor:
7215 // log2(sizeof(IdxTy)) - log2(8).
7217 countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy)) - 3;
7218 // Is the constant foldable in the shift of the addressing mode?
7219 // I.e., shift amount is between 1 and 4 inclusive.
7220 if (ShiftAmt == 0 || ShiftAmt > 4)
7224 case Instruction::Trunc:
7225 // Check if this is a noop.
7226 // trunc(sext ty1 to ty2) to ty1.
7227 if (Instr->getType() == Ext->getOperand(0)->getType())
7234 // At this point we can use the bfm family, so this extension is free
7240 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
7241 unsigned &RequiredAligment) const {
7242 if (!LoadedType.isSimple() ||
7243 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
7245 // Cyclone supports unaligned accesses.
7246 RequiredAligment = 0;
7247 unsigned NumBits = LoadedType.getSizeInBits();
7248 return NumBits == 32 || NumBits == 64;
7251 /// \brief Lower an interleaved load into a ldN intrinsic.
7253 /// E.g. Lower an interleaved load (Factor = 2):
7254 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
7255 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
7256 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
7259 /// %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
7260 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
7261 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
7262 bool AArch64TargetLowering::lowerInterleavedLoad(
7263 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
7264 ArrayRef<unsigned> Indices, unsigned Factor) const {
7265 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7266 "Invalid interleave factor");
7267 assert(!Shuffles.empty() && "Empty shufflevector input");
7268 assert(Shuffles.size() == Indices.size() &&
7269 "Unmatched number of shufflevectors and indices");
7271 const DataLayout &DL = LI->getModule()->getDataLayout();
7273 VectorType *VecTy = Shuffles[0]->getType();
7274 unsigned VecSize = DL.getTypeSizeInBits(VecTy);
7276 // Skip if we do not have NEON and skip illegal vector types.
7277 if (!Subtarget->hasNEON() || (VecSize != 64 && VecSize != 128))
7280 // A pointer vector can not be the return type of the ldN intrinsics. Need to
7281 // load integer vectors first and then convert to pointer vectors.
7282 Type *EltTy = VecTy->getVectorElementType();
7283 if (EltTy->isPointerTy())
7285 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
7287 Type *PtrTy = VecTy->getPointerTo(LI->getPointerAddressSpace());
7288 Type *Tys[2] = {VecTy, PtrTy};
7289 static const Intrinsic::ID LoadInts[3] = {Intrinsic::aarch64_neon_ld2,
7290 Intrinsic::aarch64_neon_ld3,
7291 Intrinsic::aarch64_neon_ld4};
7293 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
7295 IRBuilder<> Builder(LI);
7296 Value *Ptr = Builder.CreateBitCast(LI->getPointerOperand(), PtrTy);
7298 CallInst *LdN = Builder.CreateCall(LdNFunc, Ptr, "ldN");
7300 // Replace uses of each shufflevector with the corresponding vector loaded
7302 for (unsigned i = 0; i < Shuffles.size(); i++) {
7303 ShuffleVectorInst *SVI = Shuffles[i];
7304 unsigned Index = Indices[i];
7306 Value *SubVec = Builder.CreateExtractValue(LdN, Index);
7308 // Convert the integer vector to pointer vector if the element is pointer.
7309 if (EltTy->isPointerTy())
7310 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType());
7312 SVI->replaceAllUsesWith(SubVec);
7318 /// \brief Get a mask consisting of sequential integers starting from \p Start.
7320 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
7321 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
7323 SmallVector<Constant *, 16> Mask;
7324 for (unsigned i = 0; i < NumElts; i++)
7325 Mask.push_back(Builder.getInt32(Start + i));
7327 return ConstantVector::get(Mask);
7330 /// \brief Lower an interleaved store into a stN intrinsic.
7332 /// E.g. Lower an interleaved store (Factor = 3):
7333 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
7334 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
7335 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7338 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7339 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7340 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7341 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7343 /// Note that the new shufflevectors will be removed and we'll only generate one
7344 /// st3 instruction in CodeGen.
7346 /// Example for a more general valid mask (Factor 3). Lower:
7347 /// %i.vec = shuffle <32 x i32> %v0, <32 x i32> %v1,
7348 /// <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19>
7349 /// store <12 x i32> %i.vec, <12 x i32>* %ptr
7352 /// %sub.v0 = shuffle <32 x i32> %v0, <32 x i32> v1, <4, 5, 6, 7>
7353 /// %sub.v1 = shuffle <32 x i32> %v0, <32 x i32> v1, <32, 33, 34, 35>
7354 /// %sub.v2 = shuffle <32 x i32> %v0, <32 x i32> v1, <16, 17, 18, 19>
7355 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7356 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7357 ShuffleVectorInst *SVI,
7358 unsigned Factor) const {
7359 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
7360 "Invalid interleave factor");
7362 VectorType *VecTy = SVI->getType();
7363 assert(VecTy->getVectorNumElements() % Factor == 0 &&
7364 "Invalid interleaved store");
7366 unsigned LaneLen = VecTy->getVectorNumElements() / Factor;
7367 Type *EltTy = VecTy->getVectorElementType();
7368 VectorType *SubVecTy = VectorType::get(EltTy, LaneLen);
7370 const DataLayout &DL = SI->getModule()->getDataLayout();
7371 unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
7373 // Skip if we do not have NEON and skip illegal vector types.
7374 if (!Subtarget->hasNEON() || (SubVecSize != 64 && SubVecSize != 128))
7377 Value *Op0 = SVI->getOperand(0);
7378 Value *Op1 = SVI->getOperand(1);
7379 IRBuilder<> Builder(SI);
7381 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
7382 // vectors to integer vectors.
7383 if (EltTy->isPointerTy()) {
7384 Type *IntTy = DL.getIntPtrType(EltTy);
7385 unsigned NumOpElts =
7386 dyn_cast<VectorType>(Op0->getType())->getVectorNumElements();
7388 // Convert to the corresponding integer vector.
7389 Type *IntVecTy = VectorType::get(IntTy, NumOpElts);
7390 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
7391 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
7393 SubVecTy = VectorType::get(IntTy, LaneLen);
7396 Type *PtrTy = SubVecTy->getPointerTo(SI->getPointerAddressSpace());
7397 Type *Tys[2] = {SubVecTy, PtrTy};
7398 static const Intrinsic::ID StoreInts[3] = {Intrinsic::aarch64_neon_st2,
7399 Intrinsic::aarch64_neon_st3,
7400 Intrinsic::aarch64_neon_st4};
7402 Intrinsic::getDeclaration(SI->getModule(), StoreInts[Factor - 2], Tys);
7404 SmallVector<Value *, 5> Ops;
7406 // Split the shufflevector operands into sub vectors for the new stN call.
7407 auto Mask = SVI->getShuffleMask();
7408 for (unsigned i = 0; i < Factor; i++) {
7410 Ops.push_back(Builder.CreateShuffleVector(
7411 Op0, Op1, getSequentialMask(Builder, Mask[i], LaneLen)));
7413 unsigned StartMask = 0;
7414 for (unsigned j = 1; j < LaneLen; j++) {
7415 if (Mask[j*Factor + i] >= 0) {
7416 StartMask = Mask[j*Factor + i] - j;
7420 // Note: If all elements in a chunk are undefs, StartMask=0!
7421 // Note: Filling undef gaps with random elements is ok, since
7422 // those elements were being written anyway (with undefs).
7423 // In the case of all undefs we're defaulting to using elems from 0
7424 // Note: StartMask cannot be negative, it's checked in isReInterleaveMask
7425 Ops.push_back(Builder.CreateShuffleVector(
7426 Op0, Op1, getSequentialMask(Builder, StartMask, LaneLen)));
7430 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), PtrTy));
7431 Builder.CreateCall(StNFunc, Ops);
7435 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
7436 unsigned AlignCheck) {
7437 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
7438 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7441 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7442 unsigned SrcAlign, bool IsMemset,
7445 MachineFunction &MF) const {
7446 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
7447 // instruction to materialize the v2i64 zero and one store (with restrictive
7448 // addressing mode). Just do two i64 store of zero-registers.
7450 const Function *F = MF.getFunction();
7451 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
7452 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
7453 (memOpAlign(SrcAlign, DstAlign, 16) ||
7454 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
7458 (memOpAlign(SrcAlign, DstAlign, 8) ||
7459 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
7463 (memOpAlign(SrcAlign, DstAlign, 4) ||
7464 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
7470 // 12-bit optionally shifted immediates are legal for adds.
7471 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7472 // Avoid UB for INT64_MIN.
7473 if (Immed == std::numeric_limits<int64_t>::min())
7475 // Same encoding for add/sub, just flip the sign.
7476 Immed = std::abs(Immed);
7477 return ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0));
7480 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
7481 // immediates is the same as for an add or a sub.
7482 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7483 return isLegalAddImmediate(Immed);
7486 /// isLegalAddressingMode - Return true if the addressing mode represented
7487 /// by AM is legal for this target, for a load/store of the specified type.
7488 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7489 const AddrMode &AM, Type *Ty,
7490 unsigned AS) const {
7491 // AArch64 has five basic addressing modes:
7493 // reg + 9-bit signed offset
7494 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
7496 // reg + SIZE_IN_BYTES * reg
7498 // No global is ever allowed as a base.
7502 // No reg+reg+imm addressing.
7503 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
7506 // check reg + imm case:
7507 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
7508 uint64_t NumBytes = 0;
7509 if (Ty->isSized()) {
7510 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
7511 NumBytes = NumBits / 8;
7512 if (!isPowerOf2_64(NumBits))
7517 int64_t Offset = AM.BaseOffs;
7519 // 9-bit signed offset
7520 if (isInt<9>(Offset))
7523 // 12-bit unsigned offset
7524 unsigned shift = Log2_64(NumBytes);
7525 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
7526 // Must be a multiple of NumBytes (NumBytes is a power of 2)
7527 (Offset >> shift) << shift == Offset)
7532 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
7534 return AM.Scale == 1 || (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes);
7537 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7538 const AddrMode &AM, Type *Ty,
7539 unsigned AS) const {
7540 // Scaling factors are not free at all.
7541 // Operands | Rt Latency
7542 // -------------------------------------------
7544 // -------------------------------------------
7545 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
7546 // Rt, [Xn, Wm, <extend> #imm] |
7547 if (isLegalAddressingMode(DL, AM, Ty, AS))
7548 // Scale represents reg2 * scale, thus account for 1 if
7549 // it is not equal to 0 or 1.
7550 return AM.Scale != 0 && AM.Scale != 1;
7554 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7555 VT = VT.getScalarType();
7560 switch (VT.getSimpleVT().SimpleTy) {
7572 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7573 // LR is a callee-save register, but we must treat it as clobbered by any call
7574 // site. Hence we include LR in the scratch registers, which are in turn added
7575 // as implicit-defs for stackmaps and patchpoints.
7576 static const MCPhysReg ScratchRegs[] = {
7577 AArch64::X16, AArch64::X17, AArch64::LR, 0
7583 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7584 EVT VT = N->getValueType(0);
7585 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
7586 // it with shift to let it be lowered to UBFX.
7587 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7588 isa<ConstantSDNode>(N->getOperand(1))) {
7589 uint64_t TruncMask = N->getConstantOperandVal(1);
7590 if (isMask_64(TruncMask) &&
7591 N->getOperand(0).getOpcode() == ISD::SRL &&
7592 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
7598 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7600 assert(Ty->isIntegerTy());
7602 unsigned BitSize = Ty->getPrimitiveSizeInBits();
7606 int64_t Val = Imm.getSExtValue();
7607 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
7610 if ((int64_t)Val < 0)
7613 Val &= (1LL << 32) - 1;
7615 unsigned LZ = countLeadingZeros((uint64_t)Val);
7616 unsigned Shift = (63 - LZ) / 16;
7617 // MOVZ is free so return true for one or fewer MOVK.
7621 /// Turn vector tests of the signbit in the form of:
7622 /// xor (sra X, elt_size(X)-1), -1
7625 static SDValue foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG,
7626 const AArch64Subtarget *Subtarget) {
7627 EVT VT = N->getValueType(0);
7628 if (!Subtarget->hasNEON() || !VT.isVector())
7631 // There must be a shift right algebraic before the xor, and the xor must be a
7633 SDValue Shift = N->getOperand(0);
7634 SDValue Ones = N->getOperand(1);
7635 if (Shift.getOpcode() != AArch64ISD::VASHR || !Shift.hasOneUse() ||
7636 !ISD::isBuildVectorAllOnes(Ones.getNode()))
7639 // The shift should be smearing the sign bit across each vector element.
7640 auto *ShiftAmt = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
7641 EVT ShiftEltTy = Shift.getValueType().getVectorElementType();
7642 if (!ShiftAmt || ShiftAmt->getZExtValue() != ShiftEltTy.getSizeInBits() - 1)
7645 return DAG.getNode(AArch64ISD::CMGEz, SDLoc(N), VT, Shift.getOperand(0));
7648 // Generate SUBS and CSEL for integer abs.
7649 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
7650 EVT VT = N->getValueType(0);
7652 SDValue N0 = N->getOperand(0);
7653 SDValue N1 = N->getOperand(1);
7656 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7657 // and change it to SUB and CSEL.
7658 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7659 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7660 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7661 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
7662 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7663 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7665 // Generate SUBS & CSEL.
7667 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7668 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7669 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7670 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
7671 SDValue(Cmp.getNode(), 1));
7676 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
7677 TargetLowering::DAGCombinerInfo &DCI,
7678 const AArch64Subtarget *Subtarget) {
7679 if (DCI.isBeforeLegalizeOps())
7682 if (SDValue Cmp = foldVectorXorShiftIntoCmp(N, DAG, Subtarget))
7685 return performIntegerAbsCombine(N, DAG);
7689 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7691 std::vector<SDNode *> *Created) const {
7692 AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();
7693 if (isIntDivCheap(N->getValueType(0), Attr))
7694 return SDValue(N,0); // Lower SDIV as SDIV
7696 // fold (sdiv X, pow2)
7697 EVT VT = N->getValueType(0);
7698 if ((VT != MVT::i32 && VT != MVT::i64) ||
7699 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7703 SDValue N0 = N->getOperand(0);
7704 unsigned Lg2 = Divisor.countTrailingZeros();
7705 SDValue Zero = DAG.getConstant(0, DL, VT);
7706 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7708 // Add (N0 < 0) ? Pow2 - 1 : 0;
7710 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
7711 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7712 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7715 Created->push_back(Cmp.getNode());
7716 Created->push_back(Add.getNode());
7717 Created->push_back(CSel.getNode());
7722 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7724 // If we're dividing by a positive value, we're done. Otherwise, we must
7725 // negate the result.
7726 if (Divisor.isNonNegative())
7730 Created->push_back(SRA.getNode());
7731 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7734 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
7735 TargetLowering::DAGCombinerInfo &DCI,
7736 const AArch64Subtarget *Subtarget) {
7737 if (DCI.isBeforeLegalizeOps())
7740 // The below optimizations require a constant RHS.
7741 if (!isa<ConstantSDNode>(N->getOperand(1)))
7744 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
7745 const APInt &ConstValue = C->getAPIntValue();
7747 // Multiplication of a power of two plus/minus one can be done more
7748 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7749 // future CPUs have a cheaper MADD instruction, this may need to be
7750 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
7751 // 64-bit is 5 cycles, so this is always a win.
7752 // More aggressively, some multiplications N0 * C can be lowered to
7753 // shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
7754 // e.g. 6=3*2=(2+1)*2.
7755 // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
7756 // which equals to (1+2)*16-(1+2).
7757 SDValue N0 = N->getOperand(0);
7758 // TrailingZeroes is used to test if the mul can be lowered to
7760 unsigned TrailingZeroes = ConstValue.countTrailingZeros();
7761 if (TrailingZeroes) {
7762 // Conservatively do not lower to shift+add+shift if the mul might be
7763 // folded into smul or umul.
7764 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) ||
7765 isZeroExtended(N0.getNode(), DAG)))
7767 // Conservatively do not lower to shift+add+shift if the mul might be
7768 // folded into madd or msub.
7769 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
7770 N->use_begin()->getOpcode() == ISD::SUB))
7773 // Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
7774 // and shift+add+shift.
7775 APInt ShiftedConstValue = ConstValue.ashr(TrailingZeroes);
7777 unsigned ShiftAmt, AddSubOpc;
7778 // Is the shifted value the LHS operand of the add/sub?
7779 bool ShiftValUseIsN0 = true;
7780 // Do we need to negate the result?
7781 bool NegateResult = false;
7783 if (ConstValue.isNonNegative()) {
7784 // (mul x, 2^N + 1) => (add (shl x, N), x)
7785 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7786 // (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
7787 APInt SCVMinus1 = ShiftedConstValue - 1;
7788 APInt CVPlus1 = ConstValue + 1;
7789 if (SCVMinus1.isPowerOf2()) {
7790 ShiftAmt = SCVMinus1.logBase2();
7791 AddSubOpc = ISD::ADD;
7792 } else if (CVPlus1.isPowerOf2()) {
7793 ShiftAmt = CVPlus1.logBase2();
7794 AddSubOpc = ISD::SUB;
7798 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7799 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7800 APInt CVNegPlus1 = -ConstValue + 1;
7801 APInt CVNegMinus1 = -ConstValue - 1;
7802 if (CVNegPlus1.isPowerOf2()) {
7803 ShiftAmt = CVNegPlus1.logBase2();
7804 AddSubOpc = ISD::SUB;
7805 ShiftValUseIsN0 = false;
7806 } else if (CVNegMinus1.isPowerOf2()) {
7807 ShiftAmt = CVNegMinus1.logBase2();
7808 AddSubOpc = ISD::ADD;
7809 NegateResult = true;
7815 EVT VT = N->getValueType(0);
7816 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0,
7817 DAG.getConstant(ShiftAmt, DL, MVT::i64));
7819 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0;
7820 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal;
7821 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1);
7822 assert(!(NegateResult && TrailingZeroes) &&
7823 "NegateResult and TrailingZeroes cannot both be true for now.");
7824 // Negate the result.
7826 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res);
7827 // Shift the result.
7829 return DAG.getNode(ISD::SHL, DL, VT, Res,
7830 DAG.getConstant(TrailingZeroes, DL, MVT::i64));
7834 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7835 SelectionDAG &DAG) {
7836 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7837 // optimize away operation when it's from a constant.
7839 // The general transformation is:
7840 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7841 // AND(VECTOR_CMP(x,y), constant2)
7842 // constant2 = UNARYOP(constant)
7844 // Early exit if this isn't a vector operation, the operand of the
7845 // unary operation isn't a bitwise AND, or if the sizes of the operations
7847 EVT VT = N->getValueType(0);
7848 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7849 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7850 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7853 // Now check that the other operand of the AND is a constant. We could
7854 // make the transformation for non-constant splats as well, but it's unclear
7855 // that would be a benefit as it would not eliminate any operations, just
7856 // perform one more step in scalar code before moving to the vector unit.
7857 if (BuildVectorSDNode *BV =
7858 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7859 // Bail out if the vector isn't a constant.
7860 if (!BV->isConstant())
7863 // Everything checks out. Build up the new and improved node.
7865 EVT IntVT = BV->getValueType(0);
7866 // Create a new constant of the appropriate type for the transformed
7868 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7869 // The AND node needs bitcasts to/from an integer vector type around it.
7870 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7871 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7872 N->getOperand(0)->getOperand(0), MaskConst);
7873 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7880 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7881 const AArch64Subtarget *Subtarget) {
7882 // First try to optimize away the conversion when it's conditionally from
7883 // a constant. Vectors only.
7884 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
7887 EVT VT = N->getValueType(0);
7888 if (VT != MVT::f32 && VT != MVT::f64)
7891 // Only optimize when the source and destination types have the same width.
7892 if (VT.getSizeInBits() != N->getOperand(0).getValueSizeInBits())
7895 // If the result of an integer load is only used by an integer-to-float
7896 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7897 // This eliminates an "integer-to-vector-move" UOP and improves throughput.
7898 SDValue N0 = N->getOperand(0);
7899 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7900 // Do not change the width of a volatile load.
7901 !cast<LoadSDNode>(N0)->isVolatile()) {
7902 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7903 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7904 LN0->getPointerInfo(), LN0->getAlignment(),
7905 LN0->getMemOperand()->getFlags());
7907 // Make sure successors of the original load stay after it by updating them
7908 // to use the new Chain.
7909 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7912 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7913 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7919 /// Fold a floating-point multiply by power of two into floating-point to
7920 /// fixed-point conversion.
7921 static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
7922 TargetLowering::DAGCombinerInfo &DCI,
7923 const AArch64Subtarget *Subtarget) {
7924 if (!Subtarget->hasNEON())
7927 SDValue Op = N->getOperand(0);
7928 if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
7929 Op.getOpcode() != ISD::FMUL)
7932 SDValue ConstVec = Op->getOperand(1);
7933 if (!isa<BuildVectorSDNode>(ConstVec))
7936 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
7937 uint32_t FloatBits = FloatTy.getSizeInBits();
7938 if (FloatBits != 32 && FloatBits != 64)
7941 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
7942 uint32_t IntBits = IntTy.getSizeInBits();
7943 if (IntBits != 16 && IntBits != 32 && IntBits != 64)
7946 // Avoid conversions where iN is larger than the float (e.g., float -> i64).
7947 if (IntBits > FloatBits)
7950 BitVector UndefElements;
7951 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
7952 int32_t Bits = IntBits == 64 ? 64 : 32;
7953 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, Bits + 1);
7954 if (C == -1 || C == 0 || C > Bits)
7958 unsigned NumLanes = Op.getValueType().getVectorNumElements();
7963 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
7966 ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
7970 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
7973 assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) &&
7974 "Illegal vector type after legalization");
7977 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
7978 unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs
7979 : Intrinsic::aarch64_neon_vcvtfp2fxu;
7981 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResTy,
7982 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32),
7983 Op->getOperand(0), DAG.getConstant(C, DL, MVT::i32));
7984 // We can handle smaller integers by generating an extra trunc.
7985 if (IntBits < FloatBits)
7986 FixConv = DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), FixConv);
7991 /// Fold a floating-point divide by power of two into fixed-point to
7992 /// floating-point conversion.
7993 static SDValue performFDivCombine(SDNode *N, SelectionDAG &DAG,
7994 TargetLowering::DAGCombinerInfo &DCI,
7995 const AArch64Subtarget *Subtarget) {
7996 if (!Subtarget->hasNEON())
7999 SDValue Op = N->getOperand(0);
8000 unsigned Opc = Op->getOpcode();
8001 if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
8002 !Op.getOperand(0).getValueType().isSimple() ||
8003 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP))
8006 SDValue ConstVec = N->getOperand(1);
8007 if (!isa<BuildVectorSDNode>(ConstVec))
8010 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
8011 int32_t IntBits = IntTy.getSizeInBits();
8012 if (IntBits != 16 && IntBits != 32 && IntBits != 64)
8015 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
8016 int32_t FloatBits = FloatTy.getSizeInBits();
8017 if (FloatBits != 32 && FloatBits != 64)
8020 // Avoid conversions where iN is larger than the float (e.g., i64 -> float).
8021 if (IntBits > FloatBits)
8024 BitVector UndefElements;
8025 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
8026 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, FloatBits + 1);
8027 if (C == -1 || C == 0 || C > FloatBits)
8031 unsigned NumLanes = Op.getValueType().getVectorNumElements();
8036 ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
8039 ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
8043 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
8047 SDValue ConvInput = Op.getOperand(0);
8048 bool IsSigned = Opc == ISD::SINT_TO_FP;
8049 if (IntBits < FloatBits)
8050 ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
8053 unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfxs2fp
8054 : Intrinsic::aarch64_neon_vcvtfxu2fp;
8055 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
8056 DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), ConvInput,
8057 DAG.getConstant(C, DL, MVT::i32));
8060 /// An EXTR instruction is made up of two shifts, ORed together. This helper
8061 /// searches for and classifies those shifts.
8062 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
8064 if (N.getOpcode() == ISD::SHL)
8066 else if (N.getOpcode() == ISD::SRL)
8071 if (!isa<ConstantSDNode>(N.getOperand(1)))
8074 ShiftAmount = N->getConstantOperandVal(1);
8075 Src = N->getOperand(0);
8079 /// EXTR instruction extracts a contiguous chunk of bits from two existing
8080 /// registers viewed as a high/low pair. This function looks for the pattern:
8081 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
8082 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
8084 static SDValue tryCombineToEXTR(SDNode *N,
8085 TargetLowering::DAGCombinerInfo &DCI) {
8086 SelectionDAG &DAG = DCI.DAG;
8088 EVT VT = N->getValueType(0);
8090 assert(N->getOpcode() == ISD::OR && "Unexpected root");
8092 if (VT != MVT::i32 && VT != MVT::i64)
8096 uint32_t ShiftLHS = 0;
8097 bool LHSFromHi = false;
8098 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
8102 uint32_t ShiftRHS = 0;
8103 bool RHSFromHi = false;
8104 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
8107 // If they're both trying to come from the high part of the register, they're
8108 // not really an EXTR.
8109 if (LHSFromHi == RHSFromHi)
8112 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
8116 std::swap(LHS, RHS);
8117 std::swap(ShiftLHS, ShiftRHS);
8120 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
8121 DAG.getConstant(ShiftRHS, DL, MVT::i64));
8124 static SDValue tryCombineToBSL(SDNode *N,
8125 TargetLowering::DAGCombinerInfo &DCI) {
8126 EVT VT = N->getValueType(0);
8127 SelectionDAG &DAG = DCI.DAG;
8133 SDValue N0 = N->getOperand(0);
8134 if (N0.getOpcode() != ISD::AND)
8137 SDValue N1 = N->getOperand(1);
8138 if (N1.getOpcode() != ISD::AND)
8141 // We only have to look for constant vectors here since the general, variable
8142 // case can be handled in TableGen.
8143 unsigned Bits = VT.getScalarSizeInBits();
8144 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
8145 for (int i = 1; i >= 0; --i)
8146 for (int j = 1; j >= 0; --j) {
8147 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
8148 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
8152 bool FoundMatch = true;
8153 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
8154 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
8155 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
8157 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
8164 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
8165 N0->getOperand(1 - i), N1->getOperand(1 - j));
8171 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
8172 const AArch64Subtarget *Subtarget) {
8173 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
8174 SelectionDAG &DAG = DCI.DAG;
8175 EVT VT = N->getValueType(0);
8177 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8180 if (SDValue Res = tryCombineToEXTR(N, DCI))
8183 if (SDValue Res = tryCombineToBSL(N, DCI))
8189 static SDValue performSRLCombine(SDNode *N,
8190 TargetLowering::DAGCombinerInfo &DCI) {
8191 SelectionDAG &DAG = DCI.DAG;
8192 EVT VT = N->getValueType(0);
8193 if (VT != MVT::i32 && VT != MVT::i64)
8196 // Canonicalize (srl (bswap i32 x), 16) to (rotr (bswap i32 x), 16), if the
8197 // high 16-bits of x are zero. Similarly, canonicalize (srl (bswap i64 x), 32)
8198 // to (rotr (bswap i64 x), 32), if the high 32-bits of x are zero.
8199 SDValue N0 = N->getOperand(0);
8200 if (N0.getOpcode() == ISD::BSWAP) {
8202 SDValue N1 = N->getOperand(1);
8203 SDValue N00 = N0.getOperand(0);
8204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
8205 uint64_t ShiftAmt = C->getZExtValue();
8206 if (VT == MVT::i32 && ShiftAmt == 16 &&
8207 DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(32, 16)))
8208 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
8209 if (VT == MVT::i64 && ShiftAmt == 32 &&
8210 DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(64, 32)))
8211 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
8217 static SDValue performBitcastCombine(SDNode *N,
8218 TargetLowering::DAGCombinerInfo &DCI,
8219 SelectionDAG &DAG) {
8220 // Wait 'til after everything is legalized to try this. That way we have
8221 // legal vector types and such.
8222 if (DCI.isBeforeLegalizeOps())
8225 // Remove extraneous bitcasts around an extract_subvector.
8227 // (v4i16 (bitconvert
8228 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
8230 // (extract_subvector ((v8i16 ...), (i64 4)))
8232 // Only interested in 64-bit vectors as the ultimate result.
8233 EVT VT = N->getValueType(0);
8236 if (VT.getSimpleVT().getSizeInBits() != 64)
8238 // Is the operand an extract_subvector starting at the beginning or halfway
8239 // point of the vector? A low half may also come through as an
8240 // EXTRACT_SUBREG, so look for that, too.
8241 SDValue Op0 = N->getOperand(0);
8242 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
8243 !(Op0->isMachineOpcode() &&
8244 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
8246 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
8247 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
8248 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
8250 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
8251 if (idx != AArch64::dsub)
8253 // The dsub reference is equivalent to a lane zero subvector reference.
8256 // Look through the bitcast of the input to the extract.
8257 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
8259 SDValue Source = Op0->getOperand(0)->getOperand(0);
8260 // If the source type has twice the number of elements as our destination
8261 // type, we know this is an extract of the high or low half of the vector.
8262 EVT SVT = Source->getValueType(0);
8263 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
8266 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
8268 // Create the simplified form to just extract the low or high half of the
8269 // vector directly rather than bothering with the bitcasts.
8271 unsigned NumElements = VT.getVectorNumElements();
8273 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
8274 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
8276 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
8277 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
8283 static SDValue performConcatVectorsCombine(SDNode *N,
8284 TargetLowering::DAGCombinerInfo &DCI,
8285 SelectionDAG &DAG) {
8287 EVT VT = N->getValueType(0);
8288 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
8290 // Optimize concat_vectors of truncated vectors, where the intermediate
8291 // type is illegal, to avoid said illegality, e.g.,
8292 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
8293 // (v2i16 (truncate (v2i64)))))
8295 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
8296 // (v4i32 (bitcast (v2i64))),
8298 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
8299 // on both input and result type, so we might generate worse code.
8300 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
8301 if (N->getNumOperands() == 2 &&
8302 N0->getOpcode() == ISD::TRUNCATE &&
8303 N1->getOpcode() == ISD::TRUNCATE) {
8304 SDValue N00 = N0->getOperand(0);
8305 SDValue N10 = N1->getOperand(0);
8306 EVT N00VT = N00.getValueType();
8308 if (N00VT == N10.getValueType() &&
8309 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
8310 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
8311 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
8312 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
8313 for (size_t i = 0; i < Mask.size(); ++i)
8315 return DAG.getNode(ISD::TRUNCATE, dl, VT,
8316 DAG.getVectorShuffle(
8318 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
8319 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
8323 // Wait 'til after everything is legalized to try this. That way we have
8324 // legal vector types and such.
8325 if (DCI.isBeforeLegalizeOps())
8328 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
8329 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
8330 // canonicalise to that.
8331 if (N0 == N1 && VT.getVectorNumElements() == 2) {
8332 assert(VT.getScalarSizeInBits() == 64);
8333 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
8334 DAG.getConstant(0, dl, MVT::i64));
8337 // Canonicalise concat_vectors so that the right-hand vector has as few
8338 // bit-casts as possible before its real operation. The primary matching
8339 // destination for these operations will be the narrowing "2" instructions,
8340 // which depend on the operation being performed on this right-hand vector.
8342 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
8344 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
8346 if (N1->getOpcode() != ISD::BITCAST)
8348 SDValue RHS = N1->getOperand(0);
8349 MVT RHSTy = RHS.getValueType().getSimpleVT();
8350 // If the RHS is not a vector, this is not the pattern we're looking for.
8351 if (!RHSTy.isVector())
8354 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
8356 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
8357 RHSTy.getVectorNumElements() * 2);
8358 return DAG.getNode(ISD::BITCAST, dl, VT,
8359 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
8360 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
8364 static SDValue tryCombineFixedPointConvert(SDNode *N,
8365 TargetLowering::DAGCombinerInfo &DCI,
8366 SelectionDAG &DAG) {
8367 // Wait 'til after everything is legalized to try this. That way we have
8368 // legal vector types and such.
8369 if (DCI.isBeforeLegalizeOps())
8371 // Transform a scalar conversion of a value from a lane extract into a
8372 // lane extract of a vector conversion. E.g., from foo1 to foo2:
8373 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
8374 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
8376 // The second form interacts better with instruction selection and the
8377 // register allocator to avoid cross-class register copies that aren't
8378 // coalescable due to a lane reference.
8380 // Check the operand and see if it originates from a lane extract.
8381 SDValue Op1 = N->getOperand(1);
8382 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8383 // Yep, no additional predication needed. Perform the transform.
8384 SDValue IID = N->getOperand(0);
8385 SDValue Shift = N->getOperand(2);
8386 SDValue Vec = Op1.getOperand(0);
8387 SDValue Lane = Op1.getOperand(1);
8388 EVT ResTy = N->getValueType(0);
8392 // The vector width should be 128 bits by the time we get here, even
8393 // if it started as 64 bits (the extract_vector handling will have
8395 assert(Vec.getValueSizeInBits() == 128 &&
8396 "unexpected vector size on extract_vector_elt!");
8397 if (Vec.getValueType() == MVT::v4i32)
8398 VecResTy = MVT::v4f32;
8399 else if (Vec.getValueType() == MVT::v2i64)
8400 VecResTy = MVT::v2f64;
8402 llvm_unreachable("unexpected vector type!");
8405 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
8406 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
8411 // AArch64 high-vector "long" operations are formed by performing the non-high
8412 // version on an extract_subvector of each operand which gets the high half:
8414 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
8416 // However, there are cases which don't have an extract_high explicitly, but
8417 // have another operation that can be made compatible with one for free. For
8420 // (dupv64 scalar) --> (extract_high (dup128 scalar))
8422 // This routine does the actual conversion of such DUPs, once outer routines
8423 // have determined that everything else is in order.
8424 // It also supports immediate DUP-like nodes (MOVI/MVNi), which we can fold
8426 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
8427 switch (N.getOpcode()) {
8428 case AArch64ISD::DUP:
8429 case AArch64ISD::DUPLANE8:
8430 case AArch64ISD::DUPLANE16:
8431 case AArch64ISD::DUPLANE32:
8432 case AArch64ISD::DUPLANE64:
8433 case AArch64ISD::MOVI:
8434 case AArch64ISD::MOVIshift:
8435 case AArch64ISD::MOVIedit:
8436 case AArch64ISD::MOVImsl:
8437 case AArch64ISD::MVNIshift:
8438 case AArch64ISD::MVNImsl:
8441 // FMOV could be supported, but isn't very useful, as it would only occur
8442 // if you passed a bitcast' floating point immediate to an eligible long
8443 // integer op (addl, smull, ...).
8447 MVT NarrowTy = N.getSimpleValueType();
8448 if (!NarrowTy.is64BitVector())
8451 MVT ElementTy = NarrowTy.getVectorElementType();
8452 unsigned NumElems = NarrowTy.getVectorNumElements();
8453 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2);
8456 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy,
8457 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
8458 DAG.getConstant(NumElems, dl, MVT::i64));
8461 static bool isEssentiallyExtractSubvector(SDValue N) {
8462 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
8465 return N.getOpcode() == ISD::BITCAST &&
8466 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
8469 /// \brief Helper structure to keep track of ISD::SET_CC operands.
8470 struct GenericSetCCInfo {
8471 const SDValue *Opnd0;
8472 const SDValue *Opnd1;
8476 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
8477 struct AArch64SetCCInfo {
8479 AArch64CC::CondCode CC;
8482 /// \brief Helper structure to keep track of SetCC information.
8484 GenericSetCCInfo Generic;
8485 AArch64SetCCInfo AArch64;
8488 /// \brief Helper structure to be able to read SetCC information. If set to
8489 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
8490 /// GenericSetCCInfo.
8491 struct SetCCInfoAndKind {
8496 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
8498 /// AArch64 lowered one.
8499 /// \p SetCCInfo is filled accordingly.
8500 /// \post SetCCInfo is meanginfull only when this function returns true.
8501 /// \return True when Op is a kind of SET_CC operation.
8502 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
8503 // If this is a setcc, this is straight forward.
8504 if (Op.getOpcode() == ISD::SETCC) {
8505 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
8506 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
8507 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8508 SetCCInfo.IsAArch64 = false;
8511 // Otherwise, check if this is a matching csel instruction.
8515 if (Op.getOpcode() != AArch64ISD::CSEL)
8517 // Set the information about the operands.
8518 // TODO: we want the operands of the Cmp not the csel
8519 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
8520 SetCCInfo.IsAArch64 = true;
8521 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
8522 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
8524 // Check that the operands matches the constraints:
8525 // (1) Both operands must be constants.
8526 // (2) One must be 1 and the other must be 0.
8527 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
8528 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8531 if (!TValue || !FValue)
8535 if (!TValue->isOne()) {
8536 // Update the comparison when we are interested in !cc.
8537 std::swap(TValue, FValue);
8538 SetCCInfo.Info.AArch64.CC =
8539 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
8541 return TValue->isOne() && FValue->isNullValue();
8544 // Returns true if Op is setcc or zext of setcc.
8545 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
8546 if (isSetCC(Op, Info))
8548 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
8549 isSetCC(Op->getOperand(0), Info));
8552 // The folding we want to perform is:
8553 // (add x, [zext] (setcc cc ...) )
8555 // (csel x, (add x, 1), !cc ...)
8557 // The latter will get matched to a CSINC instruction.
8558 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
8559 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
8560 SDValue LHS = Op->getOperand(0);
8561 SDValue RHS = Op->getOperand(1);
8562 SetCCInfoAndKind InfoAndKind;
8564 // If neither operand is a SET_CC, give up.
8565 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
8566 std::swap(LHS, RHS);
8567 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
8571 // FIXME: This could be generatized to work for FP comparisons.
8572 EVT CmpVT = InfoAndKind.IsAArch64
8573 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
8574 : InfoAndKind.Info.Generic.Opnd0->getValueType();
8575 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
8581 if (InfoAndKind.IsAArch64) {
8582 CCVal = DAG.getConstant(
8583 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8585 Cmp = *InfoAndKind.Info.AArch64.Cmp;
8587 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
8588 *InfoAndKind.Info.Generic.Opnd1,
8589 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
8592 EVT VT = Op->getValueType(0);
8593 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8594 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8597 // The basic add/sub long vector instructions have variants with "2" on the end
8598 // which act on the high-half of their inputs. They are normally matched by
8601 // (add (zeroext (extract_high LHS)),
8602 // (zeroext (extract_high RHS)))
8603 // -> uaddl2 vD, vN, vM
8605 // However, if one of the extracts is something like a duplicate, this
8606 // instruction can still be used profitably. This function puts the DAG into a
8607 // more appropriate form for those patterns to trigger.
8608 static SDValue performAddSubLongCombine(SDNode *N,
8609 TargetLowering::DAGCombinerInfo &DCI,
8610 SelectionDAG &DAG) {
8611 if (DCI.isBeforeLegalizeOps())
8614 MVT VT = N->getSimpleValueType(0);
8615 if (!VT.is128BitVector()) {
8616 if (N->getOpcode() == ISD::ADD)
8617 return performSetccAddFolding(N, DAG);
8621 // Make sure both branches are extended in the same way.
8622 SDValue LHS = N->getOperand(0);
8623 SDValue RHS = N->getOperand(1);
8624 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
8625 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
8626 LHS.getOpcode() != RHS.getOpcode())
8629 unsigned ExtType = LHS.getOpcode();
8631 // It's not worth doing if at least one of the inputs isn't already an
8632 // extract, but we don't know which it'll be so we have to try both.
8633 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
8634 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
8638 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8639 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
8640 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
8644 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8647 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8650 // Massage DAGs which we can use the high-half "long" operations on into
8651 // something isel will recognize better. E.g.
8653 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
8654 // (aarch64_neon_umull (extract_high (v2i64 vec)))
8655 // (extract_high (v2i64 (dup128 scalar)))))
8657 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
8658 TargetLowering::DAGCombinerInfo &DCI,
8659 SelectionDAG &DAG) {
8660 if (DCI.isBeforeLegalizeOps())
8663 SDValue LHS = N->getOperand(1);
8664 SDValue RHS = N->getOperand(2);
8665 assert(LHS.getValueType().is64BitVector() &&
8666 RHS.getValueType().is64BitVector() &&
8667 "unexpected shape for long operation");
8669 // Either node could be a DUP, but it's not worth doing both of them (you'd
8670 // just as well use the non-high version) so look for a corresponding extract
8671 // operation on the other "wing".
8672 if (isEssentiallyExtractSubvector(LHS)) {
8673 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
8676 } else if (isEssentiallyExtractSubvector(RHS)) {
8677 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
8682 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
8683 N->getOperand(0), LHS, RHS);
8686 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
8687 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
8688 unsigned ElemBits = ElemTy.getSizeInBits();
8690 int64_t ShiftAmount;
8691 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
8692 APInt SplatValue, SplatUndef;
8693 unsigned SplatBitSize;
8695 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
8696 HasAnyUndefs, ElemBits) ||
8697 SplatBitSize != ElemBits)
8700 ShiftAmount = SplatValue.getSExtValue();
8701 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
8702 ShiftAmount = CVN->getSExtValue();
8710 llvm_unreachable("Unknown shift intrinsic");
8711 case Intrinsic::aarch64_neon_sqshl:
8712 Opcode = AArch64ISD::SQSHL_I;
8713 IsRightShift = false;
8715 case Intrinsic::aarch64_neon_uqshl:
8716 Opcode = AArch64ISD::UQSHL_I;
8717 IsRightShift = false;
8719 case Intrinsic::aarch64_neon_srshl:
8720 Opcode = AArch64ISD::SRSHR_I;
8721 IsRightShift = true;
8723 case Intrinsic::aarch64_neon_urshl:
8724 Opcode = AArch64ISD::URSHR_I;
8725 IsRightShift = true;
8727 case Intrinsic::aarch64_neon_sqshlu:
8728 Opcode = AArch64ISD::SQSHLU_I;
8729 IsRightShift = false;
8733 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8735 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8736 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8737 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
8739 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
8740 DAG.getConstant(ShiftAmount, dl, MVT::i32));
8746 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
8747 // the intrinsics must be legal and take an i32, this means there's almost
8748 // certainly going to be a zext in the DAG which we can eliminate.
8749 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
8750 SDValue AndN = N->getOperand(2);
8751 if (AndN.getOpcode() != ISD::AND)
8754 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
8755 if (!CMask || CMask->getZExtValue() != Mask)
8758 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
8759 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
8762 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
8763 SelectionDAG &DAG) {
8765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
8766 DAG.getNode(Opc, dl,
8767 N->getOperand(1).getSimpleValueType(),
8769 DAG.getConstant(0, dl, MVT::i64));
8772 static SDValue performIntrinsicCombine(SDNode *N,
8773 TargetLowering::DAGCombinerInfo &DCI,
8774 const AArch64Subtarget *Subtarget) {
8775 SelectionDAG &DAG = DCI.DAG;
8776 unsigned IID = getIntrinsicID(N);
8780 case Intrinsic::aarch64_neon_vcvtfxs2fp:
8781 case Intrinsic::aarch64_neon_vcvtfxu2fp:
8782 return tryCombineFixedPointConvert(N, DCI, DAG);
8783 case Intrinsic::aarch64_neon_saddv:
8784 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
8785 case Intrinsic::aarch64_neon_uaddv:
8786 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
8787 case Intrinsic::aarch64_neon_sminv:
8788 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
8789 case Intrinsic::aarch64_neon_uminv:
8790 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
8791 case Intrinsic::aarch64_neon_smaxv:
8792 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
8793 case Intrinsic::aarch64_neon_umaxv:
8794 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
8795 case Intrinsic::aarch64_neon_fmax:
8796 return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),
8797 N->getOperand(1), N->getOperand(2));
8798 case Intrinsic::aarch64_neon_fmin:
8799 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
8800 N->getOperand(1), N->getOperand(2));
8801 case Intrinsic::aarch64_neon_fmaxnm:
8802 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
8803 N->getOperand(1), N->getOperand(2));
8804 case Intrinsic::aarch64_neon_fminnm:
8805 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0),
8806 N->getOperand(1), N->getOperand(2));
8807 case Intrinsic::aarch64_neon_smull:
8808 case Intrinsic::aarch64_neon_umull:
8809 case Intrinsic::aarch64_neon_pmull:
8810 case Intrinsic::aarch64_neon_sqdmull:
8811 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
8812 case Intrinsic::aarch64_neon_sqshl:
8813 case Intrinsic::aarch64_neon_uqshl:
8814 case Intrinsic::aarch64_neon_sqshlu:
8815 case Intrinsic::aarch64_neon_srshl:
8816 case Intrinsic::aarch64_neon_urshl:
8817 return tryCombineShiftImm(IID, N, DAG);
8818 case Intrinsic::aarch64_crc32b:
8819 case Intrinsic::aarch64_crc32cb:
8820 return tryCombineCRC32(0xff, N, DAG);
8821 case Intrinsic::aarch64_crc32h:
8822 case Intrinsic::aarch64_crc32ch:
8823 return tryCombineCRC32(0xffff, N, DAG);
8828 static SDValue performExtendCombine(SDNode *N,
8829 TargetLowering::DAGCombinerInfo &DCI,
8830 SelectionDAG &DAG) {
8831 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
8832 // we can convert that DUP into another extract_high (of a bigger DUP), which
8833 // helps the backend to decide that an sabdl2 would be useful, saving a real
8834 // extract_high operation.
8835 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
8836 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
8837 SDNode *ABDNode = N->getOperand(0).getNode();
8838 unsigned IID = getIntrinsicID(ABDNode);
8839 if (IID == Intrinsic::aarch64_neon_sabd ||
8840 IID == Intrinsic::aarch64_neon_uabd) {
8841 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
8842 if (!NewABD.getNode())
8845 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
8850 // This is effectively a custom type legalization for AArch64.
8852 // Type legalization will split an extend of a small, legal, type to a larger
8853 // illegal type by first splitting the destination type, often creating
8854 // illegal source types, which then get legalized in isel-confusing ways,
8855 // leading to really terrible codegen. E.g.,
8856 // %result = v8i32 sext v8i8 %value
8858 // %losrc = extract_subreg %value, ...
8859 // %hisrc = extract_subreg %value, ...
8860 // %lo = v4i32 sext v4i8 %losrc
8861 // %hi = v4i32 sext v4i8 %hisrc
8862 // Things go rapidly downhill from there.
8864 // For AArch64, the [sz]ext vector instructions can only go up one element
8865 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
8866 // take two instructions.
8868 // This implies that the most efficient way to do the extend from v8i8
8869 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
8870 // the normal splitting to happen for the v8i16->v8i32.
8872 // This is pre-legalization to catch some cases where the default
8873 // type legalization will create ill-tempered code.
8874 if (!DCI.isBeforeLegalizeOps())
8877 // We're only interested in cleaning things up for non-legal vector types
8878 // here. If both the source and destination are legal, things will just
8879 // work naturally without any fiddling.
8880 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8881 EVT ResVT = N->getValueType(0);
8882 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
8884 // If the vector type isn't a simple VT, it's beyond the scope of what
8885 // we're worried about here. Let legalization do its thing and hope for
8887 SDValue Src = N->getOperand(0);
8888 EVT SrcVT = Src->getValueType(0);
8889 if (!ResVT.isSimple() || !SrcVT.isSimple())
8892 // If the source VT is a 64-bit vector, we can play games and get the
8893 // better results we want.
8894 if (SrcVT.getSizeInBits() != 64)
8897 unsigned SrcEltSize = SrcVT.getScalarSizeInBits();
8898 unsigned ElementCount = SrcVT.getVectorNumElements();
8899 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
8901 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
8903 // Now split the rest of the operation into two halves, each with a 64
8907 unsigned NumElements = ResVT.getVectorNumElements();
8908 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
8909 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
8910 ResVT.getVectorElementType(), NumElements / 2);
8912 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
8913 LoVT.getVectorNumElements());
8914 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8915 DAG.getConstant(0, DL, MVT::i64));
8916 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
8917 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
8918 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
8919 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
8921 // Now combine the parts back together so we still have a single result
8922 // like the combiner expects.
8923 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
8926 static SDValue splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St,
8927 SDValue SplatVal, unsigned NumVecElts) {
8928 unsigned OrigAlignment = St.getAlignment();
8929 unsigned EltOffset = SplatVal.getValueType().getSizeInBits() / 8;
8931 // Create scalar stores. This is at least as good as the code sequence for a
8932 // split unaligned store which is a dup.s, ext.b, and two stores.
8933 // Most of the time the three stores should be replaced by store pair
8934 // instructions (stp).
8936 SDValue BasePtr = St.getBasePtr();
8938 DAG.getStore(St.getChain(), DL, SplatVal, BasePtr, St.getPointerInfo(),
8939 OrigAlignment, St.getMemOperand()->getFlags());
8941 unsigned Offset = EltOffset;
8942 while (--NumVecElts) {
8943 unsigned Alignment = MinAlign(OrigAlignment, Offset);
8944 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8945 DAG.getConstant(Offset, DL, MVT::i64));
8946 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
8947 St.getPointerInfo(), Alignment,
8948 St.getMemOperand()->getFlags());
8949 Offset += EltOffset;
8954 /// Replace a splat of zeros to a vector store by scalar stores of WZR/XZR. The
8955 /// load store optimizer pass will merge them to store pair stores. This should
8956 /// be better than a movi to create the vector zero followed by a vector store
8957 /// if the zero constant is not re-used, since one instructions and one register
8958 /// live range will be removed.
8960 /// For example, the final generated code should be:
8962 /// stp xzr, xzr, [x0]
8969 static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
8970 SDValue StVal = St.getValue();
8971 EVT VT = StVal.getValueType();
8973 // It is beneficial to scalarize a zero splat store for 2 or 3 i64 elements or
8974 // 2, 3 or 4 i32 elements.
8975 int NumVecElts = VT.getVectorNumElements();
8976 if (!(((NumVecElts == 2 || NumVecElts == 3) &&
8977 VT.getVectorElementType().getSizeInBits() == 64) ||
8978 ((NumVecElts == 2 || NumVecElts == 3 || NumVecElts == 4) &&
8979 VT.getVectorElementType().getSizeInBits() == 32)))
8982 if (StVal.getOpcode() != ISD::BUILD_VECTOR)
8985 // If the zero constant has more than one use then the vector store could be
8986 // better since the constant mov will be amortized and stp q instructions
8987 // should be able to be formed.
8988 if (!StVal.hasOneUse())
8991 // If the immediate offset of the address operand is too large for the stp
8992 // instruction, then bail out.
8993 if (DAG.isBaseWithConstantOffset(St.getBasePtr())) {
8994 int64_t Offset = St.getBasePtr()->getConstantOperandVal(1);
8995 if (Offset < -512 || Offset > 504)
8999 for (int I = 0; I < NumVecElts; ++I) {
9000 SDValue EltVal = StVal.getOperand(I);
9001 if (!isNullConstant(EltVal) && !isNullFPConstant(EltVal))
9005 // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
9006 // undoing this transformation.
9007 SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
9008 ? DAG.getRegister(AArch64::WZR, MVT::i32)
9009 : DAG.getRegister(AArch64::XZR, MVT::i64);
9010 return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
9013 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
9014 /// value. The load store optimizer pass will merge them to store pair stores.
9015 /// This has better performance than a splat of the scalar followed by a split
9016 /// vector store. Even if the stores are not merged it is four stores vs a dup,
9017 /// followed by an ext.b and two stores.
9018 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
9019 SDValue StVal = St.getValue();
9020 EVT VT = StVal.getValueType();
9022 // Don't replace floating point stores, they possibly won't be transformed to
9023 // stp because of the store pair suppress pass.
9024 if (VT.isFloatingPoint())
9027 // We can express a splat as store pair(s) for 2 or 4 elements.
9028 unsigned NumVecElts = VT.getVectorNumElements();
9029 if (NumVecElts != 4 && NumVecElts != 2)
9032 // Check that this is a splat.
9033 // Make sure that each of the relevant vector element locations are inserted
9034 // to, i.e. 0 and 1 for v2i64 and 0, 1, 2, 3 for v4i32.
9035 std::bitset<4> IndexNotInserted((1 << NumVecElts) - 1);
9037 for (unsigned I = 0; I < NumVecElts; ++I) {
9038 // Check for insert vector elements.
9039 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
9042 // Check that same value is inserted at each vector element.
9044 SplatVal = StVal.getOperand(1);
9045 else if (StVal.getOperand(1) != SplatVal)
9048 // Check insert element index.
9049 ConstantSDNode *CIndex = dyn_cast<ConstantSDNode>(StVal.getOperand(2));
9052 uint64_t IndexVal = CIndex->getZExtValue();
9053 if (IndexVal >= NumVecElts)
9055 IndexNotInserted.reset(IndexVal);
9057 StVal = StVal.getOperand(0);
9059 // Check that all vector element locations were inserted to.
9060 if (IndexNotInserted.any())
9063 return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
9066 static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
9068 const AArch64Subtarget *Subtarget) {
9069 if (!DCI.isBeforeLegalize())
9072 StoreSDNode *S = cast<StoreSDNode>(N);
9073 if (S->isVolatile())
9076 SDValue StVal = S->getValue();
9077 EVT VT = StVal.getValueType();
9081 // If we get a splat of zeros, convert this vector store to a store of
9082 // scalars. They will be merged into store pairs of xzr thereby removing one
9083 // instruction and one register.
9084 if (SDValue ReplacedZeroSplat = replaceZeroVectorStore(DAG, *S))
9085 return ReplacedZeroSplat;
9087 // FIXME: The logic for deciding if an unaligned store should be split should
9088 // be included in TLI.allowsMisalignedMemoryAccesses(), and there should be
9089 // a call to that function here.
9091 if (!Subtarget->isMisaligned128StoreSlow())
9094 // Don't split at -Oz.
9095 if (DAG.getMachineFunction().getFunction()->optForMinSize())
9098 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
9099 // those up regresses performance on micro-benchmarks and olden/bh.
9100 if (VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
9103 // Split unaligned 16B stores. They are terrible for performance.
9104 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
9105 // extensions can use this to mark that it does not want splitting to happen
9106 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
9107 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
9108 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
9109 S->getAlignment() <= 2)
9112 // If we get a splat of a scalar convert this vector store to a store of
9113 // scalars. They will be merged into store pairs thereby removing two
9115 if (SDValue ReplacedSplat = replaceSplatVectorStore(DAG, *S))
9116 return ReplacedSplat;
9119 unsigned NumElts = VT.getVectorNumElements() / 2;
9120 // Split VT into two.
9122 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
9123 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
9124 DAG.getConstant(0, DL, MVT::i64));
9125 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
9126 DAG.getConstant(NumElts, DL, MVT::i64));
9127 SDValue BasePtr = S->getBasePtr();
9129 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
9130 S->getAlignment(), S->getMemOperand()->getFlags());
9131 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
9132 DAG.getConstant(8, DL, MVT::i64));
9133 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
9134 S->getPointerInfo(), S->getAlignment(),
9135 S->getMemOperand()->getFlags());
9138 /// Target-specific DAG combine function for post-increment LD1 (lane) and
9139 /// post-increment LD1R.
9140 static SDValue performPostLD1Combine(SDNode *N,
9141 TargetLowering::DAGCombinerInfo &DCI,
9143 if (DCI.isBeforeLegalizeOps())
9146 SelectionDAG &DAG = DCI.DAG;
9147 EVT VT = N->getValueType(0);
9149 unsigned LoadIdx = IsLaneOp ? 1 : 0;
9150 SDNode *LD = N->getOperand(LoadIdx).getNode();
9151 // If it is not LOAD, can not do such combine.
9152 if (LD->getOpcode() != ISD::LOAD)
9155 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
9156 EVT MemVT = LoadSDN->getMemoryVT();
9157 // Check if memory operand is the same type as the vector element.
9158 if (MemVT != VT.getVectorElementType())
9161 // Check if there are other uses. If so, do not combine as it will introduce
9163 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
9165 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
9171 SDValue Addr = LD->getOperand(1);
9172 SDValue Vector = N->getOperand(0);
9173 // Search for a use of the address operand that is an increment.
9174 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
9175 Addr.getNode()->use_end(); UI != UE; ++UI) {
9177 if (User->getOpcode() != ISD::ADD
9178 || UI.getUse().getResNo() != Addr.getResNo())
9181 // Check that the add is independent of the load. Otherwise, folding it
9182 // would create a cycle.
9183 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
9185 // Also check that add is not used in the vector operand. This would also
9187 if (User->isPredecessorOf(Vector.getNode()))
9190 // If the increment is a constant, it must match the memory ref size.
9191 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9192 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9193 uint32_t IncVal = CInc->getZExtValue();
9194 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
9195 if (IncVal != NumBytes)
9197 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
9200 // Finally, check that the vector doesn't depend on the load.
9201 // Again, this would create a cycle.
9202 // The load depending on the vector is fine, as that's the case for the
9203 // LD1*post we'll eventually generate anyway.
9204 if (LoadSDN->isPredecessorOf(Vector.getNode()))
9207 SmallVector<SDValue, 8> Ops;
9208 Ops.push_back(LD->getOperand(0)); // Chain
9210 Ops.push_back(Vector); // The vector to be inserted
9211 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
9213 Ops.push_back(Addr);
9216 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
9217 SDVTList SDTys = DAG.getVTList(Tys);
9218 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
9219 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
9221 LoadSDN->getMemOperand());
9224 SDValue NewResults[] = {
9225 SDValue(LD, 0), // The result of load
9226 SDValue(UpdN.getNode(), 2) // Chain
9228 DCI.CombineTo(LD, NewResults);
9229 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
9230 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
9237 /// Simplify \Addr given that the top byte of it is ignored by HW during
9238 /// address translation.
9239 static bool performTBISimplification(SDValue Addr,
9240 TargetLowering::DAGCombinerInfo &DCI,
9241 SelectionDAG &DAG) {
9242 APInt DemandedMask = APInt::getLowBitsSet(64, 56);
9243 APInt KnownZero, KnownOne;
9244 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
9245 DCI.isBeforeLegalizeOps());
9246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9247 if (TLI.SimplifyDemandedBits(Addr, DemandedMask, KnownZero, KnownOne, TLO)) {
9248 DCI.CommitTargetLoweringOpt(TLO);
9254 static SDValue performSTORECombine(SDNode *N,
9255 TargetLowering::DAGCombinerInfo &DCI,
9257 const AArch64Subtarget *Subtarget) {
9258 if (SDValue Split = splitStores(N, DCI, DAG, Subtarget))
9261 if (Subtarget->supportsAddressTopByteIgnored() &&
9262 performTBISimplification(N->getOperand(2), DCI, DAG))
9263 return SDValue(N, 0);
9268 /// This function handles the log2-shuffle pattern produced by the
9269 /// LoopVectorizer for the across vector reduction. It consists of
9270 /// log2(NumVectorElements) steps and, in each step, 2^(s) elements
9271 /// are reduced, where s is an induction variable from 0 to
9272 /// log2(NumVectorElements).
9273 static SDValue tryMatchAcrossLaneShuffleForReduction(SDNode *N, SDValue OpV,
9275 SelectionDAG &DAG) {
9276 EVT VTy = OpV->getOperand(0).getValueType();
9277 if (!VTy.isVector())
9280 int NumVecElts = VTy.getVectorNumElements();
9281 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
9282 if (NumVecElts != 4)
9285 if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
9289 int NumExpectedSteps = APInt(8, NumVecElts).logBase2();
9290 SDValue PreOp = OpV;
9291 // Iterate over each step of the across vector reduction.
9292 for (int CurStep = 0; CurStep != NumExpectedSteps; ++CurStep) {
9293 SDValue CurOp = PreOp.getOperand(0);
9294 SDValue Shuffle = PreOp.getOperand(1);
9295 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE) {
9296 // Try to swap the 1st and 2nd operand as add and min/max instructions
9298 CurOp = PreOp.getOperand(1);
9299 Shuffle = PreOp.getOperand(0);
9300 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
9304 // Check if the input vector is fed by the operator we want to handle,
9305 // except the last step; the very first input vector is not necessarily
9306 // the same operator we are handling.
9307 if (CurOp.getOpcode() != Op && (CurStep != (NumExpectedSteps - 1)))
9310 // Check if it forms one step of the across vector reduction.
9312 // %cur = add %1, %0
9313 // %shuffle = vector_shuffle %cur, <2, 3, u, u>
9314 // %pre = add %cur, %shuffle
9315 if (Shuffle.getOperand(0) != CurOp)
9318 int NumMaskElts = 1 << CurStep;
9319 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Shuffle)->getMask();
9320 // Check mask values in each step.
9321 // We expect the shuffle mask in each step follows a specific pattern
9322 // denoted here by the <M, U> form, where M is a sequence of integers
9323 // starting from NumMaskElts, increasing by 1, and the number integers
9324 // in M should be NumMaskElts. U is a sequence of UNDEFs and the number
9325 // of undef in U should be NumVecElts - NumMaskElts.
9326 // E.g., for <8 x i16>, mask values in each step should be :
9327 // step 0 : <1,u,u,u,u,u,u,u>
9328 // step 1 : <2,3,u,u,u,u,u,u>
9329 // step 2 : <4,5,6,7,u,u,u,u>
9330 for (int i = 0; i < NumVecElts; ++i)
9331 if ((i < NumMaskElts && Mask[i] != (NumMaskElts + i)) ||
9332 (i >= NumMaskElts && !(Mask[i] < 0)))
9338 bool IsIntrinsic = false;
9342 llvm_unreachable("Unexpected operator for across vector reduction");
9344 Opcode = AArch64ISD::UADDV;
9347 Opcode = AArch64ISD::SMAXV;
9350 Opcode = AArch64ISD::UMAXV;
9353 Opcode = AArch64ISD::SMINV;
9356 Opcode = AArch64ISD::UMINV;
9359 Opcode = Intrinsic::aarch64_neon_fmaxnmv;
9363 Opcode = Intrinsic::aarch64_neon_fminnmv;
9370 ? DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, N->getValueType(0),
9371 DAG.getConstant(Opcode, DL, MVT::i32), PreOp)
9373 ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0),
9374 DAG.getNode(Opcode, DL, PreOp.getSimpleValueType(), PreOp),
9375 DAG.getConstant(0, DL, MVT::i64));
9378 /// Target-specific DAG combine for the across vector min/max reductions.
9379 /// This function specifically handles the final clean-up step of the vector
9380 /// min/max reductions produced by the LoopVectorizer. It is the log2-shuffle
9381 /// pattern, which narrows down and finds the final min/max value from all
9382 /// elements of the vector.
9383 /// For example, for a <16 x i8> vector :
9384 /// svn0 = vector_shuffle %0, undef<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u>
9385 /// %smax0 = smax %arr, svn0
9386 /// %svn1 = vector_shuffle %smax0, undef<4,5,6,7,u,u,u,u,u,u,u,u,u,u,u,u>
9387 /// %smax1 = smax %smax0, %svn1
9388 /// %svn2 = vector_shuffle %smax1, undef<2,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
9389 /// %smax2 = smax %smax1, svn2
9390 /// %svn3 = vector_shuffle %smax2, undef<1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
9391 /// %sc = setcc %smax2, %svn3, gt
9392 /// %n0 = extract_vector_elt %sc, #0
9393 /// %n1 = extract_vector_elt %smax2, #0
9394 /// %n2 = extract_vector_elt $smax2, #1
9395 /// %result = select %n0, %n1, n2
9398 /// %result = extract_vector_elt %1, 0
9400 performAcrossLaneMinMaxReductionCombine(SDNode *N, SelectionDAG &DAG,
9401 const AArch64Subtarget *Subtarget) {
9402 if (!Subtarget->hasNEON())
9405 SDValue N0 = N->getOperand(0);
9406 SDValue IfTrue = N->getOperand(1);
9407 SDValue IfFalse = N->getOperand(2);
9409 // Check if the SELECT merges up the final result of the min/max
9411 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9412 IfTrue.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9413 IfFalse.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9416 // Expect N0 is fed by SETCC.
9417 SDValue SetCC = N0.getOperand(0);
9418 EVT SetCCVT = SetCC.getValueType();
9419 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() ||
9420 SetCCVT.getVectorElementType() != MVT::i1)
9423 SDValue VectorOp = SetCC.getOperand(0);
9424 unsigned Op = VectorOp->getOpcode();
9425 // Check if the input vector is fed by the operator we want to handle.
9426 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN &&
9427 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM)
9430 EVT VTy = VectorOp.getValueType();
9431 if (!VTy.isVector())
9434 if (VTy.getSizeInBits() < 64)
9437 EVT EltTy = VTy.getVectorElementType();
9438 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
9439 if (EltTy != MVT::f32)
9442 if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
9446 // Check if extracting from the same vector.
9448 // %sc = setcc %vector, %svn1, gt
9449 // %n0 = extract_vector_elt %sc, #0
9450 // %n1 = extract_vector_elt %vector, #0
9451 // %n2 = extract_vector_elt $vector, #1
9452 if (!(VectorOp == IfTrue->getOperand(0) &&
9453 VectorOp == IfFalse->getOperand(0)))
9456 // Check if the condition code is matched with the operator type.
9457 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
9458 if ((Op == ISD::SMAX && CC != ISD::SETGT && CC != ISD::SETGE) ||
9459 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) ||
9460 (Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) ||
9461 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) ||
9462 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE &&
9463 CC != ISD::SETUGT && CC != ISD::SETUGE && CC != ISD::SETGT &&
9464 CC != ISD::SETGE) ||
9465 (Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE &&
9466 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
9470 // Expect to check only lane 0 from the vector SETCC.
9471 if (!isNullConstant(N0.getOperand(1)))
9474 // Expect to extract the true value from lane 0.
9475 if (!isNullConstant(IfTrue.getOperand(1)))
9478 // Expect to extract the false value from lane 1.
9479 if (!isOneConstant(IfFalse.getOperand(1)))
9482 return tryMatchAcrossLaneShuffleForReduction(N, SetCC, Op, DAG);
9485 /// Target-specific DAG combine for the across vector add reduction.
9486 /// This function specifically handles the final clean-up step of the vector
9487 /// add reduction produced by the LoopVectorizer. It is the log2-shuffle
9488 /// pattern, which adds all elements of a vector together.
9489 /// For example, for a <4 x i32> vector :
9490 /// %1 = vector_shuffle %0, <2,3,u,u>
9492 /// %3 = vector_shuffle %2, <1,u,u,u>
9494 /// %result = extract_vector_elt %4, 0
9497 /// %result = extract_vector_elt %0, 0
9499 performAcrossLaneAddReductionCombine(SDNode *N, SelectionDAG &DAG,
9500 const AArch64Subtarget *Subtarget) {
9501 if (!Subtarget->hasNEON())
9503 SDValue N0 = N->getOperand(0);
9504 SDValue N1 = N->getOperand(1);
9506 // Check if the input vector is fed by the ADD.
9507 if (N0->getOpcode() != ISD::ADD)
9510 // The vector extract idx must constant zero because we only expect the final
9511 // result of the reduction is placed in lane 0.
9512 if (!isNullConstant(N1))
9515 EVT VTy = N0.getValueType();
9516 if (!VTy.isVector())
9519 EVT EltTy = VTy.getVectorElementType();
9520 if (EltTy != MVT::i32 && EltTy != MVT::i16 && EltTy != MVT::i8)
9523 if (VTy.getSizeInBits() < 64)
9526 return tryMatchAcrossLaneShuffleForReduction(N, N0, ISD::ADD, DAG);
9529 /// Target-specific DAG combine function for NEON load/store intrinsics
9530 /// to merge base address updates.
9531 static SDValue performNEONPostLDSTCombine(SDNode *N,
9532 TargetLowering::DAGCombinerInfo &DCI,
9533 SelectionDAG &DAG) {
9534 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9537 unsigned AddrOpIdx = N->getNumOperands() - 1;
9538 SDValue Addr = N->getOperand(AddrOpIdx);
9540 // Search for a use of the address operand that is an increment.
9541 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9542 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9544 if (User->getOpcode() != ISD::ADD ||
9545 UI.getUse().getResNo() != Addr.getResNo())
9548 // Check that the add is independent of the load/store. Otherwise, folding
9549 // it would create a cycle.
9550 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9553 // Find the new opcode for the updating load/store.
9554 bool IsStore = false;
9555 bool IsLaneOp = false;
9556 bool IsDupOp = false;
9557 unsigned NewOpc = 0;
9558 unsigned NumVecs = 0;
9559 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9561 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9562 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
9564 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
9566 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
9568 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
9569 NumVecs = 2; IsStore = true; break;
9570 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
9571 NumVecs = 3; IsStore = true; break;
9572 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
9573 NumVecs = 4; IsStore = true; break;
9574 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
9576 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
9578 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
9580 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
9581 NumVecs = 2; IsStore = true; break;
9582 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
9583 NumVecs = 3; IsStore = true; break;
9584 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
9585 NumVecs = 4; IsStore = true; break;
9586 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
9587 NumVecs = 2; IsDupOp = true; break;
9588 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
9589 NumVecs = 3; IsDupOp = true; break;
9590 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
9591 NumVecs = 4; IsDupOp = true; break;
9592 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
9593 NumVecs = 2; IsLaneOp = true; break;
9594 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
9595 NumVecs = 3; IsLaneOp = true; break;
9596 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
9597 NumVecs = 4; IsLaneOp = true; break;
9598 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
9599 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
9600 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
9601 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
9602 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
9603 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
9608 VecTy = N->getOperand(2).getValueType();
9610 VecTy = N->getValueType(0);
9612 // If the increment is a constant, it must match the memory ref size.
9613 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9614 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9615 uint32_t IncVal = CInc->getZExtValue();
9616 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9617 if (IsLaneOp || IsDupOp)
9618 NumBytes /= VecTy.getVectorNumElements();
9619 if (IncVal != NumBytes)
9621 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
9623 SmallVector<SDValue, 8> Ops;
9624 Ops.push_back(N->getOperand(0)); // Incoming chain
9625 // Load lane and store have vector list as input.
9626 if (IsLaneOp || IsStore)
9627 for (unsigned i = 2; i < AddrOpIdx; ++i)
9628 Ops.push_back(N->getOperand(i));
9629 Ops.push_back(Addr); // Base register
9634 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
9636 for (n = 0; n < NumResultVecs; ++n)
9638 Tys[n++] = MVT::i64; // Type of write back register
9639 Tys[n] = MVT::Other; // Type of the chain
9640 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
9642 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9643 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
9644 MemInt->getMemoryVT(),
9645 MemInt->getMemOperand());
9648 std::vector<SDValue> NewResults;
9649 for (unsigned i = 0; i < NumResultVecs; ++i) {
9650 NewResults.push_back(SDValue(UpdN.getNode(), i));
9652 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
9653 DCI.CombineTo(N, NewResults);
9654 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9661 // Checks to see if the value is the prescribed width and returns information
9662 // about its extension mode.
9664 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
9665 ExtType = ISD::NON_EXTLOAD;
9666 switch(V.getNode()->getOpcode()) {
9670 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
9671 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
9672 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
9673 ExtType = LoadNode->getExtensionType();
9678 case ISD::AssertSext: {
9679 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
9680 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9681 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9682 ExtType = ISD::SEXTLOAD;
9687 case ISD::AssertZext: {
9688 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
9689 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9690 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9691 ExtType = ISD::ZEXTLOAD;
9697 case ISD::TargetConstant: {
9698 return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
9706 // This function does a whole lot of voodoo to determine if the tests are
9707 // equivalent without and with a mask. Essentially what happens is that given a
9710 // +-------------+ +-------------+ +-------------+ +-------------+
9711 // | Input | | AddConstant | | CompConstant| | CC |
9712 // +-------------+ +-------------+ +-------------+ +-------------+
9714 // V V | +----------+
9715 // +-------------+ +----+ | |
9716 // | ADD | |0xff| | |
9717 // +-------------+ +----+ | |
9720 // +-------------+ | |
9722 // +-------------+ | |
9731 // The AND node may be safely removed for some combinations of inputs. In
9732 // particular we need to take into account the extension type of the Input,
9733 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
9734 // width of the input (this can work for any width inputs, the above graph is
9735 // specific to 8 bits.
9737 // The specific equations were worked out by generating output tables for each
9738 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
9739 // problem was simplified by working with 4 bit inputs, which means we only
9740 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
9741 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
9742 // patterns present in both extensions (0,7). For every distinct set of
9743 // AddConstant and CompConstants bit patterns we can consider the masked and
9744 // unmasked versions to be equivalent if the result of this function is true for
9745 // all 16 distinct bit patterns of for the current extension type of Input (w0).
9748 // and w10, w8, #0x0f
9750 // cset w9, AArch64CC
9752 // cset w11, AArch64CC
9757 // Since the above function shows when the outputs are equivalent it defines
9758 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
9759 // would be expensive to run during compiles. The equations below were written
9760 // in a test harness that confirmed they gave equivalent outputs to the above
9761 // for all inputs function, so they can be used determine if the removal is
9764 // isEquivalentMaskless() is the code for testing if the AND can be removed
9765 // factored out of the DAG recognition as the DAG can take several forms.
9767 static bool isEquivalentMaskless(unsigned CC, unsigned width,
9768 ISD::LoadExtType ExtType, int AddConstant,
9770 // By being careful about our equations and only writing the in term
9771 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
9772 // make them generally applicable to all bit widths.
9773 int MaxUInt = (1 << width);
9775 // For the purposes of these comparisons sign extending the type is
9776 // equivalent to zero extending the add and displacing it by half the integer
9777 // width. Provided we are careful and make sure our equations are valid over
9778 // the whole range we can just adjust the input and avoid writing equations
9779 // for sign extended inputs.
9780 if (ExtType == ISD::SEXTLOAD)
9781 AddConstant -= (1 << (width-1));
9786 if ((AddConstant == 0) ||
9787 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
9788 (AddConstant >= 0 && CompConstant < 0) ||
9789 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
9794 if ((AddConstant == 0) ||
9795 (AddConstant >= 0 && CompConstant <= 0) ||
9796 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
9801 if ((AddConstant >= 0 && CompConstant < 0) ||
9802 (AddConstant <= 0 && CompConstant >= -1 &&
9803 CompConstant < AddConstant + MaxUInt))
9808 if ((AddConstant == 0) ||
9809 (AddConstant > 0 && CompConstant <= 0) ||
9810 (AddConstant < 0 && CompConstant <= AddConstant))
9815 if ((AddConstant >= 0 && CompConstant <= 0) ||
9816 (AddConstant <= 0 && CompConstant >= 0 &&
9817 CompConstant <= AddConstant + MaxUInt))
9822 if ((AddConstant > 0 && CompConstant < 0) ||
9823 (AddConstant < 0 && CompConstant >= 0 &&
9824 CompConstant < AddConstant + MaxUInt) ||
9825 (AddConstant >= 0 && CompConstant >= 0 &&
9826 CompConstant >= AddConstant) ||
9827 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
9835 case AArch64CC::Invalid:
9843 SDValue performCONDCombine(SDNode *N,
9844 TargetLowering::DAGCombinerInfo &DCI,
9845 SelectionDAG &DAG, unsigned CCIndex,
9846 unsigned CmpIndex) {
9847 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
9848 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
9849 unsigned CondOpcode = SubsNode->getOpcode();
9851 if (CondOpcode != AArch64ISD::SUBS)
9854 // There is a SUBS feeding this condition. Is it fed by a mask we can
9857 SDNode *AndNode = SubsNode->getOperand(0).getNode();
9858 unsigned MaskBits = 0;
9860 if (AndNode->getOpcode() != ISD::AND)
9863 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
9864 uint32_t CNV = CN->getZExtValue();
9867 else if (CNV == 65535)
9874 SDValue AddValue = AndNode->getOperand(0);
9876 if (AddValue.getOpcode() != ISD::ADD)
9879 // The basic dag structure is correct, grab the inputs and validate them.
9881 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
9882 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
9883 SDValue SubsInputValue = SubsNode->getOperand(1);
9885 // The mask is present and the provenance of all the values is a smaller type,
9886 // lets see if the mask is superfluous.
9888 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
9889 !isa<ConstantSDNode>(SubsInputValue.getNode()))
9892 ISD::LoadExtType ExtType;
9894 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
9895 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
9896 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
9899 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
9900 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
9901 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
9904 // The AND is not necessary, remove it.
9906 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
9907 SubsNode->getValueType(1));
9908 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
9910 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
9911 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
9913 return SDValue(N, 0);
9916 // Optimize compare with zero and branch.
9917 static SDValue performBRCONDCombine(SDNode *N,
9918 TargetLowering::DAGCombinerInfo &DCI,
9919 SelectionDAG &DAG) {
9920 if (SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3))
9922 SDValue Chain = N->getOperand(0);
9923 SDValue Dest = N->getOperand(1);
9924 SDValue CCVal = N->getOperand(2);
9925 SDValue Cmp = N->getOperand(3);
9927 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
9928 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
9929 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
9932 unsigned CmpOpc = Cmp.getOpcode();
9933 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
9936 // Only attempt folding if there is only one use of the flag and no use of the
9938 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
9941 SDValue LHS = Cmp.getOperand(0);
9942 SDValue RHS = Cmp.getOperand(1);
9944 assert(LHS.getValueType() == RHS.getValueType() &&
9945 "Expected the value type to be the same for both operands!");
9946 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
9949 if (isNullConstant(LHS))
9950 std::swap(LHS, RHS);
9952 if (!isNullConstant(RHS))
9955 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9956 LHS.getOpcode() == ISD::SRL)
9959 // Fold the compare into the branch instruction.
9961 if (CC == AArch64CC::EQ)
9962 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9964 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
9966 // Do not add new nodes to DAG combiner worklist.
9967 DCI.CombineTo(N, BR, false);
9972 // Optimize some simple tbz/tbnz cases. Returns the new operand and bit to test
9973 // as well as whether the test should be inverted. This code is required to
9974 // catch these cases (as opposed to standard dag combines) because
9975 // AArch64ISD::TBZ is matched during legalization.
9976 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
9977 SelectionDAG &DAG) {
9979 if (!Op->hasOneUse())
9982 // We don't handle undef/constant-fold cases below, as they should have
9983 // already been taken care of (e.g. and of 0, test of undefined shifted bits,
9986 // (tbz (trunc x), b) -> (tbz x, b)
9987 // This case is just here to enable more of the below cases to be caught.
9988 if (Op->getOpcode() == ISD::TRUNCATE &&
9989 Bit < Op->getValueType(0).getSizeInBits()) {
9990 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
9993 if (Op->getNumOperands() != 2)
9996 auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
10000 switch (Op->getOpcode()) {
10004 // (tbz (and x, m), b) -> (tbz x, b)
10006 if ((C->getZExtValue() >> Bit) & 1)
10007 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
10010 // (tbz (shl x, c), b) -> (tbz x, b-c)
10012 if (C->getZExtValue() <= Bit &&
10013 (Bit - C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
10014 Bit = Bit - C->getZExtValue();
10015 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
10019 // (tbz (sra x, c), b) -> (tbz x, b+c) or (tbz x, msb) if b+c is > # bits in x
10021 Bit = Bit + C->getZExtValue();
10022 if (Bit >= Op->getValueType(0).getSizeInBits())
10023 Bit = Op->getValueType(0).getSizeInBits() - 1;
10024 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
10026 // (tbz (srl x, c), b) -> (tbz x, b+c)
10028 if ((Bit + C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
10029 Bit = Bit + C->getZExtValue();
10030 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
10034 // (tbz (xor x, -1), b) -> (tbnz x, b)
10036 if ((C->getZExtValue() >> Bit) & 1)
10038 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
10042 // Optimize test single bit zero/non-zero and branch.
10043 static SDValue performTBZCombine(SDNode *N,
10044 TargetLowering::DAGCombinerInfo &DCI,
10045 SelectionDAG &DAG) {
10046 unsigned Bit = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
10047 bool Invert = false;
10048 SDValue TestSrc = N->getOperand(1);
10049 SDValue NewTestSrc = getTestBitOperand(TestSrc, Bit, Invert, DAG);
10051 if (TestSrc == NewTestSrc)
10054 unsigned NewOpc = N->getOpcode();
10056 if (NewOpc == AArch64ISD::TBZ)
10057 NewOpc = AArch64ISD::TBNZ;
10059 assert(NewOpc == AArch64ISD::TBNZ);
10060 NewOpc = AArch64ISD::TBZ;
10065 return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc,
10066 DAG.getConstant(Bit, DL, MVT::i64), N->getOperand(3));
10069 // vselect (v1i1 setcc) ->
10070 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
10071 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
10072 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
10074 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
10075 SDValue N0 = N->getOperand(0);
10076 EVT CCVT = N0.getValueType();
10078 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
10079 CCVT.getVectorElementType() != MVT::i1)
10082 EVT ResVT = N->getValueType(0);
10083 EVT CmpVT = N0.getOperand(0).getValueType();
10084 // Only combine when the result type is of the same size as the compared
10086 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
10089 SDValue IfTrue = N->getOperand(1);
10090 SDValue IfFalse = N->getOperand(2);
10092 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
10093 N0.getOperand(0), N0.getOperand(1),
10094 cast<CondCodeSDNode>(N0.getOperand(2))->get());
10095 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
10099 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
10100 /// the compare-mask instructions rather than going via NZCV, even if LHS and
10101 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
10102 /// with a vector one followed by a DUP shuffle on the result.
10103 static SDValue performSelectCombine(SDNode *N,
10104 TargetLowering::DAGCombinerInfo &DCI) {
10105 SelectionDAG &DAG = DCI.DAG;
10106 SDValue N0 = N->getOperand(0);
10107 EVT ResVT = N->getValueType(0);
10109 if (N0.getOpcode() != ISD::SETCC)
10112 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
10113 // scalar SetCCResultType. We also don't expect vectors, because we assume
10114 // that selects fed by vector SETCCs are canonicalized to VSELECT.
10115 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
10116 "Scalar-SETCC feeding SELECT has unexpected result type!");
10118 // If NumMaskElts == 0, the comparison is larger than select result. The
10119 // largest real NEON comparison is 64-bits per lane, which means the result is
10120 // at most 32-bits and an illegal vector. Just bail out for now.
10121 EVT SrcVT = N0.getOperand(0).getValueType();
10123 // Don't try to do this optimization when the setcc itself has i1 operands.
10124 // There are no legal vectors of i1, so this would be pointless.
10125 if (SrcVT == MVT::i1)
10128 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
10129 if (!ResVT.isVector() || NumMaskElts == 0)
10132 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
10133 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
10135 // Also bail out if the vector CCVT isn't the same size as ResVT.
10136 // This can happen if the SETCC operand size doesn't divide the ResVT size
10137 // (e.g., f64 vs v3f32).
10138 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
10141 // Make sure we didn't create illegal types, if we're not supposed to.
10142 assert(DCI.isBeforeLegalize() ||
10143 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
10145 // First perform a vector comparison, where lane 0 is the one we're interested
10149 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
10151 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
10152 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
10154 // Now duplicate the comparison mask we want across all other lanes.
10155 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
10156 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask);
10157 Mask = DAG.getNode(ISD::BITCAST, DL,
10158 ResVT.changeVectorElementTypeToInteger(), Mask);
10160 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
10163 /// Get rid of unnecessary NVCASTs (that don't change the type).
10164 static SDValue performNVCASTCombine(SDNode *N) {
10165 if (N->getValueType(0) == N->getOperand(0).getValueType())
10166 return N->getOperand(0);
10171 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
10172 DAGCombinerInfo &DCI) const {
10173 SelectionDAG &DAG = DCI.DAG;
10174 switch (N->getOpcode()) {
10179 return performAddSubLongCombine(N, DCI, DAG);
10181 return performXorCombine(N, DAG, DCI, Subtarget);
10183 return performMulCombine(N, DAG, DCI, Subtarget);
10184 case ISD::SINT_TO_FP:
10185 case ISD::UINT_TO_FP:
10186 return performIntToFpCombine(N, DAG, Subtarget);
10187 case ISD::FP_TO_SINT:
10188 case ISD::FP_TO_UINT:
10189 return performFpToIntCombine(N, DAG, DCI, Subtarget);
10191 return performFDivCombine(N, DAG, DCI, Subtarget);
10193 return performORCombine(N, DCI, Subtarget);
10195 return performSRLCombine(N, DCI);
10196 case ISD::INTRINSIC_WO_CHAIN:
10197 return performIntrinsicCombine(N, DCI, Subtarget);
10198 case ISD::ANY_EXTEND:
10199 case ISD::ZERO_EXTEND:
10200 case ISD::SIGN_EXTEND:
10201 return performExtendCombine(N, DCI, DAG);
10203 return performBitcastCombine(N, DCI, DAG);
10204 case ISD::CONCAT_VECTORS:
10205 return performConcatVectorsCombine(N, DCI, DAG);
10206 case ISD::SELECT: {
10207 SDValue RV = performSelectCombine(N, DCI);
10209 RV = performAcrossLaneMinMaxReductionCombine(N, DAG, Subtarget);
10213 return performVSelectCombine(N, DCI.DAG);
10215 if (performTBISimplification(N->getOperand(1), DCI, DAG))
10216 return SDValue(N, 0);
10219 return performSTORECombine(N, DCI, DAG, Subtarget);
10220 case AArch64ISD::BRCOND:
10221 return performBRCONDCombine(N, DCI, DAG);
10222 case AArch64ISD::TBNZ:
10223 case AArch64ISD::TBZ:
10224 return performTBZCombine(N, DCI, DAG);
10225 case AArch64ISD::CSEL:
10226 return performCONDCombine(N, DCI, DAG, 2, 3);
10227 case AArch64ISD::DUP:
10228 return performPostLD1Combine(N, DCI, false);
10229 case AArch64ISD::NVCAST:
10230 return performNVCASTCombine(N);
10231 case ISD::INSERT_VECTOR_ELT:
10232 return performPostLD1Combine(N, DCI, true);
10233 case ISD::EXTRACT_VECTOR_ELT:
10234 return performAcrossLaneAddReductionCombine(N, DAG, Subtarget);
10235 case ISD::INTRINSIC_VOID:
10236 case ISD::INTRINSIC_W_CHAIN:
10237 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10238 case Intrinsic::aarch64_neon_ld2:
10239 case Intrinsic::aarch64_neon_ld3:
10240 case Intrinsic::aarch64_neon_ld4:
10241 case Intrinsic::aarch64_neon_ld1x2:
10242 case Intrinsic::aarch64_neon_ld1x3:
10243 case Intrinsic::aarch64_neon_ld1x4:
10244 case Intrinsic::aarch64_neon_ld2lane:
10245 case Intrinsic::aarch64_neon_ld3lane:
10246 case Intrinsic::aarch64_neon_ld4lane:
10247 case Intrinsic::aarch64_neon_ld2r:
10248 case Intrinsic::aarch64_neon_ld3r:
10249 case Intrinsic::aarch64_neon_ld4r:
10250 case Intrinsic::aarch64_neon_st2:
10251 case Intrinsic::aarch64_neon_st3:
10252 case Intrinsic::aarch64_neon_st4:
10253 case Intrinsic::aarch64_neon_st1x2:
10254 case Intrinsic::aarch64_neon_st1x3:
10255 case Intrinsic::aarch64_neon_st1x4:
10256 case Intrinsic::aarch64_neon_st2lane:
10257 case Intrinsic::aarch64_neon_st3lane:
10258 case Intrinsic::aarch64_neon_st4lane:
10259 return performNEONPostLDSTCombine(N, DCI, DAG);
10267 // Check if the return value is used as only a return value, as otherwise
10268 // we can't perform a tail-call. In particular, we need to check for
10269 // target ISD nodes that are returns and any other "odd" constructs
10270 // that the generic analysis code won't necessarily catch.
10271 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
10272 SDValue &Chain) const {
10273 if (N->getNumValues() != 1)
10275 if (!N->hasNUsesOfValue(1, 0))
10278 SDValue TCChain = Chain;
10279 SDNode *Copy = *N->use_begin();
10280 if (Copy->getOpcode() == ISD::CopyToReg) {
10281 // If the copy has a glue operand, we conservatively assume it isn't safe to
10282 // perform a tail call.
10283 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
10286 TCChain = Copy->getOperand(0);
10287 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
10290 bool HasRet = false;
10291 for (SDNode *Node : Copy->uses()) {
10292 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
10304 // Return whether the an instruction can potentially be optimized to a tail
10305 // call. This will cause the optimizers to attempt to move, or duplicate,
10306 // return instructions to help enable tail call optimizations for this
10308 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
10309 return CI->isTailCall();
10312 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
10314 ISD::MemIndexedMode &AM,
10316 SelectionDAG &DAG) const {
10317 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
10320 Base = Op->getOperand(0);
10321 // All of the indexed addressing mode instructions take a signed
10322 // 9 bit immediate offset.
10323 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
10324 int64_t RHSC = RHS->getSExtValue();
10325 if (Op->getOpcode() == ISD::SUB)
10326 RHSC = -(uint64_t)RHSC;
10327 if (!isInt<9>(RHSC))
10329 IsInc = (Op->getOpcode() == ISD::ADD);
10330 Offset = Op->getOperand(1);
10336 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10338 ISD::MemIndexedMode &AM,
10339 SelectionDAG &DAG) const {
10342 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10343 VT = LD->getMemoryVT();
10344 Ptr = LD->getBasePtr();
10345 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10346 VT = ST->getMemoryVT();
10347 Ptr = ST->getBasePtr();
10352 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
10354 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
10358 bool AArch64TargetLowering::getPostIndexedAddressParts(
10359 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
10360 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
10363 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10364 VT = LD->getMemoryVT();
10365 Ptr = LD->getBasePtr();
10366 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10367 VT = ST->getMemoryVT();
10368 Ptr = ST->getBasePtr();
10373 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
10375 // Post-indexing updates the base, so it's not a valid transform
10376 // if that's not the same as the load's pointer.
10379 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
10383 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
10384 SelectionDAG &DAG) {
10386 SDValue Op = N->getOperand(0);
10388 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
10392 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
10393 DAG.getUNDEF(MVT::i32), Op,
10394 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
10396 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
10397 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
10400 static void ReplaceReductionResults(SDNode *N,
10401 SmallVectorImpl<SDValue> &Results,
10402 SelectionDAG &DAG, unsigned InterOp,
10403 unsigned AcrossOp) {
10407 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
10408 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
10409 SDValue InterVal = DAG.getNode(InterOp, dl, LoVT, Lo, Hi);
10410 SDValue SplitVal = DAG.getNode(AcrossOp, dl, LoVT, InterVal);
10411 Results.push_back(SplitVal);
10414 static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
10416 SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N);
10417 SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64,
10418 DAG.getNode(ISD::SRL, DL, MVT::i128, N,
10419 DAG.getConstant(64, DL, MVT::i64)));
10420 return std::make_pair(Lo, Hi);
10423 static void ReplaceCMP_SWAP_128Results(SDNode *N,
10424 SmallVectorImpl<SDValue> & Results,
10425 SelectionDAG &DAG) {
10426 assert(N->getValueType(0) == MVT::i128 &&
10427 "AtomicCmpSwap on types less than 128 should be legal");
10428 auto Desired = splitInt128(N->getOperand(2), DAG);
10429 auto New = splitInt128(N->getOperand(3), DAG);
10430 SDValue Ops[] = {N->getOperand(1), Desired.first, Desired.second,
10431 New.first, New.second, N->getOperand(0)};
10432 SDNode *CmpSwap = DAG.getMachineNode(
10433 AArch64::CMP_SWAP_128, SDLoc(N),
10434 DAG.getVTList(MVT::i64, MVT::i64, MVT::i32, MVT::Other), Ops);
10436 MachineFunction &MF = DAG.getMachineFunction();
10437 MachineSDNode::mmo_iterator MemOp = MF.allocateMemRefsArray(1);
10438 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
10439 cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
10441 Results.push_back(SDValue(CmpSwap, 0));
10442 Results.push_back(SDValue(CmpSwap, 1));
10443 Results.push_back(SDValue(CmpSwap, 3));
10446 void AArch64TargetLowering::ReplaceNodeResults(
10447 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
10448 switch (N->getOpcode()) {
10450 llvm_unreachable("Don't know how to custom expand this");
10452 ReplaceBITCASTResults(N, Results, DAG);
10454 case AArch64ISD::SADDV:
10455 ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::SADDV);
10457 case AArch64ISD::UADDV:
10458 ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::UADDV);
10460 case AArch64ISD::SMINV:
10461 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV);
10463 case AArch64ISD::UMINV:
10464 ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV);
10466 case AArch64ISD::SMAXV:
10467 ReplaceReductionResults(N, Results, DAG, ISD::SMAX, AArch64ISD::SMAXV);
10469 case AArch64ISD::UMAXV:
10470 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV);
10472 case ISD::FP_TO_UINT:
10473 case ISD::FP_TO_SINT:
10474 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
10475 // Let normal code take care of it by not adding anything to Results.
10477 case ISD::ATOMIC_CMP_SWAP:
10478 ReplaceCMP_SWAP_128Results(N, Results, DAG);
10483 bool AArch64TargetLowering::useLoadStackGuardNode() const {
10484 if (!Subtarget->isTargetAndroid())
10486 return TargetLowering::useLoadStackGuardNode();
10489 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
10490 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
10491 // reciprocal if there are three or more FDIVs.
10495 TargetLoweringBase::LegalizeTypeAction
10496 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
10497 MVT SVT = VT.getSimpleVT();
10498 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
10499 // v4i16, v2i32 instead of to promote.
10500 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
10501 || SVT == MVT::v1f32)
10502 return TypeWidenVector;
10504 return TargetLoweringBase::getPreferredVectorAction(VT);
10507 // Loads and stores less than 128-bits are already atomic; ones above that
10508 // are doomed anyway, so defer to the default libcall and blame the OS when
10509 // things go wrong.
10510 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
10511 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
10512 return Size == 128;
10515 // Loads and stores less than 128-bits are already atomic; ones above that
10516 // are doomed anyway, so defer to the default libcall and blame the OS when
10517 // things go wrong.
10518 TargetLowering::AtomicExpansionKind
10519 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
10520 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
10521 return Size == 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
10524 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
10525 TargetLowering::AtomicExpansionKind
10526 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
10527 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
10528 return Size <= 128 ? AtomicExpansionKind::LLSC : AtomicExpansionKind::None;
10531 bool AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
10532 AtomicCmpXchgInst *AI) const {
10533 // At -O0, fast-regalloc cannot cope with the live vregs necessary to
10534 // implement cmpxchg without spilling. If the address being exchanged is also
10535 // on the stack and close enough to the spill slot, this can lead to a
10536 // situation where the monitor always gets cleared and the atomic operation
10537 // can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
10538 return getTargetMachine().getOptLevel() != 0;
10541 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
10542 AtomicOrdering Ord) const {
10543 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10544 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
10545 bool IsAcquire = isAcquireOrStronger(Ord);
10547 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
10548 // intrinsic must return {i64, i64} and we have to recombine them into a
10549 // single i128 here.
10550 if (ValTy->getPrimitiveSizeInBits() == 128) {
10551 Intrinsic::ID Int =
10552 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
10553 Function *Ldxr = Intrinsic::getDeclaration(M, Int);
10555 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10556 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
10558 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
10559 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
10560 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
10561 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
10562 return Builder.CreateOr(
10563 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
10566 Type *Tys[] = { Addr->getType() };
10567 Intrinsic::ID Int =
10568 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
10569 Function *Ldxr = Intrinsic::getDeclaration(M, Int, Tys);
10571 return Builder.CreateTruncOrBitCast(
10572 Builder.CreateCall(Ldxr, Addr),
10573 cast<PointerType>(Addr->getType())->getElementType());
10576 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
10577 IRBuilder<> &Builder) const {
10578 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10579 Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex));
10582 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
10583 Value *Val, Value *Addr,
10584 AtomicOrdering Ord) const {
10585 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10586 bool IsRelease = isReleaseOrStronger(Ord);
10588 // Since the intrinsics must have legal type, the i128 intrinsics take two
10589 // parameters: "i64, i64". We must marshal Val into the appropriate form
10590 // before the call.
10591 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
10592 Intrinsic::ID Int =
10593 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
10594 Function *Stxr = Intrinsic::getDeclaration(M, Int);
10595 Type *Int64Ty = Type::getInt64Ty(M->getContext());
10597 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
10598 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
10599 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10600 return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
10603 Intrinsic::ID Int =
10604 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
10605 Type *Tys[] = { Addr->getType() };
10606 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
10608 return Builder.CreateCall(Stxr,
10609 {Builder.CreateZExtOrBitCast(
10610 Val, Stxr->getFunctionType()->getParamType(0)),
10614 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
10615 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
10616 return Ty->isArrayTy();
10619 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
10624 Value *AArch64TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
10625 if (!Subtarget->isTargetAndroid())
10626 return TargetLowering::getIRStackGuard(IRB);
10628 // Android provides a fixed TLS slot for the stack cookie. See the definition
10629 // of TLS_SLOT_STACK_GUARD in
10630 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
10631 const unsigned TlsOffset = 0x28;
10632 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
10633 Function *ThreadPointerFunc =
10634 Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
10635 return IRB.CreatePointerCast(
10636 IRB.CreateConstGEP1_32(IRB.CreateCall(ThreadPointerFunc), TlsOffset),
10637 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(0));
10640 Value *AArch64TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
10641 if (!Subtarget->isTargetAndroid())
10642 return TargetLowering::getSafeStackPointerLocation(IRB);
10644 // Android provides a fixed TLS slot for the SafeStack pointer. See the
10645 // definition of TLS_SLOT_SAFESTACK in
10646 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
10647 const unsigned TlsOffset = 0x48;
10648 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
10649 Function *ThreadPointerFunc =
10650 Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
10651 return IRB.CreatePointerCast(
10652 IRB.CreateConstGEP1_32(IRB.CreateCall(ThreadPointerFunc), TlsOffset),
10653 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(0));
10656 void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
10657 // Update IsSplitCSR in AArch64unctionInfo.
10658 AArch64FunctionInfo *AFI = Entry->getParent()->getInfo<AArch64FunctionInfo>();
10659 AFI->setIsSplitCSR(true);
10662 void AArch64TargetLowering::insertCopiesSplitCSR(
10663 MachineBasicBlock *Entry,
10664 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
10665 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
10666 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
10670 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
10671 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
10672 MachineBasicBlock::iterator MBBI = Entry->begin();
10673 for (const MCPhysReg *I = IStart; *I; ++I) {
10674 const TargetRegisterClass *RC = nullptr;
10675 if (AArch64::GPR64RegClass.contains(*I))
10676 RC = &AArch64::GPR64RegClass;
10677 else if (AArch64::FPR64RegClass.contains(*I))
10678 RC = &AArch64::FPR64RegClass;
10680 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
10682 unsigned NewVR = MRI->createVirtualRegister(RC);
10683 // Create copy from CSR to a virtual register.
10684 // FIXME: this currently does not emit CFI pseudo-instructions, it works
10685 // fine for CXX_FAST_TLS since the C++-style TLS access functions should be
10686 // nounwind. If we want to generalize this later, we may need to emit
10687 // CFI pseudo-instructions.
10688 assert(Entry->getParent()->getFunction()->hasFnAttribute(
10689 Attribute::NoUnwind) &&
10690 "Function should be nounwind in insertCopiesSplitCSR!");
10691 Entry->addLiveIn(*I);
10692 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
10695 // Insert the copy-back instructions right before the terminator.
10696 for (auto *Exit : Exits)
10697 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
10698 TII->get(TargetOpcode::COPY), *I)
10703 bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
10704 // Integer division on AArch64 is expensive. However, when aggressively
10705 // optimizing for code size, we prefer to use a div instruction, as it is
10706 // usually smaller than the alternative sequence.
10707 // The exception to this is vector division. Since AArch64 doesn't have vector
10708 // integer division, leaving the division as-is is a loss even in terms of
10709 // size, because it will have to be scalarized, while the alternative code
10710 // sequence can be performed in vector form.
10712 Attr.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
10713 return OptSize && !VT.isVector();