1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DataLayout.h"
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
38 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
40 enum ARMProcFamilyEnum : uint8_t {
62 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
63 ARMProcFamilyEnum ARMProcFamily = Others;
65 bool HasV8_1aOps = false;
66 bool HasV8_2aOps = false;
67 bool HasV8_3aOps = false;
69 bool HasFPARMv8 = false;
71 bool HasCrypto = false;
72 bool HasDotProd = false;
77 bool HasPerfMon = false;
78 bool HasFullFP16 = false;
80 bool HasLSLFast = false;
84 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
85 bool HasZeroCycleRegMove = false;
87 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
88 bool HasZeroCycleZeroing = false;
89 bool HasZeroCycleZeroingFPWorkaround = false;
91 // StrictAlign - Disallow unaligned memory accesses.
92 bool StrictAlign = false;
94 // NegativeImmediates - transform instructions with negative immediates
95 bool NegativeImmediates = true;
97 // Enable 64-bit vectorization in SLP.
98 unsigned MinVectorRegisterBitWidth = 64;
101 bool PredictableSelectIsExpensive = false;
102 bool BalanceFPOps = false;
103 bool CustomAsCheapAsMove = false;
104 bool UsePostRAScheduler = false;
105 bool Misaligned128StoreIsSlow = false;
106 bool Paired128IsSlow = false;
107 bool STRQroIsSlow = false;
108 bool UseAlternateSExtLoadCVTF32Pattern = false;
109 bool HasArithmeticBccFusion = false;
110 bool HasArithmeticCbzFusion = false;
111 bool HasFuseAES = false;
112 bool HasFuseLiterals = false;
113 bool DisableLatencySchedHeuristic = false;
114 bool UseRSqrt = false;
115 uint8_t MaxInterleaveFactor = 2;
116 uint8_t VectorInsertExtractBaseCost = 3;
117 uint16_t CacheLineSize = 0;
118 uint16_t PrefetchDistance = 0;
119 uint16_t MinPrefetchStride = 1;
120 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
121 unsigned PrefFunctionAlignment = 0;
122 unsigned PrefLoopAlignment = 0;
123 unsigned MaxJumpTableSize = 0;
124 unsigned WideningBaseCost = 0;
126 // ReserveX18 - X18 is not available as a general purpose register.
131 /// TargetTriple - What processor and OS we're targeting.
134 AArch64FrameLowering FrameLowering;
135 AArch64InstrInfo InstrInfo;
136 AArch64SelectionDAGInfo TSInfo;
137 AArch64TargetLowering TLInfo;
139 /// GlobalISel related APIs.
140 std::unique_ptr<CallLowering> CallLoweringInfo;
141 std::unique_ptr<InstructionSelector> InstSelector;
142 std::unique_ptr<LegalizerInfo> Legalizer;
143 std::unique_ptr<RegisterBankInfo> RegBankInfo;
146 /// initializeSubtargetDependencies - Initializes using CPUString and the
147 /// passed in feature string so that we can use initializer lists for
148 /// subtarget initialization.
149 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
150 StringRef CPUString);
152 /// Initialize properties based on the selected processor family.
153 void initializeProperties();
156 /// This constructor initializes the data members to match that
157 /// of the specified triple.
158 AArch64Subtarget(const Triple &TT, const std::string &CPU,
159 const std::string &FS, const TargetMachine &TM,
162 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
165 const AArch64FrameLowering *getFrameLowering() const override {
166 return &FrameLowering;
168 const AArch64TargetLowering *getTargetLowering() const override {
171 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
172 const AArch64RegisterInfo *getRegisterInfo() const override {
173 return &getInstrInfo()->getRegisterInfo();
175 const CallLowering *getCallLowering() const override;
176 const InstructionSelector *getInstructionSelector() const override;
177 const LegalizerInfo *getLegalizerInfo() const override;
178 const RegisterBankInfo *getRegBankInfo() const override;
179 const Triple &getTargetTriple() const { return TargetTriple; }
180 bool enableMachineScheduler() const override { return true; }
181 bool enablePostRAScheduler() const override {
182 return UsePostRAScheduler;
185 /// Returns ARM processor family.
186 /// Avoid this function! CPU specifics should be kept local to this class
187 /// and preferably modeled with SubtargetFeatures or properties in
188 /// initializeProperties().
189 ARMProcFamilyEnum getProcFamily() const {
190 return ARMProcFamily;
193 bool hasV8_1aOps() const { return HasV8_1aOps; }
194 bool hasV8_2aOps() const { return HasV8_2aOps; }
195 bool hasV8_3aOps() const { return HasV8_3aOps; }
197 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
199 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
201 bool hasZeroCycleZeroingFPWorkaround() const {
202 return HasZeroCycleZeroingFPWorkaround;
205 bool requiresStrictAlign() const { return StrictAlign; }
207 bool isXRaySupported() const override { return true; }
209 unsigned getMinVectorRegisterBitWidth() const {
210 return MinVectorRegisterBitWidth;
213 bool isX18Reserved() const { return ReserveX18; }
214 bool hasFPARMv8() const { return HasFPARMv8; }
215 bool hasNEON() const { return HasNEON; }
216 bool hasCrypto() const { return HasCrypto; }
217 bool hasDotProd() const { return HasDotProd; }
218 bool hasCRC() const { return HasCRC; }
219 bool hasLSE() const { return HasLSE; }
220 bool hasRAS() const { return HasRAS; }
221 bool hasRDM() const { return HasRDM; }
222 bool balanceFPOps() const { return BalanceFPOps; }
223 bool predictableSelectIsExpensive() const {
224 return PredictableSelectIsExpensive;
226 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
227 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
228 bool isPaired128Slow() const { return Paired128IsSlow; }
229 bool isSTRQroSlow() const { return STRQroIsSlow; }
230 bool useAlternateSExtLoadCVTF32Pattern() const {
231 return UseAlternateSExtLoadCVTF32Pattern;
233 bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
234 bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
235 bool hasFuseAES() const { return HasFuseAES; }
236 bool hasFuseLiterals() const { return HasFuseLiterals; }
238 /// \brief Return true if the CPU supports any kind of instruction fusion.
239 bool hasFusion() const {
240 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
241 hasFuseAES() || hasFuseLiterals();
244 bool useRSqrt() const { return UseRSqrt; }
245 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
246 unsigned getVectorInsertExtractBaseCost() const {
247 return VectorInsertExtractBaseCost;
249 unsigned getCacheLineSize() const { return CacheLineSize; }
250 unsigned getPrefetchDistance() const { return PrefetchDistance; }
251 unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
252 unsigned getMaxPrefetchIterationsAhead() const {
253 return MaxPrefetchIterationsAhead;
255 unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
256 unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
258 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
260 unsigned getWideningBaseCost() const { return WideningBaseCost; }
262 /// CPU has TBI (top byte of addresses is ignored during HW address
263 /// translation) and OS enables it.
264 bool supportsAddressTopByteIgnored() const;
266 bool hasPerfMon() const { return HasPerfMon; }
267 bool hasFullFP16() const { return HasFullFP16; }
268 bool hasSPE() const { return HasSPE; }
269 bool hasLSLFast() const { return HasLSLFast; }
270 bool hasSVE() const { return HasSVE; }
271 bool hasRCPC() const { return HasRCPC; }
273 bool isLittleEndian() const { return IsLittle; }
275 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
276 bool isTargetIOS() const { return TargetTriple.isiOS(); }
277 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
278 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
279 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
280 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
282 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
283 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
284 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
286 bool useAA() const override { return UseAA; }
288 bool useSmallAddressing() const {
289 switch (TLInfo.getTargetMachine().getCodeModel()) {
290 case CodeModel::Kernel:
291 // Kernel is currently allowed only for Fuchsia targets,
292 // where it is the same as Small for almost all purposes.
293 case CodeModel::Small:
300 /// ParseSubtargetFeatures - Parses features string setting specified
301 /// subtarget options. Definition of function is auto generated by tblgen.
302 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
304 /// ClassifyGlobalReference - Find the target operand flags that describe
305 /// how a global value should be referenced for the current subtarget.
306 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
307 const TargetMachine &TM) const;
309 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
310 const TargetMachine &TM) const;
312 void overrideSchedPolicy(MachineSchedPolicy &Policy,
313 unsigned NumRegionInstrs) const override;
315 bool enableEarlyIfConversion() const override;
317 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
319 bool isCallingConvWin64(CallingConv::ID CC) const {
322 return isTargetWindows();
323 case CallingConv::Win64:
330 } // End llvm namespace