lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AArch64Disassembler.h"
  14 #include "AArch64ExternalSymbolizer.h"
  15 #include "AArch64Subtarget.h"
  16 #include "MCTargetDesc/AArch64AddressingModes.h"
  17 #include "Utils/AArch64BaseInfo.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "aarch64-disassembler"
  28
  29 // Pull DecodeStatus and its enum values into the global namespace.
  30 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 // Forward declare these because the autogenerated code will reference them.
  33 // Definitions are further down.
  34 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  35                                               unsigned RegNo, uint64_t Address,
  36                                               const void *Decoder);
  37 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
  38                                                  unsigned RegNo,
  39                                                  uint64_t Address,
  40                                                  const void *Decoder);
  41 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  42                                              uint64_t Address,
  43                                              const void *Decoder);
  44 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  45                                              uint64_t Address,
  46                                              const void *Decoder);
  47 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  48                                              uint64_t Address,
  49                                              const void *Decoder);
  50 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  51                                             uint64_t Address,
  52                                             const void *Decoder);
  53 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  54                                              uint64_t Address,
  55                                              const void *Decoder);
  56 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
  57                                                unsigned RegNo, uint64_t Address,
  58                                                const void *Decoder);
  59 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  60                                              uint64_t Address,
  61                                              const void *Decoder);
  62 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
  63                                                unsigned RegNo, uint64_t Address,
  64                                                const void *Decoder);
  65 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                           uint64_t Address,
  67                                           const void *Decoder);
  68 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                                            uint64_t Address,
  70                                            const void *Decoder);
  71 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                             uint64_t Address,
  73                                             const void *Decoder);
  74 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                                           uint64_t Address,
  76                                           const void *Decoder);
  77 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                            uint64_t Address,
  79                                            const void *Decoder);
  80 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  81                                             uint64_t Address,
  82                                             const void *Decoder);
  83
  84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
  85                                                uint64_t Address,
  86                                                const void *Decoder);
  87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
  88                                                uint64_t Address,
  89                                                const void *Decoder);
  90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
  91                                        uint64_t Address, const void *Decoder);
  92 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
  93                                     uint64_t Address, const void *Decoder);
  94 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  95                                             uint64_t Address, const void *Decoder);
  96 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  97                                             uint64_t Address, const void *Decoder);
  98 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
  99                                                    uint32_t insn,
 100                                                    uint64_t Address,
 101                                                    const void *Decoder);
 102 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 103                                              uint64_t Address,
 104                                              const void *Decoder);
 105 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 106                                                   uint32_t insn,
 107                                                   uint64_t Address,
 108                                                   const void *Decoder);
 109 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 110                                                 uint32_t insn, uint64_t Address,
 111                                                 const void *Decoder);
 112 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
 113                                                    uint32_t insn,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
 117                                               uint64_t Address,
 118                                               const void *Decoder);
 119 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
 120                                                 uint32_t insn, uint64_t Address,
 121                                                 const void *Decoder);
 122 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
 123                                                 uint32_t insn, uint64_t Address,
 124                                                 const void *Decoder);
 125 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 126                                             uint64_t Address,
 127                                             const void *Decoder);
 128 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
 129                                                 uint32_t insn, uint64_t Address,
 130                                                 const void *Decoder);
 131 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
 132                                          uint64_t Address, const void *Decoder);
 133 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
 134                                         uint64_t Address, const void *Decoder);
 135 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
 136                                               uint64_t Address,
 137                                               const void *Decoder);
 138 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
 139                                                   uint32_t insn,
 140                                                   uint64_t Address,
 141                                                   const void *Decoder);
 142 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
 143                                         uint64_t Address, const void *Decoder);
 144
 145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 146                                               uint64_t Address,
 147                                               const void *Decoder);
 148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 149                                          uint64_t Addr, const void *Decoder);
 150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 151                                                uint64_t Addr,
 152                                                const void *Decoder);
 153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 154                                          uint64_t Addr, const void *Decoder);
 155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 156                                                uint64_t Addr,
 157                                                const void *Decoder);
 158 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 159                                          uint64_t Addr, const void *Decoder);
 160 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 161                                                uint64_t Addr,
 162                                                const void *Decoder);
 163 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 164                                         uint64_t Addr, const void *Decoder);
 165 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 166                                          uint64_t Addr, const void *Decoder);
 167 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 168                                          uint64_t Addr, const void *Decoder);
 169 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 170                                          uint64_t Addr, const void *Decoder);
 171 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 172                                         uint64_t Addr, const void *Decoder);
 173
 174 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 175   switch (In) {
 176     case MCDisassembler::Success:
 177       // Out stays the same.
 178       return true;
 179     case MCDisassembler::SoftFail:
 180       Out = In;
 181       return true;
 182     case MCDisassembler::Fail:
 183       Out = In;
 184       return false;
 185   }
 186   llvm_unreachable("Invalid DecodeStatus!");
 187 }
 188
 189 #include "AArch64GenDisassemblerTables.inc"
 190 #include "AArch64GenInstrInfo.inc"
 191
 192 #define Success llvm::MCDisassembler::Success
 193 #define Fail llvm::MCDisassembler::Fail
 194 #define SoftFail llvm::MCDisassembler::SoftFail
 195
 196 static MCDisassembler *createAArch64Disassembler(const Target &T,
 197                                                const MCSubtargetInfo &STI,
 198                                                MCContext &Ctx) {
 199   return new AArch64Disassembler(STI, Ctx);
 200 }
 201
 202 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 203                                                const MemoryObject &Region,
 204                                                uint64_t Address,
 205                                                raw_ostream &os,
 206                                                raw_ostream &cs) const {
 207   CommentStream = &cs;
 208
 209   uint8_t bytes[4];
 210
 211   Size = 0;
 212   // We want to read exactly 4 bytes of data.
 213   if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1)
 214     return Fail;
 215   Size = 4;
 216
 217   // Encoded as a small-endian 32-bit word in the stream.
 218   uint32_t insn =
 219       (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0);
 220
 221   // Calling the auto-generated decoder function.
 222   return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
 223 }
 224
 225 static MCSymbolizer *
 226 createAArch64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
 227                               LLVMSymbolLookupCallback SymbolLookUp,
 228                               void *DisInfo, MCContext *Ctx,
 229                               MCRelocationInfo *RelInfo) {
 230   return new llvm::AArch64ExternalSymbolizer(
 231                                      *Ctx,
 232                                      std::unique_ptr<MCRelocationInfo>(RelInfo),
 233                                      GetOpInfo, SymbolLookUp, DisInfo);
 234 }
 235
 236 extern "C" void LLVMInitializeAArch64Disassembler() {
 237   TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
 238                                          createAArch64Disassembler);
 239   TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
 240                                          createAArch64Disassembler);
 241   TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
 242                                        createAArch64ExternalSymbolizer);
 243   TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
 244                                        createAArch64ExternalSymbolizer);
 245
 246   TargetRegistry::RegisterMCDisassembler(TheARM64leTarget,
 247                                          createAArch64Disassembler);
 248   TargetRegistry::RegisterMCDisassembler(TheARM64beTarget,
 249                                          createAArch64Disassembler);
 250   TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget,
 251                                        createAArch64ExternalSymbolizer);
 252   TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
 253                                        createAArch64ExternalSymbolizer);
 254 }
 255
 256 static const unsigned FPR128DecoderTable[] = {
 257     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 258     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 259     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 260     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 261     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 262     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 263     AArch64::Q30, AArch64::Q31
 264 };
 265
 266 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
 267                                               uint64_t Addr,
 268                                               const void *Decoder) {
 269   if (RegNo > 31)
 270     return Fail;
 271
 272   unsigned Register = FPR128DecoderTable[RegNo];
 273   Inst.addOperand(MCOperand::CreateReg(Register));
 274   return Success;
 275 }
 276
 277 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
 278                                                  uint64_t Addr,
 279                                                  const void *Decoder) {
 280   if (RegNo > 15)
 281     return Fail;
 282   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 283 }
 284
 285 static const unsigned FPR64DecoderTable[] = {
 286     AArch64::D0,  AArch64::D1,  AArch64::D2,  AArch64::D3,  AArch64::D4,
 287     AArch64::D5,  AArch64::D6,  AArch64::D7,  AArch64::D8,  AArch64::D9,
 288     AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
 289     AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
 290     AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
 291     AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
 292     AArch64::D30, AArch64::D31
 293 };
 294
 295 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 296                                              uint64_t Addr,
 297                                              const void *Decoder) {
 298   if (RegNo > 31)
 299     return Fail;
 300
 301   unsigned Register = FPR64DecoderTable[RegNo];
 302   Inst.addOperand(MCOperand::CreateReg(Register));
 303   return Success;
 304 }
 305
 306 static const unsigned FPR32DecoderTable[] = {
 307     AArch64::S0,  AArch64::S1,  AArch64::S2,  AArch64::S3,  AArch64::S4,
 308     AArch64::S5,  AArch64::S6,  AArch64::S7,  AArch64::S8,  AArch64::S9,
 309     AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
 310     AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
 311     AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
 312     AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
 313     AArch64::S30, AArch64::S31
 314 };
 315
 316 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 317                                              uint64_t Addr,
 318                                              const void *Decoder) {
 319   if (RegNo > 31)
 320     return Fail;
 321
 322   unsigned Register = FPR32DecoderTable[RegNo];
 323   Inst.addOperand(MCOperand::CreateReg(Register));
 324   return Success;
 325 }
 326
 327 static const unsigned FPR16DecoderTable[] = {
 328     AArch64::H0,  AArch64::H1,  AArch64::H2,  AArch64::H3,  AArch64::H4,
 329     AArch64::H5,  AArch64::H6,  AArch64::H7,  AArch64::H8,  AArch64::H9,
 330     AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
 331     AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
 332     AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
 333     AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
 334     AArch64::H30, AArch64::H31
 335 };
 336
 337 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
 338                                              uint64_t Addr,
 339                                              const void *Decoder) {
 340   if (RegNo > 31)
 341     return Fail;
 342
 343   unsigned Register = FPR16DecoderTable[RegNo];
 344   Inst.addOperand(MCOperand::CreateReg(Register));
 345   return Success;
 346 }
 347
 348 static const unsigned FPR8DecoderTable[] = {
 349     AArch64::B0,  AArch64::B1,  AArch64::B2,  AArch64::B3,  AArch64::B4,
 350     AArch64::B5,  AArch64::B6,  AArch64::B7,  AArch64::B8,  AArch64::B9,
 351     AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
 352     AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
 353     AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
 354     AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
 355     AArch64::B30, AArch64::B31
 356 };
 357
 358 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 359                                             uint64_t Addr,
 360                                             const void *Decoder) {
 361   if (RegNo > 31)
 362     return Fail;
 363
 364   unsigned Register = FPR8DecoderTable[RegNo];
 365   Inst.addOperand(MCOperand::CreateReg(Register));
 366   return Success;
 367 }
 368
 369 static const unsigned GPR64DecoderTable[] = {
 370     AArch64::X0,  AArch64::X1,  AArch64::X2,  AArch64::X3,  AArch64::X4,
 371     AArch64::X5,  AArch64::X6,  AArch64::X7,  AArch64::X8,  AArch64::X9,
 372     AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
 373     AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
 374     AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
 375     AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
 376     AArch64::LR,  AArch64::XZR
 377 };
 378
 379 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 380                                              uint64_t Addr,
 381                                              const void *Decoder) {
 382   if (RegNo > 31)
 383     return Fail;
 384
 385   unsigned Register = GPR64DecoderTable[RegNo];
 386   Inst.addOperand(MCOperand::CreateReg(Register));
 387   return Success;
 388 }
 389
 390 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
 391                                                uint64_t Addr,
 392                                                const void *Decoder) {
 393   if (RegNo > 31)
 394     return Fail;
 395   unsigned Register = GPR64DecoderTable[RegNo];
 396   if (Register == AArch64::XZR)
 397     Register = AArch64::SP;
 398   Inst.addOperand(MCOperand::CreateReg(Register));
 399   return Success;
 400 }
 401
 402 static const unsigned GPR32DecoderTable[] = {
 403     AArch64::W0,  AArch64::W1,  AArch64::W2,  AArch64::W3,  AArch64::W4,
 404     AArch64::W5,  AArch64::W6,  AArch64::W7,  AArch64::W8,  AArch64::W9,
 405     AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
 406     AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
 407     AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
 408     AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
 409     AArch64::W30, AArch64::WZR
 410 };
 411
 412 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 413                                              uint64_t Addr,
 414                                              const void *Decoder) {
 415   if (RegNo > 31)
 416     return Fail;
 417
 418   unsigned Register = GPR32DecoderTable[RegNo];
 419   Inst.addOperand(MCOperand::CreateReg(Register));
 420   return Success;
 421 }
 422
 423 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
 424                                                uint64_t Addr,
 425                                                const void *Decoder) {
 426   if (RegNo > 31)
 427     return Fail;
 428
 429   unsigned Register = GPR32DecoderTable[RegNo];
 430   if (Register == AArch64::WZR)
 431     Register = AArch64::WSP;
 432   Inst.addOperand(MCOperand::CreateReg(Register));
 433   return Success;
 434 }
 435
 436 static const unsigned VectorDecoderTable[] = {
 437     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 438     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 439     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 440     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 441     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 442     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 443     AArch64::Q30, AArch64::Q31
 444 };
 445
 446 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
 447                                               uint64_t Addr,
 448                                               const void *Decoder) {
 449   if (RegNo > 31)
 450     return Fail;
 451
 452   unsigned Register = VectorDecoderTable[RegNo];
 453   Inst.addOperand(MCOperand::CreateReg(Register));
 454   return Success;
 455 }
 456
 457 static const unsigned QQDecoderTable[] = {
 458   AArch64::Q0_Q1,   AArch64::Q1_Q2,   AArch64::Q2_Q3,   AArch64::Q3_Q4,
 459   AArch64::Q4_Q5,   AArch64::Q5_Q6,   AArch64::Q6_Q7,   AArch64::Q7_Q8,
 460   AArch64::Q8_Q9,   AArch64::Q9_Q10,  AArch64::Q10_Q11, AArch64::Q11_Q12,
 461   AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
 462   AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
 463   AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
 464   AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
 465   AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
 466 };
 467
 468 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
 469                                           uint64_t Addr, const void *Decoder) {
 470   if (RegNo > 31)
 471     return Fail;
 472   unsigned Register = QQDecoderTable[RegNo];
 473   Inst.addOperand(MCOperand::CreateReg(Register));
 474   return Success;
 475 }
 476
 477 static const unsigned QQQDecoderTable[] = {
 478   AArch64::Q0_Q1_Q2,    AArch64::Q1_Q2_Q3,    AArch64::Q2_Q3_Q4,
 479   AArch64::Q3_Q4_Q5,    AArch64::Q4_Q5_Q6,    AArch64::Q5_Q6_Q7,
 480   AArch64::Q6_Q7_Q8,    AArch64::Q7_Q8_Q9,    AArch64::Q8_Q9_Q10,
 481   AArch64::Q9_Q10_Q11,  AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
 482   AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
 483   AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
 484   AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
 485   AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
 486   AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
 487   AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
 488   AArch64::Q30_Q31_Q0,  AArch64::Q31_Q0_Q1
 489 };
 490
 491 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 492                                            uint64_t Addr, const void *Decoder) {
 493   if (RegNo > 31)
 494     return Fail;
 495   unsigned Register = QQQDecoderTable[RegNo];
 496   Inst.addOperand(MCOperand::CreateReg(Register));
 497   return Success;
 498 }
 499
 500 static const unsigned QQQQDecoderTable[] = {
 501   AArch64::Q0_Q1_Q2_Q3,     AArch64::Q1_Q2_Q3_Q4,     AArch64::Q2_Q3_Q4_Q5,
 502   AArch64::Q3_Q4_Q5_Q6,     AArch64::Q4_Q5_Q6_Q7,     AArch64::Q5_Q6_Q7_Q8,
 503   AArch64::Q6_Q7_Q8_Q9,     AArch64::Q7_Q8_Q9_Q10,    AArch64::Q8_Q9_Q10_Q11,
 504   AArch64::Q9_Q10_Q11_Q12,  AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
 505   AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
 506   AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
 507   AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
 508   AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
 509   AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
 510   AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
 511   AArch64::Q30_Q31_Q0_Q1,   AArch64::Q31_Q0_Q1_Q2
 512 };
 513
 514 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 515                                             uint64_t Addr,
 516                                             const void *Decoder) {
 517   if (RegNo > 31)
 518     return Fail;
 519   unsigned Register = QQQQDecoderTable[RegNo];
 520   Inst.addOperand(MCOperand::CreateReg(Register));
 521   return Success;
 522 }
 523
 524 static const unsigned DDDecoderTable[] = {
 525   AArch64::D0_D1,   AArch64::D1_D2,   AArch64::D2_D3,   AArch64::D3_D4,
 526   AArch64::D4_D5,   AArch64::D5_D6,   AArch64::D6_D7,   AArch64::D7_D8,
 527   AArch64::D8_D9,   AArch64::D9_D10,  AArch64::D10_D11, AArch64::D11_D12,
 528   AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
 529   AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
 530   AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
 531   AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
 532   AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
 533 };
 534
 535 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
 536                                           uint64_t Addr, const void *Decoder) {
 537   if (RegNo > 31)
 538     return Fail;
 539   unsigned Register = DDDecoderTable[RegNo];
 540   Inst.addOperand(MCOperand::CreateReg(Register));
 541   return Success;
 542 }
 543
 544 static const unsigned DDDDecoderTable[] = {
 545   AArch64::D0_D1_D2,    AArch64::D1_D2_D3,    AArch64::D2_D3_D4,
 546   AArch64::D3_D4_D5,    AArch64::D4_D5_D6,    AArch64::D5_D6_D7,
 547   AArch64::D6_D7_D8,    AArch64::D7_D8_D9,    AArch64::D8_D9_D10,
 548   AArch64::D9_D10_D11,  AArch64::D10_D11_D12, AArch64::D11_D12_D13,
 549   AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
 550   AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
 551   AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
 552   AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
 553   AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
 554   AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
 555   AArch64::D30_D31_D0,  AArch64::D31_D0_D1
 556 };
 557
 558 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 559                                            uint64_t Addr, const void *Decoder) {
 560   if (RegNo > 31)
 561     return Fail;
 562   unsigned Register = DDDDecoderTable[RegNo];
 563   Inst.addOperand(MCOperand::CreateReg(Register));
 564   return Success;
 565 }
 566
 567 static const unsigned DDDDDecoderTable[] = {
 568   AArch64::D0_D1_D2_D3,     AArch64::D1_D2_D3_D4,     AArch64::D2_D3_D4_D5,
 569   AArch64::D3_D4_D5_D6,     AArch64::D4_D5_D6_D7,     AArch64::D5_D6_D7_D8,
 570   AArch64::D6_D7_D8_D9,     AArch64::D7_D8_D9_D10,    AArch64::D8_D9_D10_D11,
 571   AArch64::D9_D10_D11_D12,  AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
 572   AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
 573   AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
 574   AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
 575   AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
 576   AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
 577   AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
 578   AArch64::D30_D31_D0_D1,   AArch64::D31_D0_D1_D2
 579 };
 580
 581 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 582                                             uint64_t Addr,
 583                                             const void *Decoder) {
 584   if (RegNo > 31)
 585     return Fail;
 586   unsigned Register = DDDDDecoderTable[RegNo];
 587   Inst.addOperand(MCOperand::CreateReg(Register));
 588   return Success;
 589 }
 590
 591 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
 592                                                uint64_t Addr,
 593                                                const void *Decoder) {
 594   // scale{5} is asserted as 1 in tblgen.
 595   Imm |= 0x20;
 596   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 597   return Success;
 598 }
 599
 600 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
 601                                                uint64_t Addr,
 602                                                const void *Decoder) {
 603   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 604   return Success;
 605 }
 606
 607 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
 608                                        uint64_t Addr, const void *Decoder) {
 609   int64_t ImmVal = Imm;
 610   const AArch64Disassembler *Dis =
 611       static_cast<const AArch64Disassembler *>(Decoder);
 612
 613   // Sign-extend 19-bit immediate.
 614   if (ImmVal & (1 << (19 - 1)))
 615     ImmVal |= ~((1LL << 19) - 1);
 616
 617   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr,
 618                                      Inst.getOpcode() != AArch64::LDRXl, 0, 4))
 619     Inst.addOperand(MCOperand::CreateImm(ImmVal));
 620   return Success;
 621 }
 622
 623 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
 624                                     uint64_t Address, const void *Decoder) {
 625   Inst.addOperand(MCOperand::CreateImm((Imm  >> 1) & 1));
 626   Inst.addOperand(MCOperand::CreateImm(Imm & 1));
 627   return Success;
 628 }
 629
 630 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 631                                             uint64_t Address,
 632                                             const void *Decoder) {
 633   const AArch64Disassembler *Dis =
 634       static_cast<const AArch64Disassembler *>(Decoder);
 635   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 636
 637   Imm |= 0x8000;
 638   Inst.addOperand(MCOperand::CreateImm(Imm));
 639
 640   bool ValidNamed;
 641   (void)AArch64SysReg::MRSMapper(STI.getFeatureBits())
 642       .toString(Imm, ValidNamed);
 643
 644   return ValidNamed ? Success : Fail;
 645 }
 646
 647 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 648                                             uint64_t Address,
 649                                             const void *Decoder) {
 650   const AArch64Disassembler *Dis =
 651       static_cast<const AArch64Disassembler *>(Decoder);
 652   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 653
 654   Imm |= 0x8000;
 655   Inst.addOperand(MCOperand::CreateImm(Imm));
 656
 657   bool ValidNamed;
 658   (void)AArch64SysReg::MSRMapper(STI.getFeatureBits())
 659       .toString(Imm, ValidNamed);
 660
 661   return ValidNamed ? Success : Fail;
 662 }
 663
 664 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 665                                               uint64_t Address,
 666                                               const void *Decoder) {
 667   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 668   // be 1 in assembly but has no other real manifestation.
 669   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 670   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 671   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 672
 673   if (IsToVec) {
 674     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 675     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 676   } else {
 677     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 678     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 679   }
 680
 681   // Add the lane
 682   Inst.addOperand(MCOperand::CreateImm(1));
 683
 684   return Success;
 685 }
 686
 687 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
 688                                        unsigned Add) {
 689   Inst.addOperand(MCOperand::CreateImm(Add - Imm));
 690   return Success;
 691 }
 692
 693 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
 694                                        unsigned Add) {
 695   Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
 696   return Success;
 697 }
 698
 699 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 700                                          uint64_t Addr, const void *Decoder) {
 701   return DecodeVecShiftRImm(Inst, Imm, 64);
 702 }
 703
 704 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 705                                                uint64_t Addr,
 706                                                const void *Decoder) {
 707   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 708 }
 709
 710 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 711                                          uint64_t Addr, const void *Decoder) {
 712   return DecodeVecShiftRImm(Inst, Imm, 32);
 713 }
 714
 715 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 716                                                uint64_t Addr,
 717                                                const void *Decoder) {
 718   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 719 }
 720
 721 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 722                                          uint64_t Addr, const void *Decoder) {
 723   return DecodeVecShiftRImm(Inst, Imm, 16);
 724 }
 725
 726 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 727                                                uint64_t Addr,
 728                                                const void *Decoder) {
 729   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 730 }
 731
 732 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 733                                         uint64_t Addr, const void *Decoder) {
 734   return DecodeVecShiftRImm(Inst, Imm, 8);
 735 }
 736
 737 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 738                                          uint64_t Addr, const void *Decoder) {
 739   return DecodeVecShiftLImm(Inst, Imm, 64);
 740 }
 741
 742 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 743                                          uint64_t Addr, const void *Decoder) {
 744   return DecodeVecShiftLImm(Inst, Imm, 32);
 745 }
 746
 747 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 748                                          uint64_t Addr, const void *Decoder) {
 749   return DecodeVecShiftLImm(Inst, Imm, 16);
 750 }
 751
 752 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 753                                         uint64_t Addr, const void *Decoder) {
 754   return DecodeVecShiftLImm(Inst, Imm, 8);
 755 }
 756
 757 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
 758                                                    uint32_t insn, uint64_t Addr,
 759                                                    const void *Decoder) {
 760   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 761   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 762   unsigned Rm = fieldFromInstruction(insn, 16, 5);
 763   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
 764   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
 765   unsigned shift = (shiftHi << 6) | shiftLo;
 766   switch (Inst.getOpcode()) {
 767   default:
 768     return Fail;
 769   case AArch64::ADDWrs:
 770   case AArch64::ADDSWrs:
 771   case AArch64::SUBWrs:
 772   case AArch64::SUBSWrs:
 773     // if shift == '11' then ReservedValue()
 774     if (shiftHi == 0x3)
 775       return Fail;
 776     // Deliberate fallthrough
 777   case AArch64::ANDWrs:
 778   case AArch64::ANDSWrs:
 779   case AArch64::BICWrs:
 780   case AArch64::BICSWrs:
 781   case AArch64::ORRWrs:
 782   case AArch64::ORNWrs:
 783   case AArch64::EORWrs:
 784   case AArch64::EONWrs: {
 785     // if sf == '0' and imm6<5> == '1' then ReservedValue()
 786     if (shiftLo >> 5 == 1)
 787       return Fail;
 788     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 789     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
 790     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 791     break;
 792   }
 793   case AArch64::ADDXrs:
 794   case AArch64::ADDSXrs:
 795   case AArch64::SUBXrs:
 796   case AArch64::SUBSXrs:
 797     // if shift == '11' then ReservedValue()
 798     if (shiftHi == 0x3)
 799       return Fail;
 800     // Deliberate fallthrough
 801   case AArch64::ANDXrs:
 802   case AArch64::ANDSXrs:
 803   case AArch64::BICXrs:
 804   case AArch64::BICSXrs:
 805   case AArch64::ORRXrs:
 806   case AArch64::ORNXrs:
 807   case AArch64::EORXrs:
 808   case AArch64::EONXrs:
 809     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 810     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
 811     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 812     break;
 813   }
 814
 815   Inst.addOperand(MCOperand::CreateImm(shift));
 816   return Success;
 817 }
 818
 819 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 820                                              uint64_t Addr,
 821                                              const void *Decoder) {
 822   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 823   unsigned imm = fieldFromInstruction(insn, 5, 16);
 824   unsigned shift = fieldFromInstruction(insn, 21, 2);
 825   shift <<= 4;
 826   switch (Inst.getOpcode()) {
 827   default:
 828     return Fail;
 829   case AArch64::MOVZWi:
 830   case AArch64::MOVNWi:
 831   case AArch64::MOVKWi:
 832     if (shift & (1U << 5))
 833       return Fail;
 834     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 835     break;
 836   case AArch64::MOVZXi:
 837   case AArch64::MOVNXi:
 838   case AArch64::MOVKXi:
 839     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 840     break;
 841   }
 842
 843   if (Inst.getOpcode() == AArch64::MOVKWi ||
 844       Inst.getOpcode() == AArch64::MOVKXi)
 845     Inst.addOperand(Inst.getOperand(0));
 846
 847   Inst.addOperand(MCOperand::CreateImm(imm));
 848   Inst.addOperand(MCOperand::CreateImm(shift));
 849   return Success;
 850 }
 851
 852 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 853                                                   uint32_t insn, uint64_t Addr,
 854                                                   const void *Decoder) {
 855   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 856   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 857   unsigned offset = fieldFromInstruction(insn, 10, 12);
 858   const AArch64Disassembler *Dis =
 859       static_cast<const AArch64Disassembler *>(Decoder);
 860
 861   switch (Inst.getOpcode()) {
 862   default:
 863     return Fail;
 864   case AArch64::PRFMui:
 865     // Rt is an immediate in prefetch.
 866     Inst.addOperand(MCOperand::CreateImm(Rt));
 867     break;
 868   case AArch64::STRBBui:
 869   case AArch64::LDRBBui:
 870   case AArch64::LDRSBWui:
 871   case AArch64::STRHHui:
 872   case AArch64::LDRHHui:
 873   case AArch64::LDRSHWui:
 874   case AArch64::STRWui:
 875   case AArch64::LDRWui:
 876     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
 877     break;
 878   case AArch64::LDRSBXui:
 879   case AArch64::LDRSHXui:
 880   case AArch64::LDRSWui:
 881   case AArch64::STRXui:
 882   case AArch64::LDRXui:
 883     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
 884     break;
 885   case AArch64::LDRQui:
 886   case AArch64::STRQui:
 887     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
 888     break;
 889   case AArch64::LDRDui:
 890   case AArch64::STRDui:
 891     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
 892     break;
 893   case AArch64::LDRSui:
 894   case AArch64::STRSui:
 895     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
 896     break;
 897   case AArch64::LDRHui:
 898   case AArch64::STRHui:
 899     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
 900     break;
 901   case AArch64::LDRBui:
 902   case AArch64::STRBui:
 903     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
 904     break;
 905   }
 906
 907   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 908   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
 909     Inst.addOperand(MCOperand::CreateImm(offset));
 910   return Success;
 911 }
 912
 913 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 914                                                 uint32_t insn, uint64_t Addr,
 915                                                 const void *Decoder) {
 916   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 917   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 918   int64_t offset = fieldFromInstruction(insn, 12, 9);
 919
 920   // offset is a 9-bit signed immediate, so sign extend it to
 921   // fill the unsigned.
 922   if (offset & (1 << (9 - 1)))
 923     offset |= ~((1LL << 9) - 1);
 924
 925   // First operand is always the writeback to the address register, if needed.
 926   switch (Inst.getOpcode()) {
 927   default:
 928     break;
 929   case AArch64::LDRSBWpre:
 930   case AArch64::LDRSHWpre:
 931   case AArch64::STRBBpre:
 932   case AArch64::LDRBBpre:
 933   case AArch64::STRHHpre:
 934   case AArch64::LDRHHpre:
 935   case AArch64::STRWpre:
 936   case AArch64::LDRWpre:
 937   case AArch64::LDRSBWpost:
 938   case AArch64::LDRSHWpost:
 939   case AArch64::STRBBpost:
 940   case AArch64::LDRBBpost:
 941   case AArch64::STRHHpost:
 942   case AArch64::LDRHHpost:
 943   case AArch64::STRWpost:
 944   case AArch64::LDRWpost:
 945   case AArch64::LDRSBXpre:
 946   case AArch64::LDRSHXpre:
 947   case AArch64::STRXpre:
 948   case AArch64::LDRSWpre:
 949   case AArch64::LDRXpre:
 950   case AArch64::LDRSBXpost:
 951   case AArch64::LDRSHXpost:
 952   case AArch64::STRXpost:
 953   case AArch64::LDRSWpost:
 954   case AArch64::LDRXpost:
 955   case AArch64::LDRQpre:
 956   case AArch64::STRQpre:
 957   case AArch64::LDRQpost:
 958   case AArch64::STRQpost:
 959   case AArch64::LDRDpre:
 960   case AArch64::STRDpre:
 961   case AArch64::LDRDpost:
 962   case AArch64::STRDpost:
 963   case AArch64::LDRSpre:
 964   case AArch64::STRSpre:
 965   case AArch64::LDRSpost:
 966   case AArch64::STRSpost:
 967   case AArch64::LDRHpre:
 968   case AArch64::STRHpre:
 969   case AArch64::LDRHpost:
 970   case AArch64::STRHpost:
 971   case AArch64::LDRBpre:
 972   case AArch64::STRBpre:
 973   case AArch64::LDRBpost:
 974   case AArch64::STRBpost:
 975     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 976     break;
 977   }
 978
 979   switch (Inst.getOpcode()) {
 980   default:
 981     return Fail;
 982   case AArch64::PRFUMi:
 983     // Rt is an immediate in prefetch.
 984     Inst.addOperand(MCOperand::CreateImm(Rt));
 985     break;
 986   case AArch64::STURBBi:
 987   case AArch64::LDURBBi:
 988   case AArch64::LDURSBWi:
 989   case AArch64::STURHHi:
 990   case AArch64::LDURHHi:
 991   case AArch64::LDURSHWi:
 992   case AArch64::STURWi:
 993   case AArch64::LDURWi:
 994   case AArch64::LDTRSBWi:
 995   case AArch64::LDTRSHWi:
 996   case AArch64::STTRWi:
 997   case AArch64::LDTRWi:
 998   case AArch64::STTRHi:
 999   case AArch64::LDTRHi:
1000   case AArch64::LDTRBi:
1001   case AArch64::STTRBi:
1002   case AArch64::LDRSBWpre:
1003   case AArch64::LDRSHWpre:
1004   case AArch64::STRBBpre:
1005   case AArch64::LDRBBpre:
1006   case AArch64::STRHHpre:
1007   case AArch64::LDRHHpre:
1008   case AArch64::STRWpre:
1009   case AArch64::LDRWpre:
1010   case AArch64::LDRSBWpost:
1011   case AArch64::LDRSHWpost:
1012   case AArch64::STRBBpost:
1013   case AArch64::LDRBBpost:
1014   case AArch64::STRHHpost:
1015   case AArch64::LDRHHpost:
1016   case AArch64::STRWpost:
1017   case AArch64::LDRWpost:
1018     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1019     break;
1020   case AArch64::LDURSBXi:
1021   case AArch64::LDURSHXi:
1022   case AArch64::LDURSWi:
1023   case AArch64::STURXi:
1024   case AArch64::LDURXi:
1025   case AArch64::LDTRSBXi:
1026   case AArch64::LDTRSHXi:
1027   case AArch64::LDTRSWi:
1028   case AArch64::STTRXi:
1029   case AArch64::LDTRXi:
1030   case AArch64::LDRSBXpre:
1031   case AArch64::LDRSHXpre:
1032   case AArch64::STRXpre:
1033   case AArch64::LDRSWpre:
1034   case AArch64::LDRXpre:
1035   case AArch64::LDRSBXpost:
1036   case AArch64::LDRSHXpost:
1037   case AArch64::STRXpost:
1038   case AArch64::LDRSWpost:
1039   case AArch64::LDRXpost:
1040     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1041     break;
1042   case AArch64::LDURQi:
1043   case AArch64::STURQi:
1044   case AArch64::LDRQpre:
1045   case AArch64::STRQpre:
1046   case AArch64::LDRQpost:
1047   case AArch64::STRQpost:
1048     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1049     break;
1050   case AArch64::LDURDi:
1051   case AArch64::STURDi:
1052   case AArch64::LDRDpre:
1053   case AArch64::STRDpre:
1054   case AArch64::LDRDpost:
1055   case AArch64::STRDpost:
1056     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1057     break;
1058   case AArch64::LDURSi:
1059   case AArch64::STURSi:
1060   case AArch64::LDRSpre:
1061   case AArch64::STRSpre:
1062   case AArch64::LDRSpost:
1063   case AArch64::STRSpost:
1064     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1065     break;
1066   case AArch64::LDURHi:
1067   case AArch64::STURHi:
1068   case AArch64::LDRHpre:
1069   case AArch64::STRHpre:
1070   case AArch64::LDRHpost:
1071   case AArch64::STRHpost:
1072     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1073     break;
1074   case AArch64::LDURBi:
1075   case AArch64::STURBi:
1076   case AArch64::LDRBpre:
1077   case AArch64::STRBpre:
1078   case AArch64::LDRBpost:
1079   case AArch64::STRBpost:
1080     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1081     break;
1082   }
1083
1084   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1085   Inst.addOperand(MCOperand::CreateImm(offset));
1086
1087   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1088   bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1089   bool IsFP = fieldFromInstruction(insn, 26, 1);
1090
1091   // Cannot write back to a transfer register (but xzr != sp).
1092   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1093     return SoftFail;
1094
1095   return Success;
1096 }
1097
1098 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
1099                                                    uint32_t insn, uint64_t Addr,
1100                                                    const void *Decoder) {
1101   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1102   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1103   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1104   unsigned Rs = fieldFromInstruction(insn, 16, 5);
1105
1106   unsigned Opcode = Inst.getOpcode();
1107   switch (Opcode) {
1108   default:
1109     return Fail;
1110   case AArch64::STLXRW:
1111   case AArch64::STLXRB:
1112   case AArch64::STLXRH:
1113   case AArch64::STXRW:
1114   case AArch64::STXRB:
1115   case AArch64::STXRH:
1116     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1117   // FALLTHROUGH
1118   case AArch64::LDARW:
1119   case AArch64::LDARB:
1120   case AArch64::LDARH:
1121   case AArch64::LDAXRW:
1122   case AArch64::LDAXRB:
1123   case AArch64::LDAXRH:
1124   case AArch64::LDXRW:
1125   case AArch64::LDXRB:
1126   case AArch64::LDXRH:
1127   case AArch64::STLRW:
1128   case AArch64::STLRB:
1129   case AArch64::STLRH:
1130     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1131     break;
1132   case AArch64::STLXRX:
1133   case AArch64::STXRX:
1134     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1135   // FALLTHROUGH
1136   case AArch64::LDARX:
1137   case AArch64::LDAXRX:
1138   case AArch64::LDXRX:
1139   case AArch64::STLRX:
1140     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1141     break;
1142   case AArch64::STLXPW:
1143   case AArch64::STXPW:
1144     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1145   // FALLTHROUGH
1146   case AArch64::LDAXPW:
1147   case AArch64::LDXPW:
1148     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1149     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1150     break;
1151   case AArch64::STLXPX:
1152   case AArch64::STXPX:
1153     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1154   // FALLTHROUGH
1155   case AArch64::LDAXPX:
1156   case AArch64::LDXPX:
1157     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1158     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1159     break;
1160   }
1161
1162   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1163
1164   // You shouldn't load to the same register twice in an instruction...
1165   if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1166        Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1167       Rt == Rt2)
1168     return SoftFail;
1169
1170   return Success;
1171 }
1172
1173 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1174                                               uint64_t Addr,
1175                                               const void *Decoder) {
1176   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1177   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1178   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1179   int64_t offset = fieldFromInstruction(insn, 15, 7);
1180   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1181
1182   // offset is a 7-bit signed immediate, so sign extend it to
1183   // fill the unsigned.
1184   if (offset & (1 << (7 - 1)))
1185     offset |= ~((1LL << 7) - 1);
1186
1187   unsigned Opcode = Inst.getOpcode();
1188   bool NeedsDisjointWritebackTransfer = false;
1189
1190   // First operand is always writeback of base register.
1191   switch (Opcode) {
1192   default:
1193     break;
1194   case AArch64::LDPXpost:
1195   case AArch64::STPXpost:
1196   case AArch64::LDPSWpost:
1197   case AArch64::LDPXpre:
1198   case AArch64::STPXpre:
1199   case AArch64::LDPSWpre:
1200   case AArch64::LDPWpost:
1201   case AArch64::STPWpost:
1202   case AArch64::LDPWpre:
1203   case AArch64::STPWpre:
1204   case AArch64::LDPQpost:
1205   case AArch64::STPQpost:
1206   case AArch64::LDPQpre:
1207   case AArch64::STPQpre:
1208   case AArch64::LDPDpost:
1209   case AArch64::STPDpost:
1210   case AArch64::LDPDpre:
1211   case AArch64::STPDpre:
1212   case AArch64::LDPSpost:
1213   case AArch64::STPSpost:
1214   case AArch64::LDPSpre:
1215   case AArch64::STPSpre:
1216     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1217     break;
1218   }
1219
1220   switch (Opcode) {
1221   default:
1222     return Fail;
1223   case AArch64::LDPXpost:
1224   case AArch64::STPXpost:
1225   case AArch64::LDPSWpost:
1226   case AArch64::LDPXpre:
1227   case AArch64::STPXpre:
1228   case AArch64::LDPSWpre:
1229     NeedsDisjointWritebackTransfer = true;
1230     // Fallthrough
1231   case AArch64::LDNPXi:
1232   case AArch64::STNPXi:
1233   case AArch64::LDPXi:
1234   case AArch64::STPXi:
1235   case AArch64::LDPSWi:
1236     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1237     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1238     break;
1239   case AArch64::LDPWpost:
1240   case AArch64::STPWpost:
1241   case AArch64::LDPWpre:
1242   case AArch64::STPWpre:
1243     NeedsDisjointWritebackTransfer = true;
1244     // Fallthrough
1245   case AArch64::LDNPWi:
1246   case AArch64::STNPWi:
1247   case AArch64::LDPWi:
1248   case AArch64::STPWi:
1249     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1250     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1251     break;
1252   case AArch64::LDNPQi:
1253   case AArch64::STNPQi:
1254   case AArch64::LDPQpost:
1255   case AArch64::STPQpost:
1256   case AArch64::LDPQi:
1257   case AArch64::STPQi:
1258   case AArch64::LDPQpre:
1259   case AArch64::STPQpre:
1260     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1261     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1262     break;
1263   case AArch64::LDNPDi:
1264   case AArch64::STNPDi:
1265   case AArch64::LDPDpost:
1266   case AArch64::STPDpost:
1267   case AArch64::LDPDi:
1268   case AArch64::STPDi:
1269   case AArch64::LDPDpre:
1270   case AArch64::STPDpre:
1271     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1272     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1273     break;
1274   case AArch64::LDNPSi:
1275   case AArch64::STNPSi:
1276   case AArch64::LDPSpost:
1277   case AArch64::STPSpost:
1278   case AArch64::LDPSi:
1279   case AArch64::STPSi:
1280   case AArch64::LDPSpre:
1281   case AArch64::STPSpre:
1282     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1283     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1284     break;
1285   }
1286
1287   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1288   Inst.addOperand(MCOperand::CreateImm(offset));
1289
1290   // You shouldn't load to the same register twice in an instruction...
1291   if (IsLoad && Rt == Rt2)
1292     return SoftFail;
1293
1294   // ... or do any operation that writes-back to a transfer register. But note
1295   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1296   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1297     return SoftFail;
1298
1299   return Success;
1300 }
1301
1302 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1303                                                 uint32_t insn, uint64_t Addr,
1304                                                 const void *Decoder) {
1305   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1306   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1307   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1308   unsigned extend = fieldFromInstruction(insn, 10, 6);
1309
1310   unsigned shift = extend & 0x7;
1311   if (shift > 4)
1312     return Fail;
1313
1314   switch (Inst.getOpcode()) {
1315   default:
1316     return Fail;
1317   case AArch64::ADDWrx:
1318   case AArch64::SUBWrx:
1319     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1320     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1321     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1322     break;
1323   case AArch64::ADDSWrx:
1324   case AArch64::SUBSWrx:
1325     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1326     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1327     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1328     break;
1329   case AArch64::ADDXrx:
1330   case AArch64::SUBXrx:
1331     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1332     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1333     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1334     break;
1335   case AArch64::ADDSXrx:
1336   case AArch64::SUBSXrx:
1337     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1338     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1339     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1340     break;
1341   case AArch64::ADDXrx64:
1342   case AArch64::SUBXrx64:
1343     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1344     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1345     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1346     break;
1347   case AArch64::SUBSXrx64:
1348   case AArch64::ADDSXrx64:
1349     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1350     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1351     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1352     break;
1353   }
1354
1355   Inst.addOperand(MCOperand::CreateImm(extend));
1356   return Success;
1357 }
1358
1359 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1360                                                 uint32_t insn, uint64_t Addr,
1361                                                 const void *Decoder) {
1362   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1363   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1364   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1365   unsigned imm;
1366
1367   if (Datasize) {
1368     if (Inst.getOpcode() == AArch64::ANDSXri)
1369       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1370     else
1371       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1372     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1373     imm = fieldFromInstruction(insn, 10, 13);
1374     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1375       return Fail;
1376   } else {
1377     if (Inst.getOpcode() == AArch64::ANDSWri)
1378       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1379     else
1380       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1381     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1382     imm = fieldFromInstruction(insn, 10, 12);
1383     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1384       return Fail;
1385   }
1386   Inst.addOperand(MCOperand::CreateImm(imm));
1387   return Success;
1388 }
1389
1390 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1391                                             uint64_t Addr,
1392                                             const void *Decoder) {
1393   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1394   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1395   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1396   imm |= fieldFromInstruction(insn, 5, 5);
1397
1398   if (Inst.getOpcode() == AArch64::MOVID)
1399     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1400   else
1401     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1402
1403   Inst.addOperand(MCOperand::CreateImm(imm));
1404
1405   switch (Inst.getOpcode()) {
1406   default:
1407     break;
1408   case AArch64::MOVIv4i16:
1409   case AArch64::MOVIv8i16:
1410   case AArch64::MVNIv4i16:
1411   case AArch64::MVNIv8i16:
1412   case AArch64::MOVIv2i32:
1413   case AArch64::MOVIv4i32:
1414   case AArch64::MVNIv2i32:
1415   case AArch64::MVNIv4i32:
1416     Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1417     break;
1418   case AArch64::MOVIv2s_msl:
1419   case AArch64::MOVIv4s_msl:
1420   case AArch64::MVNIv2s_msl:
1421   case AArch64::MVNIv4s_msl:
1422     Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1423     break;
1424   }
1425
1426   return Success;
1427 }
1428
1429 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1430                                                 uint32_t insn, uint64_t Addr,
1431                                                 const void *Decoder) {
1432   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1433   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1434   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1435   imm |= fieldFromInstruction(insn, 5, 5);
1436
1437   // Tied operands added twice.
1438   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1439   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1440
1441   Inst.addOperand(MCOperand::CreateImm(imm));
1442   Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1443
1444   return Success;
1445 }
1446
1447 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1448                                          uint64_t Addr, const void *Decoder) {
1449   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1450   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1451   imm |= fieldFromInstruction(insn, 29, 2);
1452   const AArch64Disassembler *Dis =
1453       static_cast<const AArch64Disassembler *>(Decoder);
1454
1455   // Sign-extend the 21-bit immediate.
1456   if (imm & (1 << (21 - 1)))
1457     imm |= ~((1LL << 21) - 1);
1458
1459   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1460   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1461     Inst.addOperand(MCOperand::CreateImm(imm));
1462
1463   return Success;
1464 }
1465
1466 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1467                                         uint64_t Addr, const void *Decoder) {
1468   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1469   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1470   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1471   unsigned S = fieldFromInstruction(insn, 29, 1);
1472   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1473
1474   unsigned ShifterVal = (Imm >> 12) & 3;
1475   unsigned ImmVal = Imm & 0xFFF;
1476   const AArch64Disassembler *Dis =
1477       static_cast<const AArch64Disassembler *>(Decoder);
1478
1479   if (ShifterVal != 0 && ShifterVal != 1)
1480     return Fail;
1481
1482   if (Datasize) {
1483     if (Rd == 31 && !S)
1484       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1485     else
1486       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1487     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1488   } else {
1489     if (Rd == 31 && !S)
1490       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1491     else
1492       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1493     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1494   }
1495
1496   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1497     Inst.addOperand(MCOperand::CreateImm(ImmVal));
1498   Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1499   return Success;
1500 }
1501
1502 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1503                                               uint64_t Addr,
1504                                               const void *Decoder) {
1505   int64_t imm = fieldFromInstruction(insn, 0, 26);
1506   const AArch64Disassembler *Dis =
1507       static_cast<const AArch64Disassembler *>(Decoder);
1508
1509   // Sign-extend the 26-bit immediate.
1510   if (imm & (1 << (26 - 1)))
1511     imm |= ~((1LL << 26) - 1);
1512
1513   if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
1514     Inst.addOperand(MCOperand::CreateImm(imm));
1515
1516   return Success;
1517 }
1518
1519 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1520                                                   uint32_t insn, uint64_t Addr,
1521                                                   const void *Decoder) {
1522   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1523   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1524   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1525
1526   uint64_t pstate_field = (op1 << 3) | op2;
1527
1528   Inst.addOperand(MCOperand::CreateImm(pstate_field));
1529   Inst.addOperand(MCOperand::CreateImm(crm));
1530
1531   bool ValidNamed;
1532   (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed);
1533
1534   return ValidNamed ? Success : Fail;
1535 }
1536
1537 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1538                                         uint64_t Addr, const void *Decoder) {
1539   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1540   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1541   bit |= fieldFromInstruction(insn, 19, 5);
1542   int64_t dst = fieldFromInstruction(insn, 5, 14);
1543   const AArch64Disassembler *Dis =
1544       static_cast<const AArch64Disassembler *>(Decoder);
1545
1546   // Sign-extend 14-bit immediate.
1547   if (dst & (1 << (14 - 1)))
1548     dst |= ~((1LL << 14) - 1);
1549
1550   if (fieldFromInstruction(insn, 31, 1) == 0)
1551     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1552   else
1553     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1554   Inst.addOperand(MCOperand::CreateImm(bit));
1555   if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
1556     Inst.addOperand(MCOperand::CreateImm(dst));
1557
1558   return Success;
1559 }