1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUInstrInfo.h"
21 #include "AMDGPUISelLowering.h"
22 #include "AMDGPUSubtarget.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
66 short TexVTXClauseSize;
73 bool FlatAddressSpace;
75 bool EnableIRStructurizer;
76 bool EnablePromoteAlloca;
78 bool EnableLoadStoreOpt;
79 bool EnableUnsafeDSOffsetFolding;
81 unsigned WavefrontSize;
84 bool EnableVGPRSpilling;
93 bool EnableHugeScratchBuffer;
94 bool EnableSIScheduler;
96 std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
97 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
98 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
99 InstrItineraryData InstrItins;
103 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
105 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
106 StringRef GPU, StringRef FS);
108 const AMDGPUFrameLowering *getFrameLowering() const override {
109 return FrameLowering.get();
111 const AMDGPUInstrInfo *getInstrInfo() const override {
112 return InstrInfo.get();
114 const AMDGPURegisterInfo *getRegisterInfo() const override {
115 return &InstrInfo->getRegisterInfo();
117 AMDGPUTargetLowering *getTargetLowering() const override {
120 const InstrItineraryData *getInstrItineraryData() const override {
124 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
126 bool is64bit() const {
130 bool hasVertexCache() const {
131 return HasVertexCache;
134 short getTexVTXClauseSize() const {
135 return TexVTXClauseSize;
138 Generation getGeneration() const {
142 bool hasHWFP64() const {
146 bool hasCaymanISA() const {
150 bool hasFP32Denormals() const {
151 return FP32Denormals;
154 bool hasFP64Denormals() const {
155 return FP64Denormals;
158 bool hasFastFMAF32() const {
162 bool hasFlatAddressSpace() const {
163 return FlatAddressSpace;
166 bool useFlatForGlobal() const {
167 return FlatForGlobal;
170 bool hasBFE() const {
171 return (getGeneration() >= EVERGREEN);
174 bool hasBFI() const {
175 return (getGeneration() >= EVERGREEN);
178 bool hasBFM() const {
182 bool hasBCNT(unsigned Size) const {
184 return (getGeneration() >= EVERGREEN);
187 return (getGeneration() >= SOUTHERN_ISLANDS);
192 bool hasMulU24() const {
193 return (getGeneration() >= EVERGREEN);
196 bool hasMulI24() const {
197 return (getGeneration() >= SOUTHERN_ISLANDS ||
201 bool hasFFBL() const {
202 return (getGeneration() >= EVERGREEN);
205 bool hasFFBH() const {
206 return (getGeneration() >= EVERGREEN);
209 bool hasCARRY() const {
210 return (getGeneration() >= EVERGREEN);
213 bool hasBORROW() const {
214 return (getGeneration() >= EVERGREEN);
217 bool IsIRStructurizerEnabled() const {
218 return EnableIRStructurizer;
221 bool isPromoteAllocaEnabled() const {
222 return EnablePromoteAlloca;
225 bool isIfCvtEnabled() const {
229 bool loadStoreOptEnabled() const {
230 return EnableLoadStoreOpt;
233 bool unsafeDSOffsetFoldingEnabled() const {
234 return EnableUnsafeDSOffsetFolding;
237 unsigned getWavefrontSize() const {
238 return WavefrontSize;
241 unsigned getStackEntrySize() const;
243 bool hasCFAluBug() const {
244 assert(getGeneration() <= NORTHERN_ISLANDS);
248 int getLocalMemorySize() const {
249 return LocalMemorySize;
252 bool hasSGPRInitBug() const {
256 int getLDSBankCount() const {
260 unsigned getAmdKernelCodeChipID() const;
262 AMDGPU::IsaVersion getIsaVersion() const;
264 bool enableMachineScheduler() const override {
268 void overrideSchedPolicy(MachineSchedPolicy &Policy,
269 MachineInstr *begin, MachineInstr *end,
270 unsigned NumRegionInstrs) const override;
272 // Helper functions to simplify if statements
273 bool isTargetELF() const {
277 StringRef getDeviceName() const {
281 bool enableHugeScratchBuffer() const {
282 return EnableHugeScratchBuffer;
285 bool enableSIScheduler() const {
286 return EnableSIScheduler;
289 bool dumpCode() const {
292 bool r600ALUEncoding() const {
295 bool isAmdHsaOS() const {
296 return TargetTriple.getOS() == Triple::AMDHSA;
298 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
300 bool isXNACKEnabled() const {
304 unsigned getMaxWavesPerCU() const {
305 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
308 // FIXME: Not sure what this is for other subtagets.
309 llvm_unreachable("do not know max waves per CU for this subtarget.");
312 bool enableSubRegLiveness() const override {
316 /// \brief Returns the offset in bytes from the start of the input buffer
317 /// of the first explicit kernel argument.
318 unsigned getExplicitKernelArgOffset() const {
319 return isAmdHsaOS() ? 0 : 36;
322 unsigned getMaxNumUserSGPRs() const {
327 } // End namespace llvm