1 //===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are available only on Cayman
13 //===----------------------------------------------------------------------===//
15 def isCayman : Predicate<"Subtarget->hasCaymanISA()">;
17 //===----------------------------------------------------------------------===//
18 // Cayman Instructions
19 //===----------------------------------------------------------------------===//
21 let Predicates = [isCayman] in {
23 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
26 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
30 def : IMad24Pat<MULADD_INT24_cm>;
34 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
36 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
37 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
38 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
39 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
40 def MULHI_INT_cm24 : MULHI_INT24_Common<0x5c>;
41 def MULHI_UINT_cm24 : MULHI_UINT24_Common<0xb2>;
43 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
44 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
45 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
46 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
47 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
48 def SIN_cm : SIN_Common<0x8D>;
49 def COS_cm : COS_Common<0x8E>;
52 def : RsqPat<RECIPSQRT_IEEE_cm, f32>;
54 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
56 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
58 // RECIP_UINT emulation for Cayman
59 // The multiplication scales from [0,1] to the unsigned integer range
61 (AMDGPUurecip i32:$src0),
62 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
63 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
66 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
73 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
75 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
76 CF_MEM_RAT_CACHELESS <0x14, 0, mask,
77 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
78 "STORE_DWORD $rw_gpr, $index_gpr",
79 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
80 let eop = 0; // This bit is not used on Cayman.
83 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
84 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
85 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
87 def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> {
88 let eop = 0; // This bit is not used on Cayman.
91 class VTX_READ_cm <string name, dag outs>
92 : VTX_WORD0_cm, VTX_READ<name, outs, []> {
97 let FETCH_WHOLE_QUAD = 0;
99 // XXX: We can infer this field based on the SRC_GPR. This would allow us
100 // to store vertex addresses in any channel, not just X.
103 let STRUCTURED_READ = 0;
105 let COALESCED_READ = 0;
107 let Inst{31-0} = Word0;
111 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr",
112 (outs R600_TReg32_X:$dst_gpr)> {
115 let DST_SEL_Y = 7; // Masked
116 let DST_SEL_Z = 7; // Masked
117 let DST_SEL_W = 7; // Masked
118 let DATA_FORMAT = 1; // FMT_8
122 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr",
123 (outs R600_TReg32_X:$dst_gpr)> {
125 let DST_SEL_Y = 7; // Masked
126 let DST_SEL_Z = 7; // Masked
127 let DST_SEL_W = 7; // Masked
128 let DATA_FORMAT = 5; // FMT_16
133 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr",
134 (outs R600_TReg32_X:$dst_gpr)> {
137 let DST_SEL_Y = 7; // Masked
138 let DST_SEL_Z = 7; // Masked
139 let DST_SEL_W = 7; // Masked
140 let DATA_FORMAT = 0xD; // COLOR_32
142 // This is not really necessary, but there were some GPU hangs that appeared
143 // to be caused by ALU instructions in the next instruction group that wrote
144 // to the $src_gpr registers of the VTX_READ.
146 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
147 // %T2_X<def> = MOV %ZERO
148 //Adding this constraint prevents this from happening.
149 let Constraints = "$src_gpr.ptr = $dst_gpr";
153 : VTX_READ_cm <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
154 (outs R600_Reg64:$dst_gpr)> {
160 let DATA_FORMAT = 0x1D; // COLOR_32_32
164 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
165 (outs R600_Reg128:$dst_gpr)> {
171 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
173 // XXX: Need to force VTX_READ_128 instructions to write to the same register
174 // that holds its buffer address to avoid potential hangs. We can't use
175 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
176 // registers are different sizes.
179 //===----------------------------------------------------------------------===//
180 // VTX Read from parameter memory space
181 //===----------------------------------------------------------------------===//
182 def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
183 (VTX_READ_8_cm MEMxi:$src_gpr, 3)>;
184 def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
185 (VTX_READ_16_cm MEMxi:$src_gpr, 3)>;
186 def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
187 (VTX_READ_32_cm MEMxi:$src_gpr, 3)>;
188 def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
189 (VTX_READ_64_cm MEMxi:$src_gpr, 3)>;
190 def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
191 (VTX_READ_128_cm MEMxi:$src_gpr, 3)>;
193 //===----------------------------------------------------------------------===//
194 // VTX Read from constant memory space
195 //===----------------------------------------------------------------------===//
196 def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
197 (VTX_READ_8_cm MEMxi:$src_gpr, 2)>;
198 def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
199 (VTX_READ_16_cm MEMxi:$src_gpr, 2)>;
200 def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
201 (VTX_READ_32_cm MEMxi:$src_gpr, 2)>;
202 def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
203 (VTX_READ_64_cm MEMxi:$src_gpr, 2)>;
204 def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
205 (VTX_READ_128_cm MEMxi:$src_gpr, 2)>;
207 //===----------------------------------------------------------------------===//
208 // VTX Read from global memory space
209 //===----------------------------------------------------------------------===//
210 def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
211 (VTX_READ_8_cm MEMxi:$src_gpr, 1)>;
212 def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
213 (VTX_READ_16_cm MEMxi:$src_gpr, 1)>;
214 def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
215 (VTX_READ_32_cm MEMxi:$src_gpr, 1)>;
216 def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
217 (VTX_READ_64_cm MEMxi:$src_gpr, 1)>;
218 def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
219 (VTX_READ_128_cm MEMxi:$src_gpr, 1)>;