1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUELFStreamer.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "InstPrinter/AMDGPUInstPrinter.h"
20 #include "SIDefines.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MachineLocation.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define GET_INSTRINFO_MC_DESC
33 #include "AMDGPUGenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "AMDGPUGenSubtargetInfo.inc"
38 #define GET_REGINFO_MC_DESC
39 #include "AMDGPUGenRegisterInfo.inc"
41 static MCInstrInfo *createAMDGPUMCInstrInfo() {
42 MCInstrInfo *X = new MCInstrInfo();
43 InitAMDGPUMCInstrInfo(X);
47 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
48 MCRegisterInfo *X = new MCRegisterInfo();
49 InitAMDGPUMCRegisterInfo(X, 0);
53 static MCSubtargetInfo *
54 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
58 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
59 unsigned SyntaxVariant,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI) {
63 return new AMDGPUInstPrinter(MAI, MII, MRI);
66 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
67 formatted_raw_ostream &OS,
68 MCInstPrinter *InstPrint,
70 return new AMDGPUTargetAsmStreamer(S, OS);
73 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
75 const MCSubtargetInfo &STI) {
76 return new AMDGPUTargetELFStreamer(S);
79 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
80 MCAsmBackend &MAB, raw_pwrite_stream &OS,
81 MCCodeEmitter *Emitter, bool RelaxAll) {
82 if (T.getOS() == Triple::AMDHSA)
83 return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
85 return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
88 extern "C" void LLVMInitializeAMDGPUTargetMC() {
89 for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
90 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
92 TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
93 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
94 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
95 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
96 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
97 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
100 // R600 specific registration
101 TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
102 createR600MCCodeEmitter);
104 // GCN specific registration
105 TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
106 createSIMCCodeEmitter);
108 TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
109 createAMDGPUAsmTargetStreamer);
110 TargetRegistry::RegisterObjectTargetStreamer(
111 getTheGCNTarget(), createAMDGPUObjectTargetStreamer);