1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/ISDOpcodes.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineValueType.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/TargetLowering.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/IRBuilder.h"
32 #include "llvm/IR/InlineAsm.h"
33 #include "llvm/Support/CodeGen.h"
41 class FunctionLoweringInfo;
43 class InstrItineraryData;
45 class MachineBasicBlock;
48 class TargetLibraryInfo;
50 class TargetRegisterInfo;
55 // ARM Specific DAG Nodes
56 enum NodeType : unsigned {
57 // Start the numbering where the builtin ops and target ops leave off.
58 FIRST_NUMBER = ISD::BUILTIN_OP_END,
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61 // TargetExternalSymbol, and TargetGlobalAddress.
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
66 // Add pseudo op to model memcpy for struct byval.
69 CALL, // Function call.
70 CALL_PRED, // Function call that's predicable.
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 BRCOND, // Conditional branch.
73 BR_JT, // Jumptable branch.
74 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75 RET_FLAG, // Return with a flag operand.
76 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
78 PIC_ADD, // Add with a PC operand and a PIC label.
80 CMP, // ARM compare instructions.
81 CMN, // ARM CMN instructions.
82 CMPZ, // ARM compare that sets only Z flag.
83 CMPFP, // ARM VFP compare instruction, sets FPSCR.
84 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85 FMSTAT, // ARM fmstat instruction.
87 CMOV, // ARM conditional move instructions.
89 SSAT, // Signed saturation
90 USAT, // Unsigned saturation
94 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
95 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
96 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
98 ADDC, // Add with carry
99 ADDE, // Add using carry
100 SUBC, // Sub with carry
101 SUBE, // Sub using carry
103 VMOVRRD, // double to two gprs.
104 VMOVDRR, // Two gprs to double.
106 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
107 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
108 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
110 TC_RETURN, // Tail call return pseudo.
114 DYN_ALLOC, // Dynamic allocation on the stack.
116 MEMBARRIER_MCR, // Memory barrier (MCR)
120 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
121 WIN__DBZCHK, // Windows' divide by zero check
123 VCEQ, // Vector compare equal.
124 VCEQZ, // Vector compare equal to zero.
125 VCGE, // Vector compare greater than or equal.
126 VCGEZ, // Vector compare greater than or equal to zero.
127 VCLEZ, // Vector compare less than or equal to zero.
128 VCGEU, // Vector compare unsigned greater than or equal.
129 VCGT, // Vector compare greater than.
130 VCGTZ, // Vector compare greater than zero.
131 VCLTZ, // Vector compare less than zero.
132 VCGTU, // Vector compare unsigned greater than.
133 VTST, // Vector test bits.
135 // Vector shift by immediate:
137 VSHRs, // ...right (signed)
138 VSHRu, // ...right (unsigned)
140 // Vector rounding shift by immediate:
141 VRSHRs, // ...right (signed)
142 VRSHRu, // ...right (unsigned)
143 VRSHRN, // ...right narrow
145 // Vector saturating shift by immediate:
146 VQSHLs, // ...left (signed)
147 VQSHLu, // ...left (unsigned)
148 VQSHLsu, // ...left (signed to unsigned)
149 VQSHRNs, // ...right narrow (signed)
150 VQSHRNu, // ...right narrow (unsigned)
151 VQSHRNsu, // ...right narrow (signed to unsigned)
153 // Vector saturating rounding shift by immediate:
154 VQRSHRNs, // ...right narrow (signed)
155 VQRSHRNu, // ...right narrow (unsigned)
156 VQRSHRNsu, // ...right narrow (signed to unsigned)
158 // Vector shift and insert:
162 // Vector get lane (VMOV scalar to ARM core register)
163 // (These are used for 8- and 16-bit element types only.)
164 VGETLANEu, // zero-extend vector extract element
165 VGETLANEs, // sign-extend vector extract element
167 // Vector move immediate and move negated immediate:
171 // Vector move f32 immediate:
180 VREV64, // reverse elements within 64-bit doublewords
181 VREV32, // reverse elements within 32-bit words
182 VREV16, // reverse elements within 16-bit halfwords
183 VZIP, // zip (interleave)
184 VUZP, // unzip (deinterleave)
186 VTBL1, // 1-register shuffle with mask
187 VTBL2, // 2-register shuffle with mask
189 // Vector multiply long:
191 VMULLu, // ...unsigned
193 SMULWB, // Signed multiply word by half word, bottom
194 SMULWT, // Signed multiply word by half word, top
195 UMLAL, // 64bit Unsigned Accumulate Multiply
196 SMLAL, // 64bit Signed Accumulate Multiply
197 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
198 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
199 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
200 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
201 SMLALTT, // 64-bit signed accumulate multiply top, top 16
202 SMLALD, // Signed multiply accumulate long dual
203 SMLALDX, // Signed multiply accumulate long dual exchange
204 SMLSLD, // Signed multiply subtract long dual
205 SMLSLDX, // Signed multiply subtract long dual exchange
207 // Operands of the standard BUILD_VECTOR node are not legalized, which
208 // is fine if BUILD_VECTORs are always lowered to shuffles or other
209 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
210 // operands need to be legalized. Define an ARM-specific version of
211 // BUILD_VECTOR for this purpose.
217 // Vector OR with immediate
219 // Vector AND with NOT of immediate
222 // Vector bitwise select
225 // Pseudo-instruction representing a memory copy using ldm/stm
229 // Vector load N-element structure to all lanes:
230 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
235 // NEON loads with post-increment base updates:
248 // NEON stores with post-increment base updates:
258 } // end namespace ARMISD
260 /// Define some predicates that are used for node matching.
263 bool isBitFieldInvertedMask(unsigned v);
265 } // end namespace ARM
267 //===--------------------------------------------------------------------===//
268 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
270 class ARMTargetLowering : public TargetLowering {
272 explicit ARMTargetLowering(const TargetMachine &TM,
273 const ARMSubtarget &STI);
275 unsigned getJumpTableEncoding() const override;
276 bool useSoftFloat() const override;
278 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
280 /// ReplaceNodeResults - Replace the results of node with an illegal result
281 /// type with new values built out of custom code.
282 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
283 SelectionDAG &DAG) const override;
285 const char *getTargetNodeName(unsigned Opcode) const override;
287 bool isSelectSupported(SelectSupportKind Kind) const override {
288 // ARM does not support scalar condition selects on vectors.
289 return (Kind != ScalarCondVectorVal);
292 bool isReadOnly(const GlobalValue *GV) const;
294 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
295 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
296 EVT VT) const override;
299 EmitInstrWithCustomInserter(MachineInstr &MI,
300 MachineBasicBlock *MBB) const override;
302 void AdjustInstrPostInstrSelection(MachineInstr &MI,
303 SDNode *Node) const override;
305 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
306 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
307 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
308 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
310 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
312 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
313 /// unaligned memory accesses of the specified type. Returns whether it
314 /// is "fast" by reference in the second argument.
315 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
317 bool *Fast) const override;
319 EVT getOptimalMemOpType(uint64_t Size,
320 unsigned DstAlign, unsigned SrcAlign,
321 bool IsMemset, bool ZeroMemset,
323 MachineFunction &MF) const override;
325 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
326 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
327 bool isZExtFree(SDValue Val, EVT VT2) const override;
329 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
331 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
334 /// isLegalAddressingMode - Return true if the addressing mode represented
335 /// by AM is legal for this target, for a load/store of the specified type.
336 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
337 Type *Ty, unsigned AS,
338 Instruction *I = nullptr) const override;
340 /// getScalingFactorCost - Return the cost of the scaling used in
341 /// addressing mode represented by AM.
342 /// If the AM is supported, the return value must be >= 0.
343 /// If the AM is not supported, the return value must be negative.
344 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
345 unsigned AS) const override;
347 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
349 /// \brief Returns true if the addresing mode representing by AM is legal
350 /// for the Thumb1 target, for a load/store of the specified type.
351 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
353 /// isLegalICmpImmediate - Return true if the specified immediate is legal
354 /// icmp immediate, that is the target has icmp instructions which can
355 /// compare a register against the immediate without having to materialize
356 /// the immediate into a register.
357 bool isLegalICmpImmediate(int64_t Imm) const override;
359 /// isLegalAddImmediate - Return true if the specified immediate is legal
360 /// add immediate, that is the target has add instructions which can
361 /// add a register and the immediate without having to materialize
362 /// the immediate into a register.
363 bool isLegalAddImmediate(int64_t Imm) const override;
365 /// getPreIndexedAddressParts - returns true by value, base pointer and
366 /// offset pointer and addressing mode by reference if the node's address
367 /// can be legally represented as pre-indexed load / store address.
368 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
369 ISD::MemIndexedMode &AM,
370 SelectionDAG &DAG) const override;
372 /// getPostIndexedAddressParts - returns true by value, base pointer and
373 /// offset pointer and addressing mode by reference if this node can be
374 /// combined with a load / store to form a post-indexed load / store.
375 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
376 SDValue &Offset, ISD::MemIndexedMode &AM,
377 SelectionDAG &DAG) const override;
379 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
380 const APInt &DemandedElts,
381 const SelectionDAG &DAG,
382 unsigned Depth) const override;
385 bool ExpandInlineAsm(CallInst *CI) const override;
387 ConstraintType getConstraintType(StringRef Constraint) const override;
389 /// Examine constraint string and operand type and determine a weight value.
390 /// The operand object must already have been set up with the operand type.
391 ConstraintWeight getSingleConstraintMatchWeight(
392 AsmOperandInfo &info, const char *constraint) const override;
394 std::pair<unsigned, const TargetRegisterClass *>
395 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
396 StringRef Constraint, MVT VT) const override;
398 const char *LowerXConstraint(EVT ConstraintVT) const override;
400 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
401 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
402 /// true it means one of the asm constraint of the inline asm instruction
403 /// being processed is 'm'.
404 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
405 std::vector<SDValue> &Ops,
406 SelectionDAG &DAG) const override;
409 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
410 if (ConstraintCode == "Q")
411 return InlineAsm::Constraint_Q;
412 else if (ConstraintCode == "o")
413 return InlineAsm::Constraint_o;
414 else if (ConstraintCode.size() == 2) {
415 if (ConstraintCode[0] == 'U') {
416 switch(ConstraintCode[1]) {
420 return InlineAsm::Constraint_Um;
422 return InlineAsm::Constraint_Un;
424 return InlineAsm::Constraint_Uq;
426 return InlineAsm::Constraint_Us;
428 return InlineAsm::Constraint_Ut;
430 return InlineAsm::Constraint_Uv;
432 return InlineAsm::Constraint_Uy;
436 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
439 const ARMSubtarget* getSubtarget() const {
443 /// getRegClassFor - Return the register class that should be used for the
444 /// specified value type.
445 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
447 /// Returns true if a cast between SrcAS and DestAS is a noop.
448 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
449 // Addrspacecasts are always noops.
453 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
454 unsigned &PrefAlign) const override;
456 /// createFastISel - This method returns a target specific FastISel object,
457 /// or null if the target does not support "fast" ISel.
458 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
459 const TargetLibraryInfo *libInfo) const override;
461 Sched::Preference getSchedulingPreference(SDNode *N) const override;
464 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
465 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
467 /// isFPImmLegal - Returns true if the target can instruction select the
468 /// specified FP immediate natively. If false, the legalizer will
469 /// materialize the FP immediate as a load from a constant pool.
470 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
472 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
475 unsigned Intrinsic) const override;
477 /// \brief Returns true if it is beneficial to convert a load of a constant
478 /// to just the constant itself.
479 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
480 Type *Ty) const override;
482 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
484 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
485 unsigned Index) const override;
487 /// \brief Returns true if an argument of type Ty needs to be passed in a
488 /// contiguous block of registers in calling convention CallConv.
489 bool functionArgumentNeedsConsecutiveRegisters(
490 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
492 /// If a physical register, this returns the register that receives the
493 /// exception address on entry to an EH pad.
495 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
497 /// If a physical register, this returns the register that receives the
498 /// exception typeid on entry to a landing pad.
500 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
502 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
503 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
504 AtomicOrdering Ord) const override;
505 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
506 Value *Addr, AtomicOrdering Ord) const override;
508 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
510 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
511 AtomicOrdering Ord) const override;
512 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
513 AtomicOrdering Ord) const override;
515 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
517 bool lowerInterleavedLoad(LoadInst *LI,
518 ArrayRef<ShuffleVectorInst *> Shuffles,
519 ArrayRef<unsigned> Indices,
520 unsigned Factor) const override;
521 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
522 unsigned Factor) const override;
524 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
525 TargetLoweringBase::AtomicExpansionKind
526 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
527 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
528 TargetLoweringBase::AtomicExpansionKind
529 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
530 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
532 bool useLoadStackGuardNode() const override;
534 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
535 unsigned &Cost) const override;
537 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
538 const SelectionDAG &DAG) const override {
539 // Do not merge to larger than i32.
540 return (MemVT.getSizeInBits() <= 32);
543 bool isCheapToSpeculateCttz() const override;
544 bool isCheapToSpeculateCtlz() const override;
546 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
547 return VT.isScalarInteger();
550 bool supportSwiftError() const override {
554 bool hasStandaloneRem(EVT VT) const override {
555 return HasStandaloneRem;
558 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
559 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
561 /// Returns true if \p VecTy is a legal interleaved access type. This
562 /// function checks the vector element type and the overall width of the
564 bool isLegalInterleavedAccessType(VectorType *VecTy,
565 const DataLayout &DL) const;
567 /// Returns the number of interleaved accesses that will be generated when
568 /// lowering accesses of the given type.
569 unsigned getNumInterleavedAccesses(VectorType *VecTy,
570 const DataLayout &DL) const;
572 void finalizeLowering(MachineFunction &MF) const override;
575 std::pair<const TargetRegisterClass *, uint8_t>
576 findRepresentativeClass(const TargetRegisterInfo *TRI,
577 MVT VT) const override;
580 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
581 /// make the right decision when generating code for different targets.
582 const ARMSubtarget *Subtarget;
584 const TargetRegisterInfo *RegInfo;
586 const InstrItineraryData *Itins;
588 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
589 unsigned ARMPCLabelIndex;
591 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
593 bool InsertFencesForAtomic;
595 bool HasStandaloneRem = true;
597 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
598 void addDRTypeForNEON(MVT VT);
599 void addQRTypeForNEON(MVT VT);
600 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
602 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
604 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
605 SDValue &Arg, RegsToPassVector &RegsToPass,
606 CCValAssign &VA, CCValAssign &NextVA,
608 SmallVectorImpl<SDValue> &MemOpChains,
609 ISD::ArgFlagsTy Flags) const;
610 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
611 SDValue &Root, SelectionDAG &DAG,
612 const SDLoc &dl) const;
614 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
615 bool isVarArg) const;
616 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
617 bool isVarArg) const;
618 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
619 const SDLoc &dl, SelectionDAG &DAG,
620 const CCValAssign &VA,
621 ISD::ArgFlagsTy Flags) const;
622 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
623 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
624 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
625 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
626 const ARMSubtarget *Subtarget) const;
627 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
628 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
629 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
630 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
631 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
632 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
633 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
634 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
635 SelectionDAG &DAG) const;
636 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
638 TLSModel::Model model) const;
639 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
640 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
641 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
642 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
643 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
644 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
645 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
646 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
647 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
648 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
649 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
650 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
652 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
653 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
654 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
655 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
656 const ARMSubtarget *ST) const;
657 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
658 const ARMSubtarget *ST) const;
659 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
660 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
661 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
662 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
663 SmallVectorImpl<SDValue> &Results) const;
664 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
665 SDValue &Chain) const;
666 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
667 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
668 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
669 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
670 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
671 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
673 unsigned getRegisterByName(const char* RegName, EVT VT,
674 SelectionDAG &DAG) const override;
676 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
677 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
678 /// expanded to FMAs when this method returns true, otherwise fmuladd is
679 /// expanded to fmul + fadd.
681 /// ARM supports both fused and unfused multiply-add operations; we already
682 /// lower a pair of fmul and fadd to the latter so it's not clear that there
683 /// would be a gain or that the gain would be worthwhile enough to risk
684 /// correctness bugs.
685 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
687 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
689 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
690 CallingConv::ID CallConv, bool isVarArg,
691 const SmallVectorImpl<ISD::InputArg> &Ins,
692 const SDLoc &dl, SelectionDAG &DAG,
693 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
694 SDValue ThisVal) const;
696 bool supportSplitCSR(MachineFunction *MF) const override {
697 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
698 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
701 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
702 void insertCopiesSplitCSR(
703 MachineBasicBlock *Entry,
704 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
707 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
708 const SmallVectorImpl<ISD::InputArg> &Ins,
709 const SDLoc &dl, SelectionDAG &DAG,
710 SmallVectorImpl<SDValue> &InVals) const override;
712 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
713 SDValue &Chain, const Value *OrigArg,
714 unsigned InRegsParamRecordIdx, int ArgOffset,
715 unsigned ArgSize) const;
717 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
718 const SDLoc &dl, SDValue &Chain,
719 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
720 bool ForceMutable = false) const;
722 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
723 SmallVectorImpl<SDValue> &InVals) const override;
725 /// HandleByVal - Target-specific cleanup for ByVal support.
726 void HandleByVal(CCState *, unsigned &, unsigned) const override;
728 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
729 /// for tail call optimization. Targets which want to do tail call
730 /// optimization should implement this function.
731 bool IsEligibleForTailCallOptimization(SDValue Callee,
732 CallingConv::ID CalleeCC,
734 bool isCalleeStructRet,
735 bool isCallerStructRet,
736 const SmallVectorImpl<ISD::OutputArg> &Outs,
737 const SmallVectorImpl<SDValue> &OutVals,
738 const SmallVectorImpl<ISD::InputArg> &Ins,
739 SelectionDAG& DAG) const;
741 bool CanLowerReturn(CallingConv::ID CallConv,
742 MachineFunction &MF, bool isVarArg,
743 const SmallVectorImpl<ISD::OutputArg> &Outs,
744 LLVMContext &Context) const override;
746 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
747 const SmallVectorImpl<ISD::OutputArg> &Outs,
748 const SmallVectorImpl<SDValue> &OutVals,
749 const SDLoc &dl, SelectionDAG &DAG) const override;
751 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
753 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
755 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
756 SDValue ARMcc, SDValue CCR, SDValue Cmp,
757 SelectionDAG &DAG) const;
758 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
759 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
760 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
761 const SDLoc &dl, bool InvalidOnQNaN) const;
762 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
764 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
766 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
767 MachineBasicBlock *DispatchBB, int FI) const;
769 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
771 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
773 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
774 MachineBasicBlock *MBB) const;
776 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
777 MachineBasicBlock *MBB) const;
778 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
779 MachineBasicBlock *MBB) const;
782 enum NEONModImmType {
790 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
791 const TargetLibraryInfo *libInfo);
793 } // end namespace ARM
795 } // end namespace llvm
797 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H