1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
52 PIC_ADD, // Add with a PC operand and a PIC label.
54 CMP, // ARM compare instructions.
55 CMPZ, // ARM compare that sets only Z flag.
56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
59 CMOV, // ARM conditional move instructions.
60 CNEG, // ARM conditional negate instructions.
64 RBIT, // ARM bitreverse instruction
66 FTOSI, // FP to sint within a FP register.
67 FTOUI, // FP to uint within a FP register.
68 SITOF, // sint to FP within a FP register.
69 UITOF, // uint to FP within a FP register.
71 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
72 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
73 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
75 VMOVRRD, // double to two gprs.
76 VMOVDRR, // Two gprs to double.
78 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
79 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
80 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
82 TC_RETURN, // Tail call return pseudo.
86 DYN_ALLOC, // Dynamic allocation on the stack.
88 MEMBARRIER, // Memory barrier (DMB)
89 MEMBARRIER_MCR, // Memory barrier (MCR)
93 VCEQ, // Vector compare equal.
94 VCEQZ, // Vector compare equal to zero.
95 VCGE, // Vector compare greater than or equal.
96 VCGEZ, // Vector compare greater than or equal to zero.
97 VCLEZ, // Vector compare less than or equal to zero.
98 VCGEU, // Vector compare unsigned greater than or equal.
99 VCGT, // Vector compare greater than.
100 VCGTZ, // Vector compare greater than zero.
101 VCLTZ, // Vector compare less than zero.
102 VCGTU, // Vector compare unsigned greater than.
103 VTST, // Vector test bits.
105 // Vector shift by immediate:
107 VSHRs, // ...right (signed)
108 VSHRu, // ...right (unsigned)
109 VSHLLs, // ...left long (signed)
110 VSHLLu, // ...left long (unsigned)
111 VSHLLi, // ...left long (with maximum shift count)
112 VSHRN, // ...right narrow
114 // Vector rounding shift by immediate:
115 VRSHRs, // ...right (signed)
116 VRSHRu, // ...right (unsigned)
117 VRSHRN, // ...right narrow
119 // Vector saturating shift by immediate:
120 VQSHLs, // ...left (signed)
121 VQSHLu, // ...left (unsigned)
122 VQSHLsu, // ...left (signed to unsigned)
123 VQSHRNs, // ...right narrow (signed)
124 VQSHRNu, // ...right narrow (unsigned)
125 VQSHRNsu, // ...right narrow (signed to unsigned)
127 // Vector saturating rounding shift by immediate:
128 VQRSHRNs, // ...right narrow (signed)
129 VQRSHRNu, // ...right narrow (unsigned)
130 VQRSHRNsu, // ...right narrow (signed to unsigned)
132 // Vector shift and insert:
136 // Vector get lane (VMOV scalar to ARM core register)
137 // (These are used for 8- and 16-bit element types only.)
138 VGETLANEu, // zero-extend vector extract element
139 VGETLANEs, // sign-extend vector extract element
141 // Vector move immediate and move negated immediate:
151 VREV64, // reverse elements within 64-bit doublewords
152 VREV32, // reverse elements within 32-bit words
153 VREV16, // reverse elements within 16-bit halfwords
154 VZIP, // zip (interleave)
155 VUZP, // unzip (deinterleave)
158 // Vector multiply long:
160 VMULLu, // ...unsigned
162 // Operands of the standard BUILD_VECTOR node are not legalized, which
163 // is fine if BUILD_VECTORs are always lowered to shuffles or other
164 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
165 // operands need to be legalized. Define an ARM-specific version of
166 // BUILD_VECTOR for this purpose.
169 // Floating-point max and min:
176 // Vector OR with immediate
178 // Vector AND with NOT of immediate
181 // Vector load N-element structure to all lanes:
182 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
186 // NEON loads with post-increment base updates:
198 // NEON stores with post-increment base updates:
209 /// Define some predicates that are used for node matching.
211 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
212 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
213 /// instruction, returns its 8-bit integer representation. Otherwise,
215 int getVFPf32Imm(const APFloat &FPImm);
216 int getVFPf64Imm(const APFloat &FPImm);
217 bool isBitFieldInvertedMask(unsigned v);
220 //===--------------------------------------------------------------------===//
221 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
223 class ARMTargetLowering : public TargetLowering {
225 explicit ARMTargetLowering(TargetMachine &TM);
227 virtual unsigned getJumpTableEncoding(void) const;
229 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
231 /// ReplaceNodeResults - Replace the results of node with an illegal result
232 /// type with new values built out of custom code.
234 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
235 SelectionDAG &DAG) const;
237 virtual const char *getTargetNodeName(unsigned Opcode) const;
239 virtual MachineBasicBlock *
240 EmitInstrWithCustomInserter(MachineInstr *MI,
241 MachineBasicBlock *MBB) const;
243 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
245 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
247 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
248 /// unaligned memory accesses. of the specified type.
249 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
250 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
252 /// isLegalAddressingMode - Return true if the addressing mode represented
253 /// by AM is legal for this target, for a load/store of the specified type.
254 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
255 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
257 /// isLegalICmpImmediate - Return true if the specified immediate is legal
258 /// icmp immediate, that is the target has icmp instructions which can
259 /// compare a register against the immediate without having to materialize
260 /// the immediate into a register.
261 virtual bool isLegalICmpImmediate(int64_t Imm) const;
263 /// getPreIndexedAddressParts - returns true by value, base pointer and
264 /// offset pointer and addressing mode by reference if the node's address
265 /// can be legally represented as pre-indexed load / store address.
266 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
268 ISD::MemIndexedMode &AM,
269 SelectionDAG &DAG) const;
271 /// getPostIndexedAddressParts - returns true by value, base pointer and
272 /// offset pointer and addressing mode by reference if this node can be
273 /// combined with a load / store to form a post-indexed load / store.
274 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
275 SDValue &Base, SDValue &Offset,
276 ISD::MemIndexedMode &AM,
277 SelectionDAG &DAG) const;
279 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
283 const SelectionDAG &DAG,
284 unsigned Depth) const;
287 virtual bool ExpandInlineAsm(CallInst *CI) const;
289 ConstraintType getConstraintType(const std::string &Constraint) const;
291 /// Examine constraint string and operand type and determine a weight value.
292 /// The operand object must already have been set up with the operand type.
293 ConstraintWeight getSingleConstraintMatchWeight(
294 AsmOperandInfo &info, const char *constraint) const;
296 std::pair<unsigned, const TargetRegisterClass*>
297 getRegForInlineAsmConstraint(const std::string &Constraint,
299 std::vector<unsigned>
300 getRegClassForInlineAsmConstraint(const std::string &Constraint,
303 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
304 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
305 /// true it means one of the asm constraint of the inline asm instruction
306 /// being processed is 'm'.
307 virtual void LowerAsmOperandForConstraint(SDValue Op,
308 char ConstraintLetter,
309 std::vector<SDValue> &Ops,
310 SelectionDAG &DAG) const;
312 const ARMSubtarget* getSubtarget() const {
316 /// getRegClassFor - Return the register class that should be used for the
317 /// specified value type.
318 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
320 /// getFunctionAlignment - Return the Log2 alignment of this function.
321 virtual unsigned getFunctionAlignment(const Function *F) const;
323 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
324 /// be used for loads / stores from the global.
325 virtual unsigned getMaximalGlobalOffset() const;
327 /// createFastISel - This method returns a target specific FastISel object,
328 /// or null if the target does not support "fast" ISel.
329 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
331 Sched::Preference getSchedulingPreference(SDNode *N) const;
333 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
334 MachineFunction &MF) const;
336 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
337 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
339 /// isFPImmLegal - Returns true if the target can instruction select the
340 /// specified FP immediate natively. If false, the legalizer will
341 /// materialize the FP immediate as a load from a constant pool.
342 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
344 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
346 unsigned Intrinsic) const;
348 std::pair<const TargetRegisterClass*, uint8_t>
349 findRepresentativeClass(EVT VT) const;
352 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
353 /// make the right decision when generating code for different targets.
354 const ARMSubtarget *Subtarget;
356 const TargetRegisterInfo *RegInfo;
358 const InstrItineraryData *Itins;
360 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
362 unsigned ARMPCLabelIndex;
364 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
365 void addDRTypeForNEON(EVT VT);
366 void addQRTypeForNEON(EVT VT);
368 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
369 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
370 SDValue Chain, SDValue &Arg,
371 RegsToPassVector &RegsToPass,
372 CCValAssign &VA, CCValAssign &NextVA,
374 SmallVector<SDValue, 8> &MemOpChains,
375 ISD::ArgFlagsTy Flags) const;
376 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
377 SDValue &Root, SelectionDAG &DAG,
380 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
381 bool isVarArg) const;
382 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
383 DebugLoc dl, SelectionDAG &DAG,
384 const CCValAssign &VA,
385 ISD::ArgFlagsTy Flags) const;
386 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
390 const ARMSubtarget *Subtarget) const;
391 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
394 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
395 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
396 SelectionDAG &DAG) const;
397 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
398 SelectionDAG &DAG) const;
399 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
411 const ARMSubtarget *ST) const;
413 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
416 CallingConv::ID CallConv, bool isVarArg,
417 const SmallVectorImpl<ISD::InputArg> &Ins,
418 DebugLoc dl, SelectionDAG &DAG,
419 SmallVectorImpl<SDValue> &InVals) const;
422 LowerFormalArguments(SDValue Chain,
423 CallingConv::ID CallConv, bool isVarArg,
424 const SmallVectorImpl<ISD::InputArg> &Ins,
425 DebugLoc dl, SelectionDAG &DAG,
426 SmallVectorImpl<SDValue> &InVals) const;
429 LowerCall(SDValue Chain, SDValue Callee,
430 CallingConv::ID CallConv, bool isVarArg,
432 const SmallVectorImpl<ISD::OutputArg> &Outs,
433 const SmallVectorImpl<SDValue> &OutVals,
434 const SmallVectorImpl<ISD::InputArg> &Ins,
435 DebugLoc dl, SelectionDAG &DAG,
436 SmallVectorImpl<SDValue> &InVals) const;
438 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
439 /// for tail call optimization. Targets which want to do tail call
440 /// optimization should implement this function.
441 bool IsEligibleForTailCallOptimization(SDValue Callee,
442 CallingConv::ID CalleeCC,
444 bool isCalleeStructRet,
445 bool isCallerStructRet,
446 const SmallVectorImpl<ISD::OutputArg> &Outs,
447 const SmallVectorImpl<SDValue> &OutVals,
448 const SmallVectorImpl<ISD::InputArg> &Ins,
449 SelectionDAG& DAG) const;
451 LowerReturn(SDValue Chain,
452 CallingConv::ID CallConv, bool isVarArg,
453 const SmallVectorImpl<ISD::OutputArg> &Outs,
454 const SmallVectorImpl<SDValue> &OutVals,
455 DebugLoc dl, SelectionDAG &DAG) const;
457 virtual bool isUsedByReturnOnly(SDNode *N) const;
459 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
460 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
461 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
462 SelectionDAG &DAG, DebugLoc dl) const;
464 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
466 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
467 MachineBasicBlock *BB,
468 unsigned Size) const;
469 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
470 MachineBasicBlock *BB,
472 unsigned BinOpcode) const;
476 enum NEONModImmType {
484 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
488 #endif // ARMISELLOWERING_H