1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
380 let Inst{11-4} = 0b00000000;
382 let isCommutable = Commutable;
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
391 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
392 /// instruction modifies the CPSR register.
393 let Defs = [CPSR] in {
394 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
395 bit Commutable = 0> {
396 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
397 IIC_iALUi, opc, "\t$dst, $a, $b",
398 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
402 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
403 IIC_iALUr, opc, "\t$dst, $a, $b",
404 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
405 let isCommutable = Commutable;
406 let Inst{11-4} = 0b00000000;
410 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
411 IIC_iALUsr, opc, "\t$dst, $a, $b",
412 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
419 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
420 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
421 /// a explicit result, only implicitly set CPSR.
422 let Defs = [CPSR] in {
423 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
425 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
427 [(opnode GPR:$a, so_imm:$b)]> {
431 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
433 [(opnode GPR:$a, GPR:$b)]> {
434 let Inst{11-4} = 0b00000000;
437 let isCommutable = Commutable;
439 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
441 [(opnode GPR:$a, so_reg:$b)]> {
448 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
449 /// register and one whose operand is a register rotated by 8/16/24.
450 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
451 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
452 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
453 IIC_iUNAr, opc, "\t$dst, $src",
454 [(set GPR:$dst, (opnode GPR:$src))]>,
455 Requires<[IsARM, HasV6]> {
456 let Inst{11-10} = 0b00;
457 let Inst{19-16} = 0b1111;
459 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
460 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
461 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
462 Requires<[IsARM, HasV6]> {
463 let Inst{19-16} = 0b1111;
467 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
468 /// register and one whose operand is a register rotated by 8/16/24.
469 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
470 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
471 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
472 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
473 Requires<[IsARM, HasV6]> {
474 let Inst{11-10} = 0b00;
476 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
477 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
478 [(set GPR:$dst, (opnode GPR:$LHS,
479 (rotr GPR:$RHS, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
483 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
484 let Uses = [CPSR] in {
485 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
486 bit Commutable = 0> {
487 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
488 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
490 Requires<[IsARM, CarryDefIsUnused]> {
493 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
494 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
497 let isCommutable = Commutable;
498 let Inst{11-4} = 0b00000000;
501 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
502 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
503 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
504 Requires<[IsARM, CarryDefIsUnused]> {
508 // Carry setting variants
509 let Defs = [CPSR] in {
510 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
511 bit Commutable = 0> {
512 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
513 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
514 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
515 Requires<[IsARM, CarryDefIsUsed]> {
520 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
521 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
522 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
523 Requires<[IsARM, CarryDefIsUsed]> {
525 let Inst{11-4} = 0b00000000;
529 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
530 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
532 Requires<[IsARM, CarryDefIsUsed]> {
541 //===----------------------------------------------------------------------===//
543 //===----------------------------------------------------------------------===//
545 //===----------------------------------------------------------------------===//
546 // Miscellaneous Instructions.
549 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
550 /// the function. The first operand is the ID# for this instruction, the second
551 /// is the index into the MachineConstantPool that this is, the third is the
552 /// size in bytes of this constant pool entry.
553 let neverHasSideEffects = 1, isNotDuplicable = 1 in
554 def CONSTPOOL_ENTRY :
555 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
556 i32imm:$size), NoItinerary,
557 "${instid:label} ${cpidx:cpentry}", []>;
559 let Defs = [SP], Uses = [SP] in {
561 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
562 "@ ADJCALLSTACKUP $amt1",
563 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
565 def ADJCALLSTACKDOWN :
566 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKDOWN $amt",
568 [(ARMcallseq_start timm:$amt)]>;
572 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
573 ".loc $file, $line, $col",
574 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
577 // Address computation and loads and stores in PIC mode.
578 let isNotDuplicable = 1 in {
579 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
580 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
581 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
583 let AddedComplexity = 10 in {
584 let canFoldAsLoad = 1 in
585 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
586 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
587 [(set GPR:$dst, (load addrmodepc:$addr))]>;
589 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
590 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
591 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
593 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
594 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
595 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
597 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
598 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
599 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
601 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
602 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
603 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
605 let AddedComplexity = 10 in {
606 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
608 [(store GPR:$src, addrmodepc:$addr)]>;
610 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
611 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
612 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
614 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
615 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
616 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
618 } // isNotDuplicable = 1
621 // LEApcrel - Load a pc-relative address into a register without offending the
623 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
625 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
626 "${:private}PCRELL${:uid}+8))\n"),
627 !strconcat("${:private}PCRELL${:uid}:\n\t",
628 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
631 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
632 (ins i32imm:$label, nohash_imm:$id, pred:$p),
634 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
636 "${:private}PCRELL${:uid}+8))\n"),
637 !strconcat("${:private}PCRELL${:uid}:\n\t",
638 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
643 //===----------------------------------------------------------------------===//
644 // Control Flow Instructions.
647 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
648 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
649 "bx", "\tlr", [(ARMretflag)]> {
650 let Inst{3-0} = 0b1110;
651 let Inst{7-4} = 0b0001;
652 let Inst{19-8} = 0b111111111111;
653 let Inst{27-20} = 0b00010010;
657 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
658 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
659 [(brind GPR:$dst)]> {
660 let Inst{7-4} = 0b0001;
661 let Inst{19-8} = 0b111111111111;
662 let Inst{27-20} = 0b00010010;
663 let Inst{31-28} = 0b1110;
667 // FIXME: remove when we have a way to marking a MI with these properties.
668 // FIXME: Should pc be an implicit operand like PICADD, etc?
669 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
670 hasExtraDefRegAllocReq = 1 in
671 def LDM_RET : AXI4ld<(outs),
672 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
673 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
676 // On non-Darwin platforms R9 is callee-saved.
678 Defs = [R0, R1, R2, R3, R12, LR,
679 D0, D1, D2, D3, D4, D5, D6, D7,
680 D16, D17, D18, D19, D20, D21, D22, D23,
681 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
682 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
683 IIC_Br, "bl\t${func:call}",
684 [(ARMcall tglobaladdr:$func)]>,
685 Requires<[IsARM, IsNotDarwin]> {
686 let Inst{31-28} = 0b1110;
689 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
690 IIC_Br, "bl", "\t${func:call}",
691 [(ARMcall_pred tglobaladdr:$func)]>,
692 Requires<[IsARM, IsNotDarwin]>;
695 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
696 IIC_Br, "blx\t$func",
697 [(ARMcall GPR:$func)]>,
698 Requires<[IsARM, HasV5T, IsNotDarwin]> {
699 let Inst{7-4} = 0b0011;
700 let Inst{19-8} = 0b111111111111;
701 let Inst{27-20} = 0b00010010;
705 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
706 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
707 [(ARMcall_nolink GPR:$func)]>,
708 Requires<[IsARM, IsNotDarwin]> {
709 let Inst{7-4} = 0b0001;
710 let Inst{19-8} = 0b111111111111;
711 let Inst{27-20} = 0b00010010;
715 // On Darwin R9 is call-clobbered.
717 Defs = [R0, R1, R2, R3, R9, R12, LR,
718 D0, D1, D2, D3, D4, D5, D6, D7,
719 D16, D17, D18, D19, D20, D21, D22, D23,
720 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
721 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
722 IIC_Br, "bl\t${func:call}",
723 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
724 let Inst{31-28} = 0b1110;
727 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
728 IIC_Br, "bl", "\t${func:call}",
729 [(ARMcall_pred tglobaladdr:$func)]>,
730 Requires<[IsARM, IsDarwin]>;
733 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
734 IIC_Br, "blx\t$func",
735 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
736 let Inst{7-4} = 0b0011;
737 let Inst{19-8} = 0b111111111111;
738 let Inst{27-20} = 0b00010010;
742 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
743 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
744 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
745 let Inst{7-4} = 0b0001;
746 let Inst{19-8} = 0b111111111111;
747 let Inst{27-20} = 0b00010010;
751 let isBranch = 1, isTerminator = 1 in {
752 // B is "predicable" since it can be xformed into a Bcc.
753 let isBarrier = 1 in {
754 let isPredicable = 1 in
755 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
756 "b\t$target", [(br bb:$target)]>;
758 let isNotDuplicable = 1, isIndirectBranch = 1 in {
759 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
760 IIC_Br, "mov\tpc, $target \n$jt",
761 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
762 let Inst{15-12} = 0b1111;
763 let Inst{20} = 0; // S Bit
764 let Inst{24-21} = 0b1101;
765 let Inst{27-25} = 0b000;
767 def BR_JTm : JTI<(outs),
768 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
769 IIC_Br, "ldr\tpc, $target \n$jt",
770 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
772 let Inst{15-12} = 0b1111;
773 let Inst{20} = 1; // L bit
774 let Inst{21} = 0; // W bit
775 let Inst{22} = 0; // B bit
776 let Inst{24} = 1; // P bit
777 let Inst{27-25} = 0b011;
779 def BR_JTadd : JTI<(outs),
780 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
781 IIC_Br, "add\tpc, $target, $idx \n$jt",
782 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
784 let Inst{15-12} = 0b1111;
785 let Inst{20} = 0; // S bit
786 let Inst{24-21} = 0b0100;
787 let Inst{27-25} = 0b000;
789 } // isNotDuplicable = 1, isIndirectBranch = 1
792 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
793 // a two-value operand where a dag node expects two operands. :(
794 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
795 IIC_Br, "b", "\t$target",
796 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
799 //===----------------------------------------------------------------------===//
800 // Load / store Instructions.
804 let canFoldAsLoad = 1, isReMaterializable = 1 in
805 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
806 "ldr", "\t$dst, $addr",
807 [(set GPR:$dst, (load addrmode2:$addr))]>;
809 // Special LDR for loads from non-pc-relative constpools.
810 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
811 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
812 "ldr", "\t$dst, $addr", []>;
814 // Loads with zero extension
815 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
816 IIC_iLoadr, "ldrh", "\t$dst, $addr",
817 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
819 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
820 IIC_iLoadr, "ldrb", "\t$dst, $addr",
821 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
823 // Loads with sign extension
824 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
825 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
826 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
828 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
829 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
830 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
832 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
834 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
835 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
836 []>, Requires<[IsARM, HasV5TE]>;
839 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
841 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
843 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
845 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
847 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
849 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
851 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
853 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
855 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
857 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
859 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
861 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
863 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
865 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
867 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
869 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
871 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
873 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
875 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
877 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
881 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
882 "str", "\t$src, $addr",
883 [(store GPR:$src, addrmode2:$addr)]>;
885 // Stores with truncate
886 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
887 "strh", "\t$src, $addr",
888 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
890 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
891 "strb", "\t$src, $addr",
892 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
895 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
896 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
897 StMiscFrm, IIC_iStorer,
898 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
901 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset),
904 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
908 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am2offset:$offset),
911 "str", "\t$src, [$base], $offset", "$base = $base_wb",
913 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
915 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
916 (ins GPR:$src, GPR:$base,am3offset:$offset),
917 StMiscFrm, IIC_iStoreru,
918 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
920 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
922 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
923 (ins GPR:$src, GPR:$base,am3offset:$offset),
924 StMiscFrm, IIC_iStoreru,
925 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
926 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
927 GPR:$base, am3offset:$offset))]>;
929 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
930 (ins GPR:$src, GPR:$base,am2offset:$offset),
932 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
933 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
934 GPR:$base, am2offset:$offset))]>;
936 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
937 (ins GPR:$src, GPR:$base,am2offset:$offset),
939 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
940 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
941 GPR:$base, am2offset:$offset))]>;
943 //===----------------------------------------------------------------------===//
944 // Load / store multiple Instructions.
947 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
948 def LDM : AXI4ld<(outs),
949 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
950 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
953 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
954 def STM : AXI4st<(outs),
955 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
956 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
959 //===----------------------------------------------------------------------===//
960 // Move Instructions.
963 let neverHasSideEffects = 1 in
964 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
965 "mov", "\t$dst, $src", []>, UnaryDP {
966 let Inst{11-4} = 0b00000000;
970 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
971 DPSoRegFrm, IIC_iMOVsr,
972 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
976 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
977 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
978 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
982 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
983 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
985 "movw", "\t$dst, $src",
986 [(set GPR:$dst, imm0_65535:$src)]>,
987 Requires<[IsARM, HasV6T2]> {
992 let Constraints = "$src = $dst" in
993 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
995 "movt", "\t$dst, $imm",
997 (or (and GPR:$src, 0xffff),
998 lo16AllZero:$imm))]>, UnaryDP,
999 Requires<[IsARM, HasV6T2]> {
1004 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1005 Requires<[IsARM, HasV6T2]>;
1007 let Uses = [CPSR] in
1008 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1009 "mov", "\t$dst, $src, rrx",
1010 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1012 // These aren't really mov instructions, but we have to define them this way
1013 // due to flag operands.
1015 let Defs = [CPSR] in {
1016 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1017 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1018 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1019 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1020 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1021 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1024 //===----------------------------------------------------------------------===//
1025 // Extend Instructions.
1030 defm SXTB : AI_unary_rrot<0b01101010,
1031 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1032 defm SXTH : AI_unary_rrot<0b01101011,
1033 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1035 defm SXTAB : AI_bin_rrot<0b01101010,
1036 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1037 defm SXTAH : AI_bin_rrot<0b01101011,
1038 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1040 // TODO: SXT(A){B|H}16
1044 let AddedComplexity = 16 in {
1045 defm UXTB : AI_unary_rrot<0b01101110,
1046 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1047 defm UXTH : AI_unary_rrot<0b01101111,
1048 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1049 defm UXTB16 : AI_unary_rrot<0b01101100,
1050 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1052 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1053 (UXTB16r_rot GPR:$Src, 24)>;
1054 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1055 (UXTB16r_rot GPR:$Src, 8)>;
1057 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1058 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1059 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1060 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1063 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1064 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1066 // TODO: UXT(A){B|H}16
1068 def SBFX : I<(outs GPR:$dst),
1069 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1070 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1071 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1072 Requires<[IsARM, HasV6T2]> {
1073 let Inst{27-21} = 0b0111101;
1074 let Inst{6-4} = 0b101;
1077 def UBFX : I<(outs GPR:$dst),
1078 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1079 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1080 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1081 Requires<[IsARM, HasV6T2]> {
1082 let Inst{27-21} = 0b0111111;
1083 let Inst{6-4} = 0b101;
1086 //===----------------------------------------------------------------------===//
1087 // Arithmetic Instructions.
1090 defm ADD : AsI1_bin_irs<0b0100, "add",
1091 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1092 defm SUB : AsI1_bin_irs<0b0010, "sub",
1093 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1095 // ADD and SUB with 's' bit set.
1096 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1097 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1098 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1099 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1101 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1102 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1103 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1104 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1105 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1106 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1107 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1108 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1110 // These don't define reg/reg forms, because they are handled above.
1111 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1112 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1113 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1117 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1118 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1119 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1123 // RSB with 's' bit set.
1124 let Defs = [CPSR] in {
1125 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1126 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1127 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1131 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1132 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1133 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1139 let Uses = [CPSR] in {
1140 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1141 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1142 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1143 Requires<[IsARM, CarryDefIsUnused]> {
1146 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1147 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1148 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1149 Requires<[IsARM, CarryDefIsUnused]> {
1154 // FIXME: Allow these to be predicated.
1155 let Defs = [CPSR], Uses = [CPSR] in {
1156 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1157 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1158 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1159 Requires<[IsARM, CarryDefIsUnused]> {
1163 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1164 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1165 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1166 Requires<[IsARM, CarryDefIsUnused]> {
1172 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1173 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1174 (SUBri GPR:$src, so_imm_neg:$imm)>;
1176 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1177 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1178 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1179 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1181 // Note: These are implemented in C++ code, because they have to generate
1182 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1184 // (mul X, 2^n+1) -> (add (X << n), X)
1185 // (mul X, 2^n-1) -> (rsb X, (X << n))
1188 //===----------------------------------------------------------------------===//
1189 // Bitwise Instructions.
1192 defm AND : AsI1_bin_irs<0b0000, "and",
1193 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1194 defm ORR : AsI1_bin_irs<0b1100, "orr",
1195 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1196 defm EOR : AsI1_bin_irs<0b0001, "eor",
1197 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1198 defm BIC : AsI1_bin_irs<0b1110, "bic",
1199 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1201 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1202 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1203 "bfc", "\t$dst, $imm", "$src = $dst",
1204 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1205 Requires<[IsARM, HasV6T2]> {
1206 let Inst{27-21} = 0b0111110;
1207 let Inst{6-0} = 0b0011111;
1210 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1211 "mvn", "\t$dst, $src",
1212 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1213 let Inst{11-4} = 0b00000000;
1215 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1216 IIC_iMOVsr, "mvn", "\t$dst, $src",
1217 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1218 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1219 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1220 IIC_iMOVi, "mvn", "\t$dst, $imm",
1221 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1225 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1226 (BICri GPR:$src, so_imm_not:$imm)>;
1228 //===----------------------------------------------------------------------===//
1229 // Multiply Instructions.
1232 let isCommutable = 1 in
1233 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1234 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1235 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1237 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1238 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1239 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1241 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1242 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1243 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1244 Requires<[IsARM, HasV6T2]>;
1246 // Extra precision multiplies with low / high results
1247 let neverHasSideEffects = 1 in {
1248 let isCommutable = 1 in {
1249 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1250 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1251 "smull", "\t$ldst, $hdst, $a, $b", []>;
1253 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1254 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1255 "umull", "\t$ldst, $hdst, $a, $b", []>;
1258 // Multiply + accumulate
1259 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1260 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1261 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1263 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1264 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1265 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1267 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1268 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1269 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1270 Requires<[IsARM, HasV6]>;
1271 } // neverHasSideEffects
1273 // Most significant word multiply
1274 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1275 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1276 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1277 Requires<[IsARM, HasV6]> {
1278 let Inst{7-4} = 0b0001;
1279 let Inst{15-12} = 0b1111;
1282 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1283 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1284 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1285 Requires<[IsARM, HasV6]> {
1286 let Inst{7-4} = 0b0001;
1290 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1291 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1292 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1293 Requires<[IsARM, HasV6]> {
1294 let Inst{7-4} = 0b1101;
1297 multiclass AI_smul<string opc, PatFrag opnode> {
1298 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1299 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1300 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1301 (sext_inreg GPR:$b, i16)))]>,
1302 Requires<[IsARM, HasV5TE]> {
1307 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1308 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1309 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1310 (sra GPR:$b, (i32 16))))]>,
1311 Requires<[IsARM, HasV5TE]> {
1316 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1317 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1318 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1319 (sext_inreg GPR:$b, i16)))]>,
1320 Requires<[IsARM, HasV5TE]> {
1325 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1326 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1327 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1328 (sra GPR:$b, (i32 16))))]>,
1329 Requires<[IsARM, HasV5TE]> {
1334 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1335 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1336 [(set GPR:$dst, (sra (opnode GPR:$a,
1337 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1338 Requires<[IsARM, HasV5TE]> {
1343 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1344 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1345 [(set GPR:$dst, (sra (opnode GPR:$a,
1346 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1347 Requires<[IsARM, HasV5TE]> {
1354 multiclass AI_smla<string opc, PatFrag opnode> {
1355 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1356 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1357 [(set GPR:$dst, (add GPR:$acc,
1358 (opnode (sext_inreg GPR:$a, i16),
1359 (sext_inreg GPR:$b, i16))))]>,
1360 Requires<[IsARM, HasV5TE]> {
1365 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1366 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1367 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1368 (sra GPR:$b, (i32 16)))))]>,
1369 Requires<[IsARM, HasV5TE]> {
1374 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1375 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1376 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1377 (sext_inreg GPR:$b, i16))))]>,
1378 Requires<[IsARM, HasV5TE]> {
1383 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1384 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1385 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1386 (sra GPR:$b, (i32 16)))))]>,
1387 Requires<[IsARM, HasV5TE]> {
1392 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1393 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1394 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1395 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1396 Requires<[IsARM, HasV5TE]> {
1401 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1402 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1403 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1404 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1405 Requires<[IsARM, HasV5TE]> {
1411 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1412 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1414 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1415 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1417 //===----------------------------------------------------------------------===//
1418 // Misc. Arithmetic Instructions.
1421 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1422 "clz", "\t$dst, $src",
1423 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1424 let Inst{7-4} = 0b0001;
1425 let Inst{11-8} = 0b1111;
1426 let Inst{19-16} = 0b1111;
1429 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1430 "rev", "\t$dst, $src",
1431 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1432 let Inst{7-4} = 0b0011;
1433 let Inst{11-8} = 0b1111;
1434 let Inst{19-16} = 0b1111;
1437 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1438 "rev16", "\t$dst, $src",
1440 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1441 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1442 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1443 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1444 Requires<[IsARM, HasV6]> {
1445 let Inst{7-4} = 0b1011;
1446 let Inst{11-8} = 0b1111;
1447 let Inst{19-16} = 0b1111;
1450 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1451 "revsh", "\t$dst, $src",
1454 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1455 (shl GPR:$src, (i32 8))), i16))]>,
1456 Requires<[IsARM, HasV6]> {
1457 let Inst{7-4} = 0b1011;
1458 let Inst{11-8} = 0b1111;
1459 let Inst{19-16} = 0b1111;
1462 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1463 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1464 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1465 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1466 (and (shl GPR:$src2, (i32 imm:$shamt)),
1468 Requires<[IsARM, HasV6]> {
1469 let Inst{6-4} = 0b001;
1472 // Alternate cases for PKHBT where identities eliminate some nodes.
1473 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1474 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1475 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1476 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1479 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1480 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1481 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1482 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1483 (and (sra GPR:$src2, imm16_31:$shamt),
1484 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1485 let Inst{6-4} = 0b101;
1488 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1489 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1490 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1491 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1492 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1493 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1494 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1496 //===----------------------------------------------------------------------===//
1497 // Comparison Instructions...
1500 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1501 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1502 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1503 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1505 // Note that TST/TEQ don't set all the same flags that CMP does!
1506 defm TST : AI1_cmp_irs<0b1000, "tst",
1507 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1508 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1509 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1511 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1512 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1513 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1514 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1516 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1517 (CMNri GPR:$src, so_imm_neg:$imm)>;
1519 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1520 (CMNri GPR:$src, so_imm_neg:$imm)>;
1523 // Conditional moves
1524 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1525 // a two-value operand where a dag node expects two operands. :(
1526 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1527 IIC_iCMOVr, "mov", "\t$dst, $true",
1528 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1529 RegConstraint<"$false = $dst">, UnaryDP {
1530 let Inst{11-4} = 0b00000000;
1534 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1535 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1536 "mov", "\t$dst, $true",
1537 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1538 RegConstraint<"$false = $dst">, UnaryDP {
1542 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1543 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1544 "mov", "\t$dst, $true",
1545 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1546 RegConstraint<"$false = $dst">, UnaryDP {
1551 //===----------------------------------------------------------------------===//
1555 // __aeabi_read_tp preserves the registers r1-r3.
1557 Defs = [R0, R12, LR, CPSR] in {
1558 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1559 "bl\t__aeabi_read_tp",
1560 [(set R0, ARMthread_pointer)]>;
1563 //===----------------------------------------------------------------------===//
1564 // SJLJ Exception handling intrinsics
1565 // eh_sjlj_setjmp() is an instruction sequence to store the return
1566 // address and save #0 in R0 for the non-longjmp case.
1567 // Since by its nature we may be coming from some other function to get
1568 // here, and we're using the stack frame for the containing function to
1569 // save/restore registers, we can't keep anything live in regs across
1570 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1571 // when we get here from a longjmp(). We force everthing out of registers
1572 // except for our own input by listing the relevant registers in Defs. By
1573 // doing so, we also cause the prologue/epilogue code to actively preserve
1574 // all of the callee-saved resgisters, which is exactly what we want.
1576 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1577 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1578 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1580 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1581 AddrModeNone, SizeSpecial, IndexModeNone,
1582 Pseudo, NoItinerary,
1583 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1584 "add\tr12, pc, #8\n\t"
1585 "str\tr12, [$src, #+4]\n\t"
1587 "add\tpc, pc, #0\n\t"
1588 "mov\tr0, #1 @ eh_setjmp end", "",
1589 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1592 //===----------------------------------------------------------------------===//
1593 // Non-Instruction Patterns
1596 // ConstantPool, GlobalAddress, and JumpTable
1597 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1598 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1599 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1600 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1602 // Large immediate handling.
1604 // Two piece so_imms.
1605 let isReMaterializable = 1 in
1606 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1608 "mov", "\t$dst, $src",
1609 [(set GPR:$dst, so_imm2part:$src)]>,
1610 Requires<[IsARM, NoV6T2]>;
1612 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1613 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1614 (so_imm2part_2 imm:$RHS))>;
1615 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1616 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1617 (so_imm2part_2 imm:$RHS))>;
1618 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1619 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1620 (so_imm2part_2 imm:$RHS))>;
1621 def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1622 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1623 (so_imm2part_2 imm:$RHS))>;
1625 // 32-bit immediate using movw + movt.
1626 // This is a single pseudo instruction, the benefit is that it can be remat'd
1627 // as a single unit instead of having to handle reg inputs.
1628 // FIXME: Remove this when we can do generalized remat.
1629 let isReMaterializable = 1 in
1630 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1631 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1632 [(set GPR:$dst, (i32 imm:$src))]>,
1633 Requires<[IsARM, HasV6T2]>;
1635 // TODO: add,sub,and, 3-instr forms?
1639 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1640 Requires<[IsARM, IsNotDarwin]>;
1641 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1642 Requires<[IsARM, IsDarwin]>;
1644 // zextload i1 -> zextload i8
1645 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1647 // extload -> zextload
1648 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1649 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1650 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1652 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1653 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1656 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1657 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1658 (SMULBB GPR:$a, GPR:$b)>;
1659 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1660 (SMULBB GPR:$a, GPR:$b)>;
1661 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1662 (sra GPR:$b, (i32 16))),
1663 (SMULBT GPR:$a, GPR:$b)>;
1664 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1665 (SMULBT GPR:$a, GPR:$b)>;
1666 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1667 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1668 (SMULTB GPR:$a, GPR:$b)>;
1669 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1670 (SMULTB GPR:$a, GPR:$b)>;
1671 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1673 (SMULWB GPR:$a, GPR:$b)>;
1674 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1675 (SMULWB GPR:$a, GPR:$b)>;
1677 def : ARMV5TEPat<(add GPR:$acc,
1678 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1679 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1680 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1681 def : ARMV5TEPat<(add GPR:$acc,
1682 (mul sext_16_node:$a, sext_16_node:$b)),
1683 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1684 def : ARMV5TEPat<(add GPR:$acc,
1685 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1686 (sra GPR:$b, (i32 16)))),
1687 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1688 def : ARMV5TEPat<(add GPR:$acc,
1689 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1690 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1691 def : ARMV5TEPat<(add GPR:$acc,
1692 (mul (sra GPR:$a, (i32 16)),
1693 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1694 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1695 def : ARMV5TEPat<(add GPR:$acc,
1696 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1697 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1698 def : ARMV5TEPat<(add GPR:$acc,
1699 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1701 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1702 def : ARMV5TEPat<(add GPR:$acc,
1703 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1704 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1706 //===----------------------------------------------------------------------===//
1710 include "ARMInstrThumb.td"
1712 //===----------------------------------------------------------------------===//
1716 include "ARMInstrThumb2.td"
1718 //===----------------------------------------------------------------------===//
1719 // Floating Point Support
1722 include "ARMInstrVFP.td"
1724 //===----------------------------------------------------------------------===//
1725 // Advanced SIMD (NEON) Support
1728 include "ARMInstrNEON.td"