1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
97 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
98 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
99 def HasNEON : Predicate<"Subtarget->hasNEON()">;
100 def IsThumb : Predicate<"Subtarget->isThumb()">;
101 def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
102 def IsARM : Predicate<"!Subtarget->isThumb()">;
103 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
104 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
106 //===----------------------------------------------------------------------===//
107 // ARM Flag Definitions.
109 class RegConstraint<string C> {
110 string Constraints = C;
113 //===----------------------------------------------------------------------===//
114 // ARM specific transformation functions and pattern fragments.
117 // so_imm_XFORM - Return a so_imm value packed into the format described for
119 def so_imm_XFORM : SDNodeXForm<imm, [{
120 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
124 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
125 // so_imm_neg def below.
126 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
131 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
132 // so_imm_not def below.
133 def so_imm_not_XFORM : SDNodeXForm<imm, [{
134 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
138 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
139 def rot_imm : PatLeaf<(i32 imm), [{
140 int32_t v = (int32_t)N->getZExtValue();
141 return v == 8 || v == 16 || v == 24;
144 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
145 def imm1_15 : PatLeaf<(i32 imm), [{
146 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
149 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
150 def imm16_31 : PatLeaf<(i32 imm), [{
151 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
156 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
157 }], so_imm_neg_XFORM>;
161 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
162 }], so_imm_not_XFORM>;
164 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
165 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
166 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
169 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
170 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
172 //===----------------------------------------------------------------------===//
173 // Operand Definitions.
177 def brtarget : Operand<OtherVT>;
179 // A list of registers separated by comma. Used by load/store multiple.
180 def reglist : Operand<i32> {
181 let PrintMethod = "printRegisterList";
184 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
185 def cpinst_operand : Operand<i32> {
186 let PrintMethod = "printCPInstOperand";
189 def jtblock_operand : Operand<i32> {
190 let PrintMethod = "printJTBlockOperand";
194 def pclabel : Operand<i32> {
195 let PrintMethod = "printPCLabel";
198 // shifter_operand operands: so_reg and so_imm.
199 def so_reg : Operand<i32>, // reg reg imm
200 ComplexPattern<i32, 3, "SelectShifterOperandReg",
201 [shl,srl,sra,rotr]> {
202 let PrintMethod = "printSORegOperand";
203 let MIOperandInfo = (ops GPR, GPR, i32imm);
206 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
207 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
208 // represented in the imm field in the same 12-bit form that they are encoded
209 // into so_imm instructions: the 8-bit immediate is the least significant bits
210 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
211 def so_imm : Operand<i32>,
213 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
215 let PrintMethod = "printSOImmOperand";
218 // Break so_imm's up into two pieces. This handles immediates with up to 16
219 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
220 // get the first/second pieces.
221 def so_imm2part : Operand<i32>,
223 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
225 let PrintMethod = "printSOImm2PartOperand";
228 def so_imm2part_1 : SDNodeXForm<imm, [{
229 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
230 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
233 def so_imm2part_2 : SDNodeXForm<imm, [{
234 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
235 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
239 // Define ARM specific addressing modes.
241 // addrmode2 := reg +/- reg shop imm
242 // addrmode2 := reg +/- imm12
244 def addrmode2 : Operand<i32>,
245 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
246 let PrintMethod = "printAddrMode2Operand";
247 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
250 def am2offset : Operand<i32>,
251 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
252 let PrintMethod = "printAddrMode2OffsetOperand";
253 let MIOperandInfo = (ops GPR, i32imm);
256 // addrmode3 := reg +/- reg
257 // addrmode3 := reg +/- imm8
259 def addrmode3 : Operand<i32>,
260 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
261 let PrintMethod = "printAddrMode3Operand";
262 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
265 def am3offset : Operand<i32>,
266 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
267 let PrintMethod = "printAddrMode3OffsetOperand";
268 let MIOperandInfo = (ops GPR, i32imm);
271 // addrmode4 := reg, <mode|W>
273 def addrmode4 : Operand<i32>,
274 ComplexPattern<i32, 2, "", []> {
275 let PrintMethod = "printAddrMode4Operand";
276 let MIOperandInfo = (ops GPR, i32imm);
279 // addrmode5 := reg +/- imm8*4
281 def addrmode5 : Operand<i32>,
282 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
283 let PrintMethod = "printAddrMode5Operand";
284 let MIOperandInfo = (ops GPR, i32imm);
287 // addrmodepc := pc + reg
289 def addrmodepc : Operand<i32>,
290 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
291 let PrintMethod = "printAddrModePCOperand";
292 let MIOperandInfo = (ops GPR, i32imm);
295 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
296 // register whose default is 0 (no register).
297 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
298 (ops (i32 14), (i32 zero_reg))> {
299 let PrintMethod = "printPredicateOperand";
302 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
304 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
305 let PrintMethod = "printSBitModifierOperand";
308 //===----------------------------------------------------------------------===//
309 // ARM Instruction flags. These need to match ARMInstrInfo.h.
313 class AddrMode<bits<4> val> {
316 def AddrModeNone : AddrMode<0>;
317 def AddrMode1 : AddrMode<1>;
318 def AddrMode2 : AddrMode<2>;
319 def AddrMode3 : AddrMode<3>;
320 def AddrMode4 : AddrMode<4>;
321 def AddrMode5 : AddrMode<5>;
322 def AddrModeT1 : AddrMode<6>;
323 def AddrModeT2 : AddrMode<7>;
324 def AddrModeT4 : AddrMode<8>;
325 def AddrModeTs : AddrMode<9>;
328 class SizeFlagVal<bits<3> val> {
331 def SizeInvalid : SizeFlagVal<0>; // Unset.
332 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
333 def Size8Bytes : SizeFlagVal<2>;
334 def Size4Bytes : SizeFlagVal<3>;
335 def Size2Bytes : SizeFlagVal<4>;
337 // Load / store index mode.
338 class IndexMode<bits<2> val> {
341 def IndexModeNone : IndexMode<0>;
342 def IndexModePre : IndexMode<1>;
343 def IndexModePost : IndexMode<2>;
345 //===----------------------------------------------------------------------===//
347 include "ARMInstrFormats.td"
349 //===----------------------------------------------------------------------===//
350 // Multiclass helpers...
353 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
354 /// binop that produces a value.
355 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
356 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
357 opc, " $dst, $a, $b",
358 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
359 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
360 opc, " $dst, $a, $b",
361 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
362 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
363 opc, " $dst, $a, $b",
364 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
367 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
368 /// instruction modifies the CSPR register.
369 let Defs = [CPSR] in {
370 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
371 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
372 opc, "s $dst, $a, $b",
373 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
374 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
375 opc, "s $dst, $a, $b",
376 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
377 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
378 opc, "s $dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
383 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
384 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
385 /// a explicit result, only implicitly set CPSR.
386 let Defs = [CPSR] in {
387 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
388 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
390 [(opnode GPR:$a, so_imm:$b)]>;
391 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
393 [(opnode GPR:$a, GPR:$b)]>;
394 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
396 [(opnode GPR:$a, so_reg:$b)]>;
400 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
401 /// register and one whose operand is a register rotated by 8/16/24.
402 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
403 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
404 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
406 [(set GPR:$dst, (opnode GPR:$Src))]>,
407 Requires<[IsARM, HasV6]> {
408 let Inst{19-16} = 0b1111;
410 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
411 opc, " $dst, $Src, ror $rot",
412 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
413 Requires<[IsARM, HasV6]> {
414 let Inst{19-16} = 0b1111;
418 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
419 /// register and one whose operand is a register rotated by 8/16/24.
420 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
421 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
422 opc, " $dst, $LHS, $RHS",
423 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
424 Requires<[IsARM, HasV6]>;
425 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
426 opc, " $dst, $LHS, $RHS, ror $rot",
427 [(set GPR:$dst, (opnode GPR:$LHS,
428 (rotr GPR:$RHS, rot_imm:$rot)))]>,
429 Requires<[IsARM, HasV6]>;
432 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
433 /// setting carry bit. But it can optionally set CPSR.
434 let Uses = [CPSR] in {
435 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
436 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
437 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
438 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
439 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
440 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
441 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
442 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
443 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
444 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
448 //===----------------------------------------------------------------------===//
450 //===----------------------------------------------------------------------===//
452 //===----------------------------------------------------------------------===//
453 // Miscellaneous Instructions.
456 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
457 /// the function. The first operand is the ID# for this instruction, the second
458 /// is the index into the MachineConstantPool that this is, the third is the
459 /// size in bytes of this constant pool entry.
460 let neverHasSideEffects = 1, isNotDuplicable = 1 in
461 def CONSTPOOL_ENTRY :
462 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
464 "${instid:label} ${cpidx:cpentry}", []>;
466 let Defs = [SP], Uses = [SP] in {
468 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
469 "@ ADJCALLSTACKUP $amt1",
470 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
472 def ADJCALLSTACKDOWN :
473 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
474 "@ ADJCALLSTACKDOWN $amt",
475 [(ARMcallseq_start timm:$amt)]>;
479 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
480 ".loc $file, $line, $col",
481 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
484 // Address computation and loads and stores in PIC mode.
485 let isNotDuplicable = 1 in {
486 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
487 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
488 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
490 let AddedComplexity = 10 in {
491 let canFoldAsLoad = 1 in
492 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
493 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
494 [(set GPR:$dst, (load addrmodepc:$addr))]>;
496 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
497 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
498 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
500 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
501 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
502 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
504 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
505 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
506 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
508 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
509 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
510 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
512 let AddedComplexity = 10 in {
513 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
514 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
515 [(store GPR:$src, addrmodepc:$addr)]>;
517 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
518 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
519 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
521 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
522 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
523 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
525 } // isNotDuplicable = 1
528 // LEApcrel - Load a pc-relative address into a register without offending the
530 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
531 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
532 "${:private}PCRELL${:uid}+8))\n"),
533 !strconcat("${:private}PCRELL${:uid}:\n\t",
534 "add$p $dst, pc, #PCRELV${:uid}")),
537 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
539 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
540 "${:private}PCRELL${:uid}+8))\n"),
541 !strconcat("${:private}PCRELL${:uid}:\n\t",
542 "add$p $dst, pc, #PCRELV${:uid}")),
545 //===----------------------------------------------------------------------===//
546 // Control Flow Instructions.
549 let isReturn = 1, isTerminator = 1 in
550 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
551 let Inst{7-4} = 0b0001;
552 let Inst{19-8} = 0b111111111111;
553 let Inst{27-20} = 0b00010010;
556 // FIXME: remove when we have a way to marking a MI with these properties.
557 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
559 // FIXME: Should pc be an implicit operand like PICADD, etc?
560 let isReturn = 1, isTerminator = 1 in
561 def LDM_RET : AXI4ld<(outs),
562 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
563 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
566 // On non-Darwin platforms R9 is callee-saved.
567 let isCall = 1, Itinerary = IIC_Br,
568 Defs = [R0, R1, R2, R3, R12, LR,
569 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
570 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
572 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
574 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
575 "bl", " ${func:call}",
576 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
579 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
581 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
582 let Inst{7-4} = 0b0011;
583 let Inst{19-8} = 0b111111111111;
584 let Inst{27-20} = 0b00010010;
589 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
590 "mov lr, pc\n\tbx $func",
591 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
595 // On Darwin R9 is call-clobbered.
596 let isCall = 1, Itinerary = IIC_Br,
597 Defs = [R0, R1, R2, R3, R9, R12, LR,
598 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
599 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
601 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
603 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
604 "bl", " ${func:call}",
605 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
608 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
610 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
611 let Inst{7-4} = 0b0011;
612 let Inst{19-8} = 0b111111111111;
613 let Inst{27-20} = 0b00010010;
618 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
619 "mov lr, pc\n\tbx $func",
620 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
624 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
625 // B is "predicable" since it can be xformed into a Bcc.
626 let isBarrier = 1 in {
627 let isPredicable = 1 in
628 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
631 let isNotDuplicable = 1, isIndirectBranch = 1 in {
632 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
633 "mov pc, $target \n$jt",
634 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
635 let Inst{20} = 0; // S Bit
636 let Inst{24-21} = 0b1101;
637 let Inst{27-26} = {0,0};
639 def BR_JTm : JTI<(outs),
640 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
641 "ldr pc, $target \n$jt",
642 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
644 let Inst{20} = 1; // L bit
645 let Inst{21} = 0; // W bit
646 let Inst{22} = 0; // B bit
647 let Inst{24} = 1; // P bit
648 let Inst{27-26} = {0,1};
650 def BR_JTadd : JTI<(outs),
651 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
652 "add pc, $target, $idx \n$jt",
653 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
655 let Inst{20} = 0; // S bit
656 let Inst{24-21} = 0b0100;
657 let Inst{27-26} = {0,0};
659 } // isNotDuplicable = 1, isIndirectBranch = 1
662 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
663 // a two-value operand where a dag node expects two operands. :(
664 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
666 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
669 //===----------------------------------------------------------------------===//
670 // Load / store Instructions.
674 let canFoldAsLoad = 1 in
675 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
676 "ldr", " $dst, $addr",
677 [(set GPR:$dst, (load addrmode2:$addr))]>;
679 // Special LDR for loads from non-pc-relative constpools.
680 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
681 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
682 "ldr", " $dst, $addr", []>;
684 // Loads with zero extension
685 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
686 "ldr", "h $dst, $addr",
687 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
689 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
690 "ldr", "b $dst, $addr",
691 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
693 // Loads with sign extension
694 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
695 "ldr", "sh $dst, $addr",
696 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
698 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
699 "ldr", "sb $dst, $addr",
700 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
704 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
705 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
708 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
709 (ins addrmode2:$addr), LdFrm,
710 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
712 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
713 (ins GPR:$base, am2offset:$offset), LdFrm,
714 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
716 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
717 (ins addrmode3:$addr), LdMiscFrm,
718 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
720 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
721 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
722 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
724 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
725 (ins addrmode2:$addr), LdFrm,
726 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
728 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
729 (ins GPR:$base,am2offset:$offset), LdFrm,
730 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
732 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
733 (ins addrmode3:$addr), LdMiscFrm,
734 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
736 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
737 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
738 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
740 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
741 (ins addrmode3:$addr), LdMiscFrm,
742 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
744 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
745 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
746 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
750 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
751 "str", " $src, $addr",
752 [(store GPR:$src, addrmode2:$addr)]>;
754 // Stores with truncate
755 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
756 "str", "h $src, $addr",
757 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
759 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
760 "str", "b $src, $addr",
761 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
765 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
766 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
769 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
770 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
771 "str", " $src, [$base, $offset]!", "$base = $base_wb",
773 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
775 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
776 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
777 "str", " $src, [$base], $offset", "$base = $base_wb",
779 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
781 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
782 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
783 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
785 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
787 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
788 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
789 "str", "h $src, [$base], $offset", "$base = $base_wb",
790 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
791 GPR:$base, am3offset:$offset))]>;
793 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
794 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
795 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
796 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
797 GPR:$base, am2offset:$offset))]>;
799 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
800 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
801 "str", "b $src, [$base], $offset", "$base = $base_wb",
802 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
803 GPR:$base, am2offset:$offset))]>;
805 //===----------------------------------------------------------------------===//
806 // Load / store multiple Instructions.
809 // FIXME: $dst1 should be a def.
811 def LDM : AXI4ld<(outs),
812 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
813 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
817 def STM : AXI4st<(outs),
818 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
819 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
822 //===----------------------------------------------------------------------===//
823 // Move Instructions.
826 let neverHasSideEffects = 1 in
827 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
828 "mov", " $dst, $src", []>, UnaryDP;
829 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
830 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
832 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
833 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
834 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
836 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
837 "mov", " $dst, $src, rrx",
838 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
840 // These aren't really mov instructions, but we have to define them this way
841 // due to flag operands.
843 let Defs = [CPSR] in {
844 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
845 "mov", "s $dst, $src, lsr #1",
846 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
847 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
848 "mov", "s $dst, $src, asr #1",
849 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
852 //===----------------------------------------------------------------------===//
853 // Extend Instructions.
858 defm SXTB : AI_unary_rrot<0b01101010,
859 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
860 defm SXTH : AI_unary_rrot<0b01101011,
861 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
863 defm SXTAB : AI_bin_rrot<0b01101010,
864 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
865 defm SXTAH : AI_bin_rrot<0b01101011,
866 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
868 // TODO: SXT(A){B|H}16
872 let AddedComplexity = 16 in {
873 defm UXTB : AI_unary_rrot<0b01101110,
874 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
875 defm UXTH : AI_unary_rrot<0b01101111,
876 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
877 defm UXTB16 : AI_unary_rrot<0b01101100,
878 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
880 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
881 (UXTB16r_rot GPR:$Src, 24)>;
882 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
883 (UXTB16r_rot GPR:$Src, 8)>;
885 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
886 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
887 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
888 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
891 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
892 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
894 // TODO: UXT(A){B|H}16
896 //===----------------------------------------------------------------------===//
897 // Arithmetic Instructions.
900 defm ADD : AsI1_bin_irs<0b0100, "add",
901 BinOpFrag<(add node:$LHS, node:$RHS)>>;
902 defm SUB : AsI1_bin_irs<0b0010, "sub",
903 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
905 // ADD and SUB with 's' bit set.
906 defm ADDS : ASI1_bin_s_irs<0b0100, "add",
907 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
908 defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
909 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
911 // FIXME: Do not allow ADC / SBC to be predicated for now.
912 defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
913 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
914 defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
915 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
917 // These don't define reg/reg forms, because they are handled above.
918 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
919 "rsb", " $dst, $a, $b",
920 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
922 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
923 "rsb", " $dst, $a, $b",
924 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
926 // RSB with 's' bit set.
927 let Defs = [CPSR] in {
928 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
929 "rsb", "s $dst, $a, $b",
930 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
931 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
932 "rsb", "s $dst, $a, $b",
933 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
936 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
937 let Uses = [CPSR] in {
938 def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
939 DPFrm, "rsc${s} $dst, $a, $b",
940 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
941 def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
942 DPSoRegFrm, "rsc${s} $dst, $a, $b",
943 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
946 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
947 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
948 (SUBri GPR:$src, so_imm_neg:$imm)>;
950 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
951 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
952 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
953 // (SBCri GPR:$src, so_imm_neg:$imm)>;
955 // Note: These are implemented in C++ code, because they have to generate
956 // ADD/SUBrs instructions, which use a complex pattern that a xform function
958 // (mul X, 2^n+1) -> (add (X << n), X)
959 // (mul X, 2^n-1) -> (rsb X, (X << n))
962 //===----------------------------------------------------------------------===//
963 // Bitwise Instructions.
966 defm AND : AsI1_bin_irs<0b0000, "and",
967 BinOpFrag<(and node:$LHS, node:$RHS)>>;
968 defm ORR : AsI1_bin_irs<0b1100, "orr",
969 BinOpFrag<(or node:$LHS, node:$RHS)>>;
970 defm EOR : AsI1_bin_irs<0b0001, "eor",
971 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
972 defm BIC : AsI1_bin_irs<0b1110, "bic",
973 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
975 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
976 "mvn", " $dst, $src",
977 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
978 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
979 "mvn", " $dst, $src",
980 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
981 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
982 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
983 "mvn", " $dst, $imm",
984 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
986 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
987 (BICri GPR:$src, so_imm_not:$imm)>;
989 //===----------------------------------------------------------------------===//
990 // Multiply Instructions.
993 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
994 "mul", " $dst, $a, $b",
995 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
997 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
998 "mla", " $dst, $a, $b, $c",
999 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1001 // Extra precision multiplies with low / high results
1002 let neverHasSideEffects = 1 in {
1003 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1004 (ins GPR:$a, GPR:$b),
1005 "smull", " $ldst, $hdst, $a, $b", []>;
1007 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1008 (ins GPR:$a, GPR:$b),
1009 "umull", " $ldst, $hdst, $a, $b", []>;
1011 // Multiply + accumulate
1012 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1013 (ins GPR:$a, GPR:$b),
1014 "smlal", " $ldst, $hdst, $a, $b", []>;
1016 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1017 (ins GPR:$a, GPR:$b),
1018 "umlal", " $ldst, $hdst, $a, $b", []>;
1020 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1021 (ins GPR:$a, GPR:$b),
1022 "umaal", " $ldst, $hdst, $a, $b", []>,
1023 Requires<[IsARM, HasV6]>;
1024 } // neverHasSideEffects
1026 // Most significant word multiply
1027 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1028 "smmul", " $dst, $a, $b",
1029 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1030 Requires<[IsARM, HasV6]> {
1031 let Inst{7-4} = 0b0001;
1032 let Inst{15-12} = 0b1111;
1035 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1036 "smmla", " $dst, $a, $b, $c",
1037 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1038 Requires<[IsARM, HasV6]> {
1039 let Inst{7-4} = 0b0001;
1043 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1044 "smmls", " $dst, $a, $b, $c",
1045 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1046 Requires<[IsARM, HasV6]> {
1047 let Inst{7-4} = 0b1101;
1050 multiclass AI_smul<string opc, PatFrag opnode> {
1051 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1052 !strconcat(opc, "bb"), " $dst, $a, $b",
1053 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1054 (sext_inreg GPR:$b, i16)))]>,
1055 Requires<[IsARM, HasV5TE]> {
1060 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1061 !strconcat(opc, "bt"), " $dst, $a, $b",
1062 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1063 (sra GPR:$b, (i32 16))))]>,
1064 Requires<[IsARM, HasV5TE]> {
1069 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1070 !strconcat(opc, "tb"), " $dst, $a, $b",
1071 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1072 (sext_inreg GPR:$b, i16)))]>,
1073 Requires<[IsARM, HasV5TE]> {
1078 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1079 !strconcat(opc, "tt"), " $dst, $a, $b",
1080 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1081 (sra GPR:$b, (i32 16))))]>,
1082 Requires<[IsARM, HasV5TE]> {
1087 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1088 !strconcat(opc, "wb"), " $dst, $a, $b",
1089 [(set GPR:$dst, (sra (opnode GPR:$a,
1090 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1091 Requires<[IsARM, HasV5TE]> {
1096 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1097 !strconcat(opc, "wt"), " $dst, $a, $b",
1098 [(set GPR:$dst, (sra (opnode GPR:$a,
1099 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1100 Requires<[IsARM, HasV5TE]> {
1107 multiclass AI_smla<string opc, PatFrag opnode> {
1108 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1109 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1110 [(set GPR:$dst, (add GPR:$acc,
1111 (opnode (sext_inreg GPR:$a, i16),
1112 (sext_inreg GPR:$b, i16))))]>,
1113 Requires<[IsARM, HasV5TE]> {
1118 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1119 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1120 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1121 (sra GPR:$b, (i32 16)))))]>,
1122 Requires<[IsARM, HasV5TE]> {
1127 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1128 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1129 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1130 (sext_inreg GPR:$b, i16))))]>,
1131 Requires<[IsARM, HasV5TE]> {
1136 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1137 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1138 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1139 (sra GPR:$b, (i32 16)))))]>,
1140 Requires<[IsARM, HasV5TE]> {
1145 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1146 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1147 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1148 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1149 Requires<[IsARM, HasV5TE]> {
1154 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1155 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1156 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1157 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1158 Requires<[IsARM, HasV5TE]> {
1164 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1165 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1167 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1168 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1170 //===----------------------------------------------------------------------===//
1171 // Misc. Arithmetic Instructions.
1174 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1175 "clz", " $dst, $src",
1176 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1177 let Inst{7-4} = 0b0001;
1178 let Inst{11-8} = 0b1111;
1179 let Inst{19-16} = 0b1111;
1182 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1183 "rev", " $dst, $src",
1184 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1185 let Inst{7-4} = 0b0011;
1186 let Inst{11-8} = 0b1111;
1187 let Inst{19-16} = 0b1111;
1190 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1191 "rev16", " $dst, $src",
1193 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1194 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1195 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1196 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1197 Requires<[IsARM, HasV6]> {
1198 let Inst{7-4} = 0b1011;
1199 let Inst{11-8} = 0b1111;
1200 let Inst{19-16} = 0b1111;
1203 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1204 "revsh", " $dst, $src",
1207 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1208 (shl GPR:$src, (i32 8))), i16))]>,
1209 Requires<[IsARM, HasV6]> {
1210 let Inst{7-4} = 0b1011;
1211 let Inst{11-8} = 0b1111;
1212 let Inst{19-16} = 0b1111;
1215 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1216 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1217 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1218 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1219 (and (shl GPR:$src2, (i32 imm:$shamt)),
1221 Requires<[IsARM, HasV6]> {
1222 let Inst{6-4} = 0b001;
1225 // Alternate cases for PKHBT where identities eliminate some nodes.
1226 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1227 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1228 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1229 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1232 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1233 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1234 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1235 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1236 (and (sra GPR:$src2, imm16_31:$shamt),
1237 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1238 let Inst{6-4} = 0b101;
1241 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1242 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1243 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1244 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1245 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1246 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1247 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1249 //===----------------------------------------------------------------------===//
1250 // Comparison Instructions...
1253 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1254 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1255 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1256 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1258 // Note that TST/TEQ don't set all the same flags that CMP does!
1259 defm TST : AI1_cmp_irs<0b1000, "tst",
1260 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1261 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1262 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1264 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1265 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1266 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1267 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1269 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1270 (CMNri GPR:$src, so_imm_neg:$imm)>;
1272 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1273 (CMNri GPR:$src, so_imm_neg:$imm)>;
1276 // Conditional moves
1277 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1278 // a two-value operand where a dag node expects two operands. :(
1279 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1280 "mov", " $dst, $true",
1281 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1282 RegConstraint<"$false = $dst">, UnaryDP;
1284 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1285 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1286 "mov", " $dst, $true",
1287 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1288 RegConstraint<"$false = $dst">, UnaryDP;
1290 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1291 (ins GPR:$false, so_imm:$true), DPFrm,
1292 "mov", " $dst, $true",
1293 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1294 RegConstraint<"$false = $dst">, UnaryDP;
1297 //===----------------------------------------------------------------------===//
1301 // __aeabi_read_tp preserves the registers r1-r3.
1303 Defs = [R0, R12, LR, CPSR] in {
1304 def TPsoft : ABXI<0b1011, (outs), (ins),
1305 "bl __aeabi_read_tp",
1306 [(set R0, ARMthread_pointer)]>;
1309 //===----------------------------------------------------------------------===//
1310 // SJLJ Exception handling intrinsics
1311 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1312 // address and save #0 in R0 for the non-longjmp case.
1313 // Since by its nature we may be coming from some other function to get
1314 // here, and we're using the stack frame for the containing function to
1315 // save/restore registers, we can't keep anything live in regs across
1316 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1317 // when we get here from a longjmp(). We force everthing out of registers
1318 // except for our own input by listing the relevant registers in Defs. By
1319 // doing so, we also cause the prologue/epilogue code to actively preserve
1320 // all of the callee-saved resgisters, which is exactly what we want.
1322 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1323 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1324 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1325 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1326 "add r0, pc, #4\n\t"
1327 "str r0, [$src, #+4]\n\t"
1328 "mov r0, #0 @ eh_setjmp", "",
1329 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1332 //===----------------------------------------------------------------------===//
1333 // Non-Instruction Patterns
1336 // ConstantPool, GlobalAddress, and JumpTable
1337 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1338 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1339 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1340 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1342 // Large immediate handling.
1344 // Two piece so_imms.
1345 let isReMaterializable = 1 in
1346 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1347 "mov", " $dst, $src",
1348 [(set GPR:$dst, so_imm2part:$src)]>;
1350 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1351 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1352 (so_imm2part_2 imm:$RHS))>;
1353 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1354 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1355 (so_imm2part_2 imm:$RHS))>;
1357 // TODO: add,sub,and, 3-instr forms?
1361 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1362 Requires<[IsNotDarwin]>;
1363 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1364 Requires<[IsDarwin]>;
1366 // zextload i1 -> zextload i8
1367 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1369 // extload -> zextload
1370 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1371 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1372 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1374 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1375 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1378 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1379 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1380 (SMULBB GPR:$a, GPR:$b)>;
1381 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1382 (SMULBB GPR:$a, GPR:$b)>;
1383 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1384 (sra GPR:$b, (i32 16))),
1385 (SMULBT GPR:$a, GPR:$b)>;
1386 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1387 (SMULBT GPR:$a, GPR:$b)>;
1388 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1389 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1390 (SMULTB GPR:$a, GPR:$b)>;
1391 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1392 (SMULTB GPR:$a, GPR:$b)>;
1393 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1395 (SMULWB GPR:$a, GPR:$b)>;
1396 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1397 (SMULWB GPR:$a, GPR:$b)>;
1399 def : ARMV5TEPat<(add GPR:$acc,
1400 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1401 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1402 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1403 def : ARMV5TEPat<(add GPR:$acc,
1404 (mul sext_16_node:$a, sext_16_node:$b)),
1405 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1406 def : ARMV5TEPat<(add GPR:$acc,
1407 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1408 (sra GPR:$b, (i32 16)))),
1409 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1410 def : ARMV5TEPat<(add GPR:$acc,
1411 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1412 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1413 def : ARMV5TEPat<(add GPR:$acc,
1414 (mul (sra GPR:$a, (i32 16)),
1415 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1416 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1417 def : ARMV5TEPat<(add GPR:$acc,
1418 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1419 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1420 def : ARMV5TEPat<(add GPR:$acc,
1421 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1423 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1424 def : ARMV5TEPat<(add GPR:$acc,
1425 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1426 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1428 //===----------------------------------------------------------------------===//
1432 include "ARMInstrThumb.td"
1434 //===----------------------------------------------------------------------===//
1438 include "ARMInstrThumb2.td"
1440 //===----------------------------------------------------------------------===//
1441 // Floating Point Support
1444 include "ARMInstrVFP.td"
1446 //===----------------------------------------------------------------------===//
1447 // Advanced SIMD (NEON) Support
1450 include "ARMInstrNEON.td"