1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "llvm/Target/TargetInstrItineraries.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtarget.h"
25 class ARMSubtarget : public TargetSubtarget {
28 V4T, V5T, V5TE, V6, V6T2, V7A
32 None, VFPv2, VFPv3, NEON
40 /// ARMArchVersion - ARM architecture version: V4T (base), V5T, V5TE,
42 ARMArchEnum ARMArchVersion;
44 /// ARMFPUType - Floating Point Unit type.
47 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
48 /// specified. Use the method useNEONForSinglePrecisionFP() to
49 /// determine if NEON should actually be used.
50 bool UseNEONForSinglePrecisionFP;
52 /// IsThumb - True if we are in thumb mode, false if in ARM mode.
55 /// ThumbMode - Indicates supported Thumb version.
56 ThumbTypeEnum ThumbMode;
58 /// PostRAScheduler - True if using post-register-allocation scheduler.
61 /// IsR9Reserved - True if R9 is a not available as general purpose register.
64 /// stackAlignment - The minimum alignment known to hold of the stack frame on
65 /// entry to the function and which must be maintained by every function.
66 unsigned stackAlignment;
68 /// CPUString - String name of used CPU.
69 std::string CPUString;
71 /// Selected instruction itineraries (one entry per itinerary class.)
72 InstrItineraryData InstrItins;
81 ARM_ABI_AAPCS // ARM EABI
84 /// This constructor initializes the data members to match that
85 /// of the specified triple.
87 ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
89 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
90 /// that still makes it profitable to inline the call.
91 unsigned getMaxInlineSizeThreshold() const {
92 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb.
93 // Change this once Thumb ldmia / stmia support is added.
94 return isThumb() ? 0 : 64;
96 /// ParseSubtargetFeatures - Parses features string setting specified
97 /// subtarget options. Definition of function is auto generated by tblgen.
98 std::string ParseSubtargetFeatures(const std::string &FS,
99 const std::string &CPU);
101 bool hasV4TOps() const { return ARMArchVersion >= V4T; }
102 bool hasV5TOps() const { return ARMArchVersion >= V5T; }
103 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
104 bool hasV6Ops() const { return ARMArchVersion >= V6; }
105 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
106 bool hasV7Ops() const { return ARMArchVersion >= V7A; }
108 bool hasVFP2() const { return ARMFPUType >= VFPv2; }
109 bool hasVFP3() const { return ARMFPUType >= VFPv3; }
110 bool hasNEON() const { return ARMFPUType >= NEON; }
111 bool useNEONForSinglePrecisionFP() const {
112 return hasNEON() && UseNEONForSinglePrecisionFP; }
114 bool isTargetDarwin() const { return TargetType == isDarwin; }
115 bool isTargetELF() const { return TargetType == isELF; }
117 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
118 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
120 bool isThumb() const { return IsThumb; }
121 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
122 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
123 bool hasThumb2() const { return ThumbMode >= Thumb2; }
125 bool isR9Reserved() const { return IsR9Reserved; }
127 const std::string & getCPUString() const { return CPUString; }
129 /// enablePostRAScheduler - True at 'More' optimization except
131 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
132 TargetSubtarget::AntiDepBreakMode& mode) const {
133 mode = TargetSubtarget::ANTIDEP_NONE;
134 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
137 /// getInstrItins - Return the instruction itineraies based on subtarget
139 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
141 /// getStackAlignment - Returns the minimum alignment known to hold of the
142 /// stack frame on entry to the function and which must be maintained by every
143 /// function for this subtarget.
144 unsigned getStackAlignment() const { return stackAlignment; }
146 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
148 bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const;
150 } // End llvm namespace
152 #endif // ARMSUBTARGET_H