1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
21 #include "ARMTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 #include "llvm/Target/TargetLowering.h"
28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
29 typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
30 typedef TargetTransformInfo TTI;
33 const ARMSubtarget *ST;
34 const ARMTargetLowering *TLI;
36 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
37 /// are set if the result needs to be inserted and/or extracted from vectors.
38 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
40 const ARMSubtarget *getST() const { return ST; }
41 const ARMTargetLowering *getTLI() const { return TLI; }
44 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
45 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
46 TLI(ST->getTargetLowering()) {}
48 bool enableInterleavedAccessVectorization() { return true; }
50 /// Floating-point computation using ARMv8 AArch32 Advanced
51 /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
52 /// is IEEE-754 compliant, but it's not covered in this target.
53 bool isFPVectorizationPotentiallyUnsafe() {
54 return !ST->isTargetDarwin();
57 /// \name Scalar TTI Implementations
60 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
63 using BaseT::getIntImmCost;
64 int getIntImmCost(const APInt &Imm, Type *Ty);
66 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
70 /// \name Vector TTI Implementations
73 unsigned getNumberOfRegisters(bool Vector) {
80 if (ST->isThumb1Only())
85 unsigned getRegisterBitWidth(bool Vector) {
95 unsigned getMaxInterleaveFactor(unsigned VF) {
96 return ST->getMaxInterleaveFactor();
99 int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
101 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
103 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
105 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
107 int getAddressComputationCost(Type *Val, ScalarEvolution *SE,
110 int getFPOpCost(Type *Ty);
112 int getArithmeticInstrCost(
113 unsigned Opcode, Type *Ty,
114 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
115 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
116 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
117 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
118 ArrayRef<const Value *> Args = ArrayRef<const Value *>());
120 int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
121 unsigned AddressSpace);
123 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
124 ArrayRef<unsigned> Indices, unsigned Alignment,
125 unsigned AddressSpace);
127 bool shouldBuildLookupTablesForConstant(Constant *C) const {
128 // In the ROPI and RWPI relocation models we can't have pointers to global
129 // variables or functions in constant data, so don't convert switches to
130 // lookup tables if any of the values would need relocation.
131 if (ST->isROPI() || ST->isRWPI())
132 return !C->needsRelocation();
139 } // end namespace llvm