1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2InstrInfo.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Support/CommandLine.h"
31 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
32 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
35 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
36 : ARMBaseInstrInfo(STI), RI(*this, STI) {
39 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
46 MachineBasicBlock *NewDest) const {
47 MachineBasicBlock *MBB = Tail->getParent();
48 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
49 if (!AFI->hasITBlocks()) {
50 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
54 // If the first instruction of Tail is predicated, we may have to update
55 // the IT instruction.
57 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
58 MachineBasicBlock::iterator MBBI = Tail;
60 // Expecting at least the t2IT instruction before it.
63 // Actually replace the tail.
64 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
67 if (CC != ARMCC::AL) {
68 MachineBasicBlock::iterator E = MBB->begin();
69 unsigned Count = 4; // At most 4 instructions in an IT block.
70 while (Count && MBBI != E) {
71 if (MBBI->isDebugValue()) {
75 if (MBBI->getOpcode() == ARM::t2IT) {
76 unsigned Mask = MBBI->getOperand(1).getImm();
78 MBBI->eraseFromParent();
80 unsigned MaskOn = 1 << Count;
81 unsigned MaskOff = ~(MaskOn - 1);
82 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
90 // Ctrl flow can reach here if branch folding is run before IT block
96 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI) const {
99 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
102 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I, DebugLoc DL,
104 unsigned DestReg, unsigned SrcReg,
105 bool KillSrc) const {
106 // Handle SPR, DPR, and QPR copies.
107 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
108 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
110 bool tDest = ARM::tGPRRegClass.contains(DestReg);
111 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
112 unsigned Opc = ARM::tMOVgpr2gpr;
116 Opc = ARM::tMOVtgpr2gpr;
118 Opc = ARM::tMOVgpr2tgpr;
120 BuildMI(MBB, I, DL, get(Opc), DestReg)
121 .addReg(SrcReg, getKillRegState(KillSrc));
124 void Thumb2InstrInfo::
125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned SrcReg, bool isKill, int FI,
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const {
129 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
130 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
132 if (I != MBB.end()) DL = I->getDebugLoc();
134 MachineFunction &MF = *MBB.getParent();
135 MachineFrameInfo &MFI = *MF.getFrameInfo();
136 MachineMemOperand *MMO =
137 MF.getMachineMemOperand(
138 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
139 MachineMemOperand::MOStore,
140 MFI.getObjectSize(FI),
141 MFI.getObjectAlignment(FI));
142 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
143 .addReg(SrcReg, getKillRegState(isKill))
144 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
148 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
151 void Thumb2InstrInfo::
152 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
153 unsigned DestReg, int FI,
154 const TargetRegisterClass *RC,
155 const TargetRegisterInfo *TRI) const {
156 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
157 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
159 if (I != MBB.end()) DL = I->getDebugLoc();
161 MachineFunction &MF = *MBB.getParent();
162 MachineFrameInfo &MFI = *MF.getFrameInfo();
163 MachineMemOperand *MMO =
164 MF.getMachineMemOperand(
165 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
166 MachineMemOperand::MOLoad,
167 MFI.getObjectSize(FI),
168 MFI.getObjectAlignment(FI));
169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
170 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
177 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
179 unsigned DestReg, unsigned BaseReg, int NumBytes,
180 ARMCC::CondCodes Pred, unsigned PredReg,
181 const ARMBaseInstrInfo &TII) {
182 bool isSub = NumBytes < 0;
183 if (isSub) NumBytes = -NumBytes;
185 // If profitable, use a movw or movt to materialize the offset.
186 // FIXME: Use the scavenger to grab a scratch register.
187 if (DestReg != ARM::SP && DestReg != BaseReg &&
189 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
191 if (NumBytes < 65536) {
192 // Use a movw to materialize the 16-bit constant.
193 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
195 .addImm((unsigned)Pred).addReg(PredReg);
197 } else if ((NumBytes & 0xffff) == 0) {
198 // Use a movt to materialize the 32-bit constant.
199 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
201 .addImm(NumBytes >> 16)
202 .addImm((unsigned)Pred).addReg(PredReg);
208 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
209 .addReg(BaseReg, RegState::Kill)
210 .addReg(DestReg, RegState::Kill)
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
213 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
214 .addReg(DestReg, RegState::Kill)
215 .addReg(BaseReg, RegState::Kill)
216 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
223 unsigned ThisVal = NumBytes;
225 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
226 // mov sp, rn. Note t2MOVr cannot be used.
227 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
232 bool HasCCOut = true;
233 if (BaseReg == ARM::SP) {
235 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
236 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
237 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
238 // FIXME: Fix Thumb1 immediate encoding.
239 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
240 .addReg(BaseReg).addImm(ThisVal/4);
245 // sub rd, sp, so_imm
246 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
247 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
250 // FIXME: Move this to ARMAddressingModes.h?
251 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
252 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
253 NumBytes &= ~ThisVal;
254 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
255 "Bit extraction didn't work?");
258 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
259 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
260 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
262 } else if (ThisVal < 4096) {
263 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
267 // FIXME: Move this to ARMAddressingModes.h?
268 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
269 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
270 NumBytes &= ~ThisVal;
271 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
272 "Bit extraction didn't work?");
276 // Build the new ADD / SUB.
277 MachineInstrBuilder MIB =
278 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
279 .addReg(BaseReg, RegState::Kill)
289 negativeOffsetOpcode(unsigned opcode)
292 case ARM::t2LDRi12: return ARM::t2LDRi8;
293 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
294 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
295 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
296 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
297 case ARM::t2STRi12: return ARM::t2STRi8;
298 case ARM::t2STRBi12: return ARM::t2STRBi8;
299 case ARM::t2STRHi12: return ARM::t2STRHi8;
319 positiveOffsetOpcode(unsigned opcode)
322 case ARM::t2LDRi8: return ARM::t2LDRi12;
323 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
324 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
325 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
326 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
327 case ARM::t2STRi8: return ARM::t2STRi12;
328 case ARM::t2STRBi8: return ARM::t2STRBi12;
329 case ARM::t2STRHi8: return ARM::t2STRHi12;
334 case ARM::t2LDRSHi12:
335 case ARM::t2LDRSBi12:
349 immediateOffsetOpcode(unsigned opcode)
352 case ARM::t2LDRs: return ARM::t2LDRi12;
353 case ARM::t2LDRHs: return ARM::t2LDRHi12;
354 case ARM::t2LDRBs: return ARM::t2LDRBi12;
355 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
356 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
357 case ARM::t2STRs: return ARM::t2STRi12;
358 case ARM::t2STRBs: return ARM::t2STRBi12;
359 case ARM::t2STRHs: return ARM::t2STRHi12;
364 case ARM::t2LDRSHi12:
365 case ARM::t2LDRSBi12:
386 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
387 unsigned FrameReg, int &Offset,
388 const ARMBaseInstrInfo &TII) {
389 unsigned Opcode = MI.getOpcode();
390 const TargetInstrDesc &Desc = MI.getDesc();
391 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
394 // Memory operands in inline assembly always use AddrModeT2_i12.
395 if (Opcode == ARM::INLINEASM)
396 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
398 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
399 Offset += MI.getOperand(FrameRegIdx+1).getImm();
402 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
403 // Turn it into a move.
404 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
405 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
406 // Remove offset and remaining explicit predicate operands.
407 do MI.RemoveOperand(FrameRegIdx+1);
408 while (MI.getNumOperands() > FrameRegIdx+1 &&
409 (!MI.getOperand(FrameRegIdx+1).isReg() ||
410 !MI.getOperand(FrameRegIdx+1).isImm()));
414 bool isSP = FrameReg == ARM::SP;
415 bool HasCCOut = Opcode != ARM::t2ADDri12;
420 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
422 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
425 // Common case: small offset, fits into instruction.
426 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
427 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
428 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
429 // Add cc_out operand if the original instruction did not have one.
431 MI.addOperand(MachineOperand::CreateReg(0, false));
435 // Another common case: imm12.
437 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
438 unsigned NewOpc = isSP
439 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
440 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
441 MI.setDesc(TII.get(NewOpc));
442 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
443 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
444 // Remove the cc_out operand.
446 MI.RemoveOperand(MI.getNumOperands()-1);
451 // Otherwise, extract 8 adjacent bits from the immediate into this
453 unsigned RotAmt = CountLeadingZeros_32(Offset);
454 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
456 // We will handle these bits from offset, clear them.
457 Offset &= ~ThisImmVal;
459 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
460 "Bit extraction didn't work?");
461 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
462 // Add cc_out operand if the original instruction did not have one.
464 MI.addOperand(MachineOperand::CreateReg(0, false));
468 // AddrMode4 and AddrMode6 cannot handle any offset.
469 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
472 // AddrModeT2_so cannot handle any offset. If there is no offset
473 // register then we change to an immediate version.
474 unsigned NewOpc = Opcode;
475 if (AddrMode == ARMII::AddrModeT2_so) {
476 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
477 if (OffsetReg != 0) {
478 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
482 MI.RemoveOperand(FrameRegIdx+1);
483 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
484 NewOpc = immediateOffsetOpcode(Opcode);
485 AddrMode = ARMII::AddrModeT2_i12;
488 unsigned NumBits = 0;
490 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
491 // i8 supports only negative, and i12 supports only positive, so
492 // based on Offset sign convert Opcode to the appropriate
494 Offset += MI.getOperand(FrameRegIdx+1).getImm();
496 NewOpc = negativeOffsetOpcode(Opcode);
501 NewOpc = positiveOffsetOpcode(Opcode);
504 } else if (AddrMode == ARMII::AddrMode5) {
506 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
507 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
508 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
512 Offset += InstrOffs * 4;
513 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
519 llvm_unreachable("Unsupported addressing mode!");
522 if (NewOpc != Opcode)
523 MI.setDesc(TII.get(NewOpc));
525 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
527 // Attempt to fold address computation
528 // Common case: small offset, fits into instruction.
529 int ImmedOffset = Offset / Scale;
530 unsigned Mask = (1 << NumBits) - 1;
531 if ((unsigned)Offset <= Mask * Scale) {
532 // Replace the FrameIndex with fp/sp
533 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
535 if (AddrMode == ARMII::AddrMode5)
536 // FIXME: Not consistent.
537 ImmedOffset |= 1 << NumBits;
539 ImmedOffset = -ImmedOffset;
541 ImmOp.ChangeToImmediate(ImmedOffset);
546 // Otherwise, offset doesn't fit. Pull in what we can to simplify
547 ImmedOffset = ImmedOffset & Mask;
549 if (AddrMode == ARMII::AddrMode5)
550 // FIXME: Not consistent.
551 ImmedOffset |= 1 << NumBits;
553 ImmedOffset = -ImmedOffset;
554 if (ImmedOffset == 0)
555 // Change the opcode back if the encoded offset is zero.
556 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
559 ImmOp.ChangeToImmediate(ImmedOffset);
560 Offset &= ~(Mask*Scale);
563 Offset = (isSub) ? -Offset : Offset;
567 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
568 /// two-addrss instruction inserted by two-address pass.
570 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
572 const TargetRegisterInfo &TRI) const {
573 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
574 SrcMI->getOperand(1).isKill())
577 unsigned PredReg = 0;
578 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
579 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
582 // Schedule the copy so it doesn't come between previous instructions
583 // and UseMI which can form an IT block.
584 unsigned SrcReg = SrcMI->getOperand(1).getReg();
585 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
586 MachineBasicBlock *MBB = UseMI->getParent();
587 MachineBasicBlock::iterator MBBI = SrcMI;
588 unsigned NumInsts = 0;
589 while (--MBBI != MBB->begin()) {
590 if (MBBI->isDebugValue())
593 MachineInstr *NMI = &*MBBI;
594 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
595 if (!(NCC == CC || NCC == OCC) ||
596 NMI->modifiesRegister(SrcReg, &TRI) ||
597 NMI->definesRegister(ARM::CPSR))
600 // Too many in a row!
606 MBB->insert(++MBBI, SrcMI);
611 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
612 unsigned Opc = MI->getOpcode();
613 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
615 return llvm::getInstrPredicate(MI, PredReg);