1 //===----------------------------------------------------------------------===//
2 // MicroMIPS Base Classes
3 //===----------------------------------------------------------------------===//
6 // Base class for MicroMips instructions.
7 // This class does not depend on the instruction size.
9 class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
10 InstrItinClass itin, Format f> : Instruction
12 let Namespace = "Mips";
13 let DecoderNamespace = "MicroMips";
15 let OutOperandList = outs;
16 let InOperandList = ins;
18 let AsmString = asmstr;
19 let Pattern = pattern;
22 let Predicates = [InMicroMips];
28 // Base class for MicroMIPS 16-bit instructions.
30 class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
31 InstrItinClass itin, Format f> :
32 MicroMipsInstBase<outs, ins, asmstr, pattern, itin, f>
36 field bits<16> SoftFail = 0;
40 //===----------------------------------------------------------------------===//
41 // MicroMIPS 16-bit Instruction Formats
42 //===----------------------------------------------------------------------===//
44 class ARITH_FM_MM16<bit funct> {
51 let Inst{15-10} = 0x01;
58 class ANDI_FM_MM16<bits<6> funct> {
65 let Inst{15-10} = funct;
71 class LOGIC_FM_MM16<bits<4> funct> {
77 let Inst{15-10} = 0x11;
78 let Inst{9-6} = funct;
83 class SHIFT_FM_MM16<bits<1> funct> {
90 let Inst{15-10} = 0x09;
93 let Inst{3-1} = shamt;
97 class ADDIUR2_FM_MM16 {
104 let Inst{15-10} = 0x1b;
111 class LOAD_STORE_FM_MM16<bits<6> op> {
117 let Inst{15-10} = op;
119 let Inst{6-4} = addr{6-4};
120 let Inst{3-0} = addr{3-0};
123 class LOAD_STORE_SP_FM_MM16<bits<6> op> {
129 let Inst{15-10} = op;
131 let Inst{4-0} = offset;
134 class LOAD_GP_FM_MM16<bits<6> op> {
140 let Inst{15-10} = op;
142 let Inst{6-0} = offset;
145 class ADDIUS5_FM_MM16 {
151 let Inst{15-10} = 0x13;
157 class ADDIUSP_FM_MM16 {
162 let Inst{15-10} = 0x13;
167 class MOVE_FM_MM16<bits<6> funct> {
173 let Inst{15-10} = funct;
184 let Inst{15-10} = 0x3b;
189 class JALR_FM_MM16<bits<5> op> {
194 let Inst{15-10} = 0x11;
199 class MFHILO_FM_MM16<bits<5> funct> {
204 let Inst{15-10} = 0x11;
205 let Inst{9-5} = funct;
209 class JRADDIUSP_FM_MM16<bits<5> op> {
215 let Inst{15-10} = 0x11;
220 class ADDIUR1SP_FM_MM16 {
226 let Inst{15-10} = 0x1b;
232 class BRKSDBBP16_FM_MM<bits<6> op> {
236 let Inst{15-10} = 0x11;
238 let Inst{3-0} = code_;
241 class BEQNEZ_FM_MM16<bits<6> op> {
247 let Inst{15-10} = op;
249 let Inst{6-0} = offset;
257 let Inst{15-10} = 0x33;
258 let Inst{9-0} = offset;
261 class MOVEP_FM_MM16 {
268 let Inst{15-10} = 0x21;
269 let Inst{9-7} = dst_regs;
275 //===----------------------------------------------------------------------===//
276 // MicroMIPS 32-bit Instruction Formats
277 //===----------------------------------------------------------------------===//
280 string Arch = "micromips";
283 class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {
290 let Inst{31-26} = op;
291 let Inst{25-21} = rt;
292 let Inst{20-16} = rs;
293 let Inst{15-11} = rd;
295 let Inst{9-0} = funct;
298 class ADDI_FM_MM<bits<6> op> : MMArch {
305 let Inst{31-26} = op;
306 let Inst{25-21} = rt;
307 let Inst{20-16} = rs;
308 let Inst{15-0} = imm16;
311 class SLTI_FM_MM<bits<6> op> : MMArch {
318 let Inst{31-26} = op;
319 let Inst{25-21} = rt;
320 let Inst{20-16} = rs;
321 let Inst{15-0} = imm16;
324 class LUI_FM_MM : MMArch {
330 let Inst{31-26} = 0x10;
331 let Inst{25-21} = 0xd;
332 let Inst{20-16} = rt;
333 let Inst{15-0} = imm16;
336 class MULT_FM_MM<bits<10> funct> : MMArch {
342 let Inst{31-26} = 0x00;
343 let Inst{25-21} = rt;
344 let Inst{20-16} = rs;
345 let Inst{15-6} = funct;
346 let Inst{5-0} = 0x3c;
349 class SRA_FM_MM<bits<10> funct, bit rotate> : MMArch {
357 let Inst{25-21} = rd;
358 let Inst{20-16} = rt;
359 let Inst{15-11} = shamt;
360 let Inst{10} = rotate;
361 let Inst{9-0} = funct;
364 class SRLV_FM_MM<bits<10> funct, bit rotate> : MMArch {
372 let Inst{25-21} = rt;
373 let Inst{20-16} = rs;
374 let Inst{15-11} = rd;
375 let Inst{10} = rotate;
376 let Inst{9-0} = funct;
379 class LW_FM_MM<bits<6> op> : MMArch {
382 bits<5> base = addr{20-16};
383 bits<16> offset = addr{15-0};
387 let Inst{31-26} = op;
388 let Inst{25-21} = rt;
389 let Inst{20-16} = base;
390 let Inst{15-0} = offset;
393 class POOL32C_LHUE_FM_MM<bits<6> op, bits<4> fmt, bits<3> funct> : MMArch {
396 bits<5> base = addr{20-16};
397 bits<9> offset = addr{8-0};
401 let Inst{31-26} = op;
402 let Inst{25-21} = rt;
403 let Inst{20-16} = base;
404 let Inst{15-12} = fmt;
405 let Inst{11-9} = funct;
406 let Inst{8-0} = offset;
409 class LWL_FM_MM<bits<4> funct> {
415 let Inst{31-26} = 0x18;
416 let Inst{25-21} = rt;
417 let Inst{20-16} = addr{20-16};
418 let Inst{15-12} = funct;
419 let Inst{11-0} = addr{11-0};
422 class POOL32C_STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
425 bits<5> base = addr{20-16};
426 bits<9> offset = addr{8-0};
430 let Inst{31-26} = 0x18;
431 let Inst{25-21} = rt;
432 let Inst{20-16} = base;
433 let Inst{15-12} = type;
434 let Inst{11-9} = funct;
435 let Inst{8-0} = offset;
438 class CMov_F_I_FM_MM<bits<7> func> : MMArch {
445 let Inst{31-26} = 0x15;
446 let Inst{25-21} = rd;
447 let Inst{20-16} = rs;
448 let Inst{15-13} = fcc;
449 let Inst{12-6} = func;
450 let Inst{5-0} = 0x3b;
453 class MTLO_FM_MM<bits<10> funct> : MMArch {
458 let Inst{31-26} = 0x00;
459 let Inst{25-21} = 0x00;
460 let Inst{20-16} = rs;
461 let Inst{15-6} = funct;
462 let Inst{5-0} = 0x3c;
465 class MFLO_FM_MM<bits<10> funct> : MMArch {
470 let Inst{31-26} = 0x00;
471 let Inst{25-21} = 0x00;
472 let Inst{20-16} = rd;
473 let Inst{15-6} = funct;
474 let Inst{5-0} = 0x3c;
477 class CLO_FM_MM<bits<10> funct> : MMArch {
483 let Inst{31-26} = 0x00;
484 let Inst{25-21} = rd;
485 let Inst{20-16} = rs;
486 let Inst{15-6} = funct;
487 let Inst{5-0} = 0x3c;
490 class SEB_FM_MM<bits<10> funct> : MMArch {
496 let Inst{31-26} = 0x00;
497 let Inst{25-21} = rd;
498 let Inst{20-16} = rt;
499 let Inst{15-6} = funct;
500 let Inst{5-0} = 0x3c;
503 class EXT_FM_MM<bits<6> funct> : MMArch {
511 let Inst{31-26} = 0x00;
512 let Inst{25-21} = rt;
513 let Inst{20-16} = rs;
514 let Inst{15-11} = size;
515 let Inst{10-6} = pos;
516 let Inst{5-0} = funct;
519 class J_FM_MM<bits<6> op> : MMArch {
524 let Inst{31-26} = op;
525 let Inst{25-0} = target;
528 class JR_FM_MM<bits<8> funct> : MMArch {
533 let Inst{31-21} = 0x00;
534 let Inst{20-16} = rs;
535 let Inst{15-14} = 0x0;
536 let Inst{13-6} = funct;
537 let Inst{5-0} = 0x3c;
540 class JALR_FM_MM<bits<10> funct> {
546 let Inst{31-26} = 0x00;
547 let Inst{25-21} = rd;
548 let Inst{20-16} = rs;
549 let Inst{15-6} = funct;
550 let Inst{5-0} = 0x3c;
553 class BEQ_FM_MM<bits<6> op> : MMArch {
560 let Inst{31-26} = op;
561 let Inst{25-21} = rt;
562 let Inst{20-16} = rs;
563 let Inst{15-0} = offset;
566 class BGEZ_FM_MM<bits<5> funct> : MMArch {
572 let Inst{31-26} = 0x10;
573 let Inst{25-21} = funct;
574 let Inst{20-16} = rs;
575 let Inst{15-0} = offset;
578 class BGEZAL_FM_MM<bits<5> funct> : MMArch {
584 let Inst{31-26} = 0x10;
585 let Inst{25-21} = funct;
586 let Inst{20-16} = rs;
587 let Inst{15-0} = offset;
590 class SYNC_FM_MM : MMArch {
595 let Inst{31-26} = 0x00;
596 let Inst{25-21} = 0x0;
597 let Inst{20-16} = stype;
598 let Inst{15-6} = 0x1ad;
599 let Inst{5-0} = 0x3c;
602 class SYNCI_FM_MM : MMArch {
607 let Inst{31-26} = 0b010000;
608 let Inst{25-21} = 0b10000;
609 let Inst{20-16} = rs;
610 let Inst{15-0} = offset;
613 class BRK_FM_MM : MMArch {
617 let Inst{31-26} = 0x0;
618 let Inst{25-16} = code_1;
619 let Inst{15-6} = code_2;
620 let Inst{5-0} = 0x07;
623 class SYS_FM_MM : MMArch {
626 let Inst{31-26} = 0x0;
627 let Inst{25-16} = code_;
628 let Inst{15-6} = 0x22d;
629 let Inst{5-0} = 0x3c;
636 let Inst{31-26} = 0x00;
637 let Inst{25-16} = code_;
638 let Inst{15-6} = 0x24d;
639 let Inst{5-0} = 0x3c;
642 class ER_FM_MM<bits<10> funct> : MMArch {
645 let Inst{31-26} = 0x00;
646 let Inst{25-16} = 0x00;
647 let Inst{15-6} = funct;
648 let Inst{5-0} = 0x3c;
651 class EI_FM_MM<bits<10> funct> : MMArch {
655 let Inst{31-26} = 0x00;
656 let Inst{25-21} = 0x00;
657 let Inst{20-16} = rt;
658 let Inst{15-6} = funct;
659 let Inst{5-0} = 0x3c;
662 class TEQ_FM_MM<bits<6> funct> : MMArch {
669 let Inst{31-26} = 0x00;
670 let Inst{25-21} = rt;
671 let Inst{20-16} = rs;
672 let Inst{15-12} = code_;
673 let Inst{11-6} = funct;
674 let Inst{5-0} = 0x3c;
677 class TEQI_FM_MM<bits<5> funct> : MMArch {
683 let Inst{31-26} = 0x10;
684 let Inst{25-21} = funct;
685 let Inst{20-16} = rs;
686 let Inst{15-0} = imm16;
689 class LL_FM_MM<bits<4> funct> : MMArch {
695 let Inst{31-26} = 0x18;
696 let Inst{25-21} = rt;
697 let Inst{20-16} = addr{20-16};
698 let Inst{15-12} = funct;
699 let Inst{11-0} = addr{11-0};
702 class LLE_FM_MM<bits<4> funct> {
705 bits<5> base = addr{20-16};
706 bits<9> offset = addr{8-0};
710 let Inst{31-26} = 0x18;
711 let Inst{25-21} = rt;
712 let Inst{20-16} = base;
713 let Inst{15-12} = funct;
714 let Inst{11-9} = 0x6;
715 let Inst{8-0} = offset;
718 class ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
725 let Inst{31-26} = 0x15;
726 let Inst{25-21} = ft;
727 let Inst{20-16} = fs;
728 let Inst{15-11} = fd;
731 let Inst{7-0} = funct;
733 list<dag> Pattern = [];
736 class LWXC1_FM_MM<bits<9> funct> : MMArch {
743 let Inst{31-26} = 0x15;
744 let Inst{25-21} = index;
745 let Inst{20-16} = base;
746 let Inst{15-11} = fd;
747 let Inst{10-9} = 0x0;
748 let Inst{8-0} = funct;
751 class SWXC1_FM_MM<bits<9> funct> : MMArch {
758 let Inst{31-26} = 0x15;
759 let Inst{25-21} = index;
760 let Inst{20-16} = base;
761 let Inst{15-11} = fs;
762 let Inst{10-9} = 0x0;
763 let Inst{8-0} = funct;
766 class CEQS_FM_MM<bits<2> fmt> : MMArch {
774 let Inst{31-26} = 0x15;
775 let Inst{25-21} = ft;
776 let Inst{20-16} = fs;
777 let Inst{15-13} = fcc;
779 let Inst{11-10} = fmt;
780 let Inst{9-6} = cond;
781 let Inst{5-0} = 0x3c;
784 class C_COND_FM_MM<bits <2> fmt, bits<4> c> : CEQS_FM_MM<fmt> {
788 class BC1F_FM_MM<bits<5> tf> : MMArch {
793 let Inst{31-26} = 0x10;
794 let Inst{25-21} = tf;
795 let Inst{20-18} = 0x0; // cc
796 let Inst{17-16} = 0x0;
797 let Inst{15-0} = offset;
800 class ROUND_W_FM_MM<bits<1> fmt, bits<8> funct> : MMArch {
806 let Inst{31-26} = 0x15;
807 let Inst{25-21} = fd;
808 let Inst{20-16} = fs;
811 let Inst{13-6} = funct;
812 let Inst{5-0} = 0x3b;
815 class ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
821 let Inst{31-26} = 0x15;
822 let Inst{25-21} = fd;
823 let Inst{20-16} = fs;
825 let Inst{14-13} = fmt;
826 let Inst{12-6} = funct;
827 let Inst{5-0} = 0x3b;
830 class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
836 let Inst{31-26} = 0x15;
837 let Inst{25-21} = fd;
838 let Inst{20-16} = fs;
839 let Inst{15-13} = 0x0; //cc
840 let Inst{12-11} = 0x0;
841 let Inst{10-9} = fmt;
842 let Inst{8-0} = func;
845 class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
852 let Inst{31-26} = 0x15;
853 let Inst{25-21} = rt;
854 let Inst{20-16} = fs;
855 let Inst{15-11} = fd;
857 let Inst{7-0} = funct;
860 class MFC1_FM_MM<bits<8> funct> : MMArch {
866 let Inst{31-26} = 0x15;
867 let Inst{25-21} = rt;
868 let Inst{20-16} = fs;
869 let Inst{15-14} = 0x0;
870 let Inst{13-6} = funct;
871 let Inst{5-0} = 0x3b;
874 class MADDS_FM_MM<bits<6> funct>: MMArch {
882 let Inst{31-26} = 0x15;
883 let Inst{25-21} = ft;
884 let Inst{20-16} = fs;
885 let Inst{15-11} = fd;
887 let Inst{5-0} = funct;
890 class COMPACT_BRANCH_FM_MM<bits<5> funct> {
896 let Inst{31-26} = 0x10;
897 let Inst{25-21} = funct;
898 let Inst{20-16} = rs;
899 let Inst{15-0} = offset;
902 class COP0_TLB_FM_MM<bits<10> op> : MMArch {
905 let Inst{31-26} = 0x0;
906 let Inst{25-16} = 0x0;
908 let Inst{5-0} = 0x3c;
911 class SDBBP_FM_MM : MMArch {
916 let Inst{31-26} = 0x0;
917 let Inst{25-16} = code_;
918 let Inst{15-6} = 0x36d;
919 let Inst{5-0} = 0x3c;
922 class RDHWR_FM_MM : MMArch {
928 let Inst{31-26} = 0x0;
929 let Inst{25-21} = rt;
930 let Inst{20-16} = rd;
931 let Inst{15-6} = 0x1ac;
932 let Inst{5-0} = 0x3c;
935 class LWXS_FM_MM<bits<10> funct> {
942 let Inst{31-26} = 0x0;
943 let Inst{25-21} = index;
944 let Inst{20-16} = base;
945 let Inst{15-11} = rd;
947 let Inst{9-0} = funct;
950 class LWM_FM_MM<bits<4> funct> : MMArch {
956 let Inst{31-26} = 0x8;
957 let Inst{25-21} = rt;
958 let Inst{20-16} = addr{20-16};
959 let Inst{15-12} = funct;
960 let Inst{11-0} = addr{11-0};
963 class LWM_FM_MM16<bits<4> funct> : MMArch, PredicateControl {
969 let Inst{15-10} = 0x11;
970 let Inst{9-6} = funct;
972 let Inst{3-0} = addr;
975 class CACHE_PREF_FM_MM<bits<6> op, bits<4> funct> : MMArch {
978 bits<5> base = addr{20-16};
979 bits<12> offset = addr{11-0};
983 let Inst{31-26} = op;
984 let Inst{25-21} = hint;
985 let Inst{20-16} = base;
986 let Inst{15-12} = funct;
987 let Inst{11-0} = offset;
990 class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
993 bits<5> base = addr{20-16};
994 bits<9> offset = addr{8-0};
998 let Inst{31-26} = op;
999 let Inst{25-21} = hint;
1000 let Inst{20-16} = base;
1001 let Inst{15-12} = 0xA;
1002 let Inst{11-9} = funct;
1003 let Inst{8-0} = offset;
1006 class POOL32F_PREFX_FM_MM<bits<6> op, bits<9> funct> : MMArch {
1013 let Inst{31-26} = op;
1014 let Inst{25-21} = index;
1015 let Inst{20-16} = base;
1016 let Inst{15-11} = hint;
1017 let Inst{10-9} = 0x0;
1018 let Inst{8-0} = funct;
1021 class BARRIER_FM_MM<bits<5> op> : MMArch {
1024 let Inst{31-26} = 0x0;
1025 let Inst{25-21} = 0x0;
1026 let Inst{20-16} = 0x0;
1027 let Inst{15-11} = op;
1028 let Inst{10-6} = 0x0;
1029 let Inst{5-0} = 0x0;
1032 class ADDIUPC_FM_MM {
1038 let Inst{31-26} = 0x1e;
1039 let Inst{25-23} = rs;
1040 let Inst{22-0} = imm;
1043 class POOL32A_CFTC2_FM_MM<bits<10> funct> : MMArch {
1049 let Inst{31-26} = 0b000000;
1050 let Inst{25-21} = rt;
1051 let Inst{20-16} = impl;
1052 let Inst{15-6} = funct;
1053 let Inst{5-0} = 0b111100;