1 //===----------------------------------------------------------------------===//
2 // MicroMIPS Base Classes
3 //===----------------------------------------------------------------------===//
6 // Base class for MicroMips instructions.
7 // This class does not depend on the instruction size.
9 class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
10 InstrItinClass itin, Format f> : Instruction
12 let Namespace = "Mips";
13 let DecoderNamespace = "MicroMips";
15 let OutOperandList = outs;
16 let InOperandList = ins;
18 let AsmString = asmstr;
19 let Pattern = pattern;
22 let Predicates = [InMicroMips];
28 // Base class for MicroMIPS 16-bit instructions.
30 class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
31 InstrItinClass itin, Format f> :
32 MicroMipsInstBase<outs, ins, asmstr, pattern, itin, f>
36 field bits<16> SoftFail = 0;
40 //===----------------------------------------------------------------------===//
41 // MicroMIPS 16-bit Instruction Formats
42 //===----------------------------------------------------------------------===//
44 class ARITH_FM_MM16<bit funct> {
51 let Inst{15-10} = 0x01;
58 class ANDI_FM_MM16<bits<6> funct> {
65 let Inst{15-10} = funct;
71 class LOGIC_FM_MM16<bits<4> funct> {
77 let Inst{15-10} = 0x11;
78 let Inst{9-6} = funct;
83 class SHIFT_FM_MM16<bits<1> funct> {
90 let Inst{15-10} = 0x09;
93 let Inst{3-1} = shamt;
97 class ADDIUR2_FM_MM16 {
104 let Inst{15-10} = 0x1b;
111 class LOAD_STORE_FM_MM16<bits<6> op> {
117 let Inst{15-10} = op;
119 let Inst{6-4} = addr{6-4};
120 let Inst{3-0} = addr{3-0};
123 class LOAD_STORE_SP_FM_MM16<bits<6> op> {
129 let Inst{15-10} = op;
131 let Inst{4-0} = offset;
134 class LOAD_GP_FM_MM16<bits<6> op> {
140 let Inst{15-10} = op;
142 let Inst{6-0} = offset;
145 class ADDIUS5_FM_MM16 {
151 let Inst{15-10} = 0x13;
157 class ADDIUSP_FM_MM16 {
162 let Inst{15-10} = 0x13;
167 class MOVE_FM_MM16<bits<6> funct> {
173 let Inst{15-10} = funct;
184 let Inst{15-10} = 0x3b;
189 class JALR_FM_MM16<bits<5> op> {
194 let Inst{15-10} = 0x11;
199 class MFHILO_FM_MM16<bits<5> funct> {
204 let Inst{15-10} = 0x11;
205 let Inst{9-5} = funct;
209 class JRADDIUSP_FM_MM16<bits<5> op> {
215 let Inst{15-10} = 0x11;
220 class ADDIUR1SP_FM_MM16 {
226 let Inst{15-10} = 0x1b;
232 class BRKSDBBP16_FM_MM<bits<6> op> {
236 let Inst{15-10} = 0x11;
238 let Inst{3-0} = code_;
241 class BEQNEZ_FM_MM16<bits<6> op> {
247 let Inst{15-10} = op;
249 let Inst{6-0} = offset;
257 let Inst{15-10} = 0x33;
258 let Inst{9-0} = offset;
261 class MOVEP_FM_MM16 {
268 let Inst{15-10} = 0x21;
269 let Inst{9-7} = dst_regs;
275 //===----------------------------------------------------------------------===//
276 // MicroMIPS 32-bit Instruction Formats
277 //===----------------------------------------------------------------------===//
280 string Arch = "micromips";
283 class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {
290 let Inst{31-26} = op;
291 let Inst{25-21} = rt;
292 let Inst{20-16} = rs;
293 let Inst{15-11} = rd;
295 let Inst{9-0} = funct;
298 class ADDI_FM_MM<bits<6> op> : MMArch {
305 let Inst{31-26} = op;
306 let Inst{25-21} = rt;
307 let Inst{20-16} = rs;
308 let Inst{15-0} = imm16;
311 class SLTI_FM_MM<bits<6> op> : MMArch {
318 let Inst{31-26} = op;
319 let Inst{25-21} = rt;
320 let Inst{20-16} = rs;
321 let Inst{15-0} = imm16;
324 class LUI_FM_MM : MMArch {
330 let Inst{31-26} = 0x10;
331 let Inst{25-21} = 0xd;
332 let Inst{20-16} = rt;
333 let Inst{15-0} = imm16;
336 class MULT_FM_MM<bits<10> funct> : MMArch {
342 let Inst{31-26} = 0x00;
343 let Inst{25-21} = rt;
344 let Inst{20-16} = rs;
345 let Inst{15-6} = funct;
346 let Inst{5-0} = 0x3c;
349 class SRA_FM_MM<bits<10> funct, bit rotate> : MMArch {
357 let Inst{25-21} = rd;
358 let Inst{20-16} = rt;
359 let Inst{15-11} = shamt;
360 let Inst{10} = rotate;
361 let Inst{9-0} = funct;
364 class SRLV_FM_MM<bits<10> funct, bit rotate> : MMArch {
372 let Inst{25-21} = rt;
373 let Inst{20-16} = rs;
374 let Inst{15-11} = rd;
375 let Inst{10} = rotate;
376 let Inst{9-0} = funct;
379 class LW_FM_MM<bits<6> op> : MMArch {
382 bits<5> base = addr{20-16};
383 bits<16> offset = addr{15-0};
387 let Inst{31-26} = op;
388 let Inst{25-21} = rt;
389 let Inst{20-16} = base;
390 let Inst{15-0} = offset;
393 class POOL32C_LHUE_FM_MM<bits<6> op, bits<4> fmt, bits<3> funct> : MMArch {
396 bits<5> base = addr{20-16};
397 bits<9> offset = addr{8-0};
401 let Inst{31-26} = op;
402 let Inst{25-21} = rt;
403 let Inst{20-16} = base;
404 let Inst{15-12} = fmt;
405 let Inst{11-9} = funct;
406 let Inst{8-0} = offset;
409 class LWL_FM_MM<bits<4> funct> {
415 let Inst{31-26} = 0x18;
416 let Inst{25-21} = rt;
417 let Inst{20-16} = addr{20-16};
418 let Inst{15-12} = funct;
419 let Inst{11-0} = addr{11-0};
422 class POOL32C_STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
425 bits<5> base = addr{20-16};
426 bits<9> offset = addr{8-0};
430 let Inst{31-26} = 0x18;
431 let Inst{25-21} = rt;
432 let Inst{20-16} = base;
433 let Inst{15-12} = type;
434 let Inst{11-9} = funct;
435 let Inst{8-0} = offset;
438 class CMov_F_I_FM_MM<bits<7> func> : MMArch {
445 let Inst{31-26} = 0x15;
446 let Inst{25-21} = rd;
447 let Inst{20-16} = rs;
448 let Inst{15-13} = fcc;
449 let Inst{12-6} = func;
450 let Inst{5-0} = 0x3b;
453 class MTLO_FM_MM<bits<10> funct> : MMArch {
458 let Inst{31-26} = 0x00;
459 let Inst{25-21} = 0x00;
460 let Inst{20-16} = rs;
461 let Inst{15-6} = funct;
462 let Inst{5-0} = 0x3c;
465 class MFLO_FM_MM<bits<10> funct> : MMArch {
470 let Inst{31-26} = 0x00;
471 let Inst{25-21} = 0x00;
472 let Inst{20-16} = rd;
473 let Inst{15-6} = funct;
474 let Inst{5-0} = 0x3c;
477 class CLO_FM_MM<bits<10> funct> : MMArch {
483 let Inst{31-26} = 0x00;
484 let Inst{25-21} = rd;
485 let Inst{20-16} = rs;
486 let Inst{15-6} = funct;
487 let Inst{5-0} = 0x3c;
490 class SEB_FM_MM<bits<10> funct> : MMArch {
496 let Inst{31-26} = 0x00;
497 let Inst{25-21} = rd;
498 let Inst{20-16} = rt;
499 let Inst{15-6} = funct;
500 let Inst{5-0} = 0x3c;
503 class EXT_FM_MM<bits<6> funct> : MMArch {
511 let Inst{31-26} = 0x00;
512 let Inst{25-21} = rt;
513 let Inst{20-16} = rs;
514 let Inst{15-11} = size;
515 let Inst{10-6} = pos;
516 let Inst{5-0} = funct;
519 class J_FM_MM<bits<6> op> : MMArch {
524 let Inst{31-26} = op;
525 let Inst{25-0} = target;
528 class JR_FM_MM<bits<8> funct> : MMArch {
533 let Inst{31-21} = 0x00;
534 let Inst{20-16} = rs;
535 let Inst{15-14} = 0x0;
536 let Inst{13-6} = funct;
537 let Inst{5-0} = 0x3c;
540 class JALR_FM_MM<bits<10> funct> {
546 let Inst{31-26} = 0x00;
547 let Inst{25-21} = rd;
548 let Inst{20-16} = rs;
549 let Inst{15-6} = funct;
550 let Inst{5-0} = 0x3c;
553 class BEQ_FM_MM<bits<6> op> : MMArch {
560 let Inst{31-26} = op;
561 let Inst{25-21} = rt;
562 let Inst{20-16} = rs;
563 let Inst{15-0} = offset;
566 class BGEZ_FM_MM<bits<5> funct> : MMArch {
572 let Inst{31-26} = 0x10;
573 let Inst{25-21} = funct;
574 let Inst{20-16} = rs;
575 let Inst{15-0} = offset;
578 class BGEZAL_FM_MM<bits<5> funct> : MMArch {
584 let Inst{31-26} = 0x10;
585 let Inst{25-21} = funct;
586 let Inst{20-16} = rs;
587 let Inst{15-0} = offset;
590 class SYNC_FM_MM : MMArch {
595 let Inst{31-26} = 0x00;
596 let Inst{25-21} = 0x0;
597 let Inst{20-16} = stype;
598 let Inst{15-6} = 0x1ad;
599 let Inst{5-0} = 0x3c;
602 class BRK_FM_MM : MMArch {
606 let Inst{31-26} = 0x0;
607 let Inst{25-16} = code_1;
608 let Inst{15-6} = code_2;
609 let Inst{5-0} = 0x07;
612 class SYS_FM_MM : MMArch {
615 let Inst{31-26} = 0x0;
616 let Inst{25-16} = code_;
617 let Inst{15-6} = 0x22d;
618 let Inst{5-0} = 0x3c;
625 let Inst{31-26} = 0x00;
626 let Inst{25-16} = code_;
627 let Inst{15-6} = 0x24d;
628 let Inst{5-0} = 0x3c;
631 class ER_FM_MM<bits<10> funct> : MMArch {
634 let Inst{31-26} = 0x00;
635 let Inst{25-16} = 0x00;
636 let Inst{15-6} = funct;
637 let Inst{5-0} = 0x3c;
640 class EI_FM_MM<bits<10> funct> : MMArch {
644 let Inst{31-26} = 0x00;
645 let Inst{25-21} = 0x00;
646 let Inst{20-16} = rt;
647 let Inst{15-6} = funct;
648 let Inst{5-0} = 0x3c;
651 class TEQ_FM_MM<bits<6> funct> : MMArch {
658 let Inst{31-26} = 0x00;
659 let Inst{25-21} = rt;
660 let Inst{20-16} = rs;
661 let Inst{15-12} = code_;
662 let Inst{11-6} = funct;
663 let Inst{5-0} = 0x3c;
666 class TEQI_FM_MM<bits<5> funct> : MMArch {
672 let Inst{31-26} = 0x10;
673 let Inst{25-21} = funct;
674 let Inst{20-16} = rs;
675 let Inst{15-0} = imm16;
678 class LL_FM_MM<bits<4> funct> : MMArch {
684 let Inst{31-26} = 0x18;
685 let Inst{25-21} = rt;
686 let Inst{20-16} = addr{20-16};
687 let Inst{15-12} = funct;
688 let Inst{11-0} = addr{11-0};
691 class LLE_FM_MM<bits<4> funct> {
694 bits<5> base = addr{20-16};
695 bits<9> offset = addr{8-0};
699 let Inst{31-26} = 0x18;
700 let Inst{25-21} = rt;
701 let Inst{20-16} = base;
702 let Inst{15-12} = funct;
703 let Inst{11-9} = 0x6;
704 let Inst{8-0} = offset;
707 class ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
714 let Inst{31-26} = 0x15;
715 let Inst{25-21} = ft;
716 let Inst{20-16} = fs;
717 let Inst{15-11} = fd;
720 let Inst{7-0} = funct;
722 list<dag> Pattern = [];
725 class LWXC1_FM_MM<bits<9> funct> : MMArch {
732 let Inst{31-26} = 0x15;
733 let Inst{25-21} = index;
734 let Inst{20-16} = base;
735 let Inst{15-11} = fd;
736 let Inst{10-9} = 0x0;
737 let Inst{8-0} = funct;
740 class SWXC1_FM_MM<bits<9> funct> : MMArch {
747 let Inst{31-26} = 0x15;
748 let Inst{25-21} = index;
749 let Inst{20-16} = base;
750 let Inst{15-11} = fs;
751 let Inst{10-9} = 0x0;
752 let Inst{8-0} = funct;
755 class CEQS_FM_MM<bits<2> fmt> : MMArch {
762 let Inst{31-26} = 0x15;
763 let Inst{25-21} = ft;
764 let Inst{20-16} = fs;
765 let Inst{15-13} = 0x0; // cc
767 let Inst{11-10} = fmt;
768 let Inst{9-6} = cond;
769 let Inst{5-0} = 0x3c;
772 class BC1F_FM_MM<bits<5> tf> : MMArch {
777 let Inst{31-26} = 0x10;
778 let Inst{25-21} = tf;
779 let Inst{20-18} = 0x0; // cc
780 let Inst{17-16} = 0x0;
781 let Inst{15-0} = offset;
784 class ROUND_W_FM_MM<bits<1> fmt, bits<8> funct> : MMArch {
790 let Inst{31-26} = 0x15;
791 let Inst{25-21} = fd;
792 let Inst{20-16} = fs;
795 let Inst{13-6} = funct;
796 let Inst{5-0} = 0x3b;
799 class ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
805 let Inst{31-26} = 0x15;
806 let Inst{25-21} = fd;
807 let Inst{20-16} = fs;
809 let Inst{14-13} = fmt;
810 let Inst{12-6} = funct;
811 let Inst{5-0} = 0x3b;
814 class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
820 let Inst{31-26} = 0x15;
821 let Inst{25-21} = fd;
822 let Inst{20-16} = fs;
823 let Inst{15-13} = 0x0; //cc
824 let Inst{12-11} = 0x0;
825 let Inst{10-9} = fmt;
826 let Inst{8-0} = func;
829 class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
836 let Inst{31-26} = 0x15;
837 let Inst{25-21} = rt;
838 let Inst{20-16} = fs;
839 let Inst{15-11} = fd;
841 let Inst{7-0} = funct;
844 class MFC1_FM_MM<bits<8> funct> : MMArch {
850 let Inst{31-26} = 0x15;
851 let Inst{25-21} = rt;
852 let Inst{20-16} = fs;
853 let Inst{15-14} = 0x0;
854 let Inst{13-6} = funct;
855 let Inst{5-0} = 0x3b;
858 class MADDS_FM_MM<bits<6> funct>: MMArch {
866 let Inst{31-26} = 0x15;
867 let Inst{25-21} = ft;
868 let Inst{20-16} = fs;
869 let Inst{15-11} = fd;
871 let Inst{5-0} = funct;
874 class COMPACT_BRANCH_FM_MM<bits<5> funct> {
880 let Inst{31-26} = 0x10;
881 let Inst{25-21} = funct;
882 let Inst{20-16} = rs;
883 let Inst{15-0} = offset;
886 class COP0_TLB_FM_MM<bits<10> op> : MMArch {
889 let Inst{31-26} = 0x0;
890 let Inst{25-16} = 0x0;
892 let Inst{5-0} = 0x3c;
895 class SDBBP_FM_MM : MMArch {
900 let Inst{31-26} = 0x0;
901 let Inst{25-16} = code_;
902 let Inst{15-6} = 0x36d;
903 let Inst{5-0} = 0x3c;
906 class RDHWR_FM_MM : MMArch {
912 let Inst{31-26} = 0x0;
913 let Inst{25-21} = rt;
914 let Inst{20-16} = rd;
915 let Inst{15-6} = 0x1ac;
916 let Inst{5-0} = 0x3c;
919 class LWXS_FM_MM<bits<10> funct> {
926 let Inst{31-26} = 0x0;
927 let Inst{25-21} = index;
928 let Inst{20-16} = base;
929 let Inst{15-11} = rd;
931 let Inst{9-0} = funct;
934 class LWM_FM_MM<bits<4> funct> : MMArch {
940 let Inst{31-26} = 0x8;
941 let Inst{25-21} = rt;
942 let Inst{20-16} = addr{20-16};
943 let Inst{15-12} = funct;
944 let Inst{11-0} = addr{11-0};
947 class LWM_FM_MM16<bits<4> funct> : MMArch, PredicateControl {
953 let Inst{15-10} = 0x11;
954 let Inst{9-6} = funct;
956 let Inst{3-0} = addr;
959 class CACHE_PREF_FM_MM<bits<6> op, bits<4> funct> : MMArch {
962 bits<5> base = addr{20-16};
963 bits<12> offset = addr{11-0};
967 let Inst{31-26} = op;
968 let Inst{25-21} = hint;
969 let Inst{20-16} = base;
970 let Inst{15-12} = funct;
971 let Inst{11-0} = offset;
974 class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
977 bits<5> base = addr{20-16};
978 bits<9> offset = addr{8-0};
982 let Inst{31-26} = op;
983 let Inst{25-21} = hint;
984 let Inst{20-16} = base;
985 let Inst{15-12} = 0xA;
986 let Inst{11-9} = funct;
987 let Inst{8-0} = offset;
990 class POOL32F_PREFX_FM_MM<bits<6> op, bits<9> funct> : MMArch {
997 let Inst{31-26} = op;
998 let Inst{25-21} = index;
999 let Inst{20-16} = base;
1000 let Inst{15-11} = hint;
1001 let Inst{10-9} = 0x0;
1002 let Inst{8-0} = funct;
1005 class BARRIER_FM_MM<bits<5> op> : MMArch {
1008 let Inst{31-26} = 0x0;
1009 let Inst{25-21} = 0x0;
1010 let Inst{20-16} = 0x0;
1011 let Inst{15-11} = op;
1012 let Inst{10-6} = 0x0;
1013 let Inst{5-0} = 0x0;
1016 class ADDIUPC_FM_MM {
1022 let Inst{31-26} = 0x1e;
1023 let Inst{25-23} = rs;
1024 let Inst{22-0} = imm;