1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
127 BuildMI(MBB, MI, DL, get(Mips::NOP));
131 copyPhysReg(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator I, DebugLoc DL,
133 unsigned DestReg, unsigned SrcReg,
134 bool KillSrc) const {
135 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
136 bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg);
138 // CPU-CPU is the most common.
139 if (DestCPU && SrcCPU) {
140 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
141 .addReg(SrcReg, getKillRegState(KillSrc));
145 // Copy to CPU from other registers.
147 if (Mips::CCRRegClass.contains(SrcReg))
148 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
149 .addReg(SrcReg, getKillRegState(KillSrc));
150 else if (Mips::FGR32RegClass.contains(SrcReg))
151 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
152 .addReg(SrcReg, getKillRegState(KillSrc));
153 else if (SrcReg == Mips::HI)
154 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
155 else if (SrcReg == Mips::LO)
156 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
158 llvm_unreachable("Copy to CPU from invalid register");
162 // Copy to other registers from CPU.
164 if (Mips::CCRRegClass.contains(DestReg))
165 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
166 .addReg(SrcReg, getKillRegState(KillSrc));
167 else if (Mips::FGR32RegClass.contains(DestReg))
168 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
169 .addReg(SrcReg, getKillRegState(KillSrc));
170 else if (DestReg == Mips::HI)
171 BuildMI(MBB, I, DL, get(Mips::MTHI))
172 .addReg(SrcReg, getKillRegState(KillSrc));
173 else if (DestReg == Mips::LO)
174 BuildMI(MBB, I, DL, get(Mips::MTLO))
175 .addReg(SrcReg, getKillRegState(KillSrc));
177 llvm_unreachable("Copy from CPU to invalid register");
181 if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
182 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
183 .addReg(SrcReg, getKillRegState(KillSrc));
187 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
188 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
189 .addReg(SrcReg, getKillRegState(KillSrc));
193 if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
194 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
195 .addReg(SrcReg, getKillRegState(KillSrc));
198 llvm_unreachable("Cannot copy registers");
202 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
203 unsigned SrcReg, bool isKill, int FI,
204 const TargetRegisterClass *RC,
205 const TargetRegisterInfo *TRI) const {
207 if (I != MBB.end()) DL = I->getDebugLoc();
209 if (RC == Mips::CPURegsRegisterClass)
210 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
211 .addImm(0).addFrameIndex(FI);
212 else if (RC == Mips::FGR32RegisterClass)
213 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
214 .addImm(0).addFrameIndex(FI);
215 else if (RC == Mips::AFGR64RegisterClass) {
216 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
217 BuildMI(MBB, I, DL, get(Mips::SDC1))
218 .addReg(SrcReg, getKillRegState(isKill))
219 .addImm(0).addFrameIndex(FI);
221 const TargetRegisterInfo *TRI =
222 MBB.getParent()->getTarget().getRegisterInfo();
223 const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
224 BuildMI(MBB, I, DL, get(Mips::SWC1))
225 .addReg(SubSet[0], getKillRegState(isKill))
226 .addImm(0).addFrameIndex(FI);
227 BuildMI(MBB, I, DL, get(Mips::SWC1))
228 .addReg(SubSet[1], getKillRegState(isKill))
229 .addImm(4).addFrameIndex(FI);
232 llvm_unreachable("Register class not handled!");
236 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
237 unsigned DestReg, int FI,
238 const TargetRegisterClass *RC,
239 const TargetRegisterInfo *TRI) const
242 if (I != MBB.end()) DL = I->getDebugLoc();
244 if (RC == Mips::CPURegsRegisterClass)
245 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
246 else if (RC == Mips::FGR32RegisterClass)
247 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
248 else if (RC == Mips::AFGR64RegisterClass) {
249 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
250 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
252 const TargetRegisterInfo *TRI =
253 MBB.getParent()->getTarget().getRegisterInfo();
254 const unsigned *SubSet = TRI->getSubRegisters(DestReg);
255 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
256 .addImm(0).addFrameIndex(FI);
257 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
258 .addImm(4).addFrameIndex(FI);
261 llvm_unreachable("Register class not handled!");
264 //===----------------------------------------------------------------------===//
266 //===----------------------------------------------------------------------===//
268 /// GetCondFromBranchOpc - Return the Mips CC that matches
269 /// the correspondent Branch instruction opcode.
270 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
273 default: return Mips::COND_INVALID;
274 case Mips::BEQ : return Mips::COND_E;
275 case Mips::BNE : return Mips::COND_NE;
276 case Mips::BGTZ : return Mips::COND_GZ;
277 case Mips::BGEZ : return Mips::COND_GEZ;
278 case Mips::BLTZ : return Mips::COND_LZ;
279 case Mips::BLEZ : return Mips::COND_LEZ;
281 // We dont do fp branch analysis yet!
283 case Mips::BC1F : return Mips::COND_INVALID;
287 /// GetCondBranchFromCond - Return the Branch instruction
288 /// opcode that matches the cc.
289 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
292 default: llvm_unreachable("Illegal condition code!");
293 case Mips::COND_E : return Mips::BEQ;
294 case Mips::COND_NE : return Mips::BNE;
295 case Mips::COND_GZ : return Mips::BGTZ;
296 case Mips::COND_GEZ : return Mips::BGEZ;
297 case Mips::COND_LZ : return Mips::BLTZ;
298 case Mips::COND_LEZ : return Mips::BLEZ;
303 case Mips::FCOND_UEQ:
304 case Mips::FCOND_OLT:
305 case Mips::FCOND_ULT:
306 case Mips::FCOND_OLE:
307 case Mips::FCOND_ULE:
309 case Mips::FCOND_NGLE:
310 case Mips::FCOND_SEQ:
311 case Mips::FCOND_NGL:
313 case Mips::FCOND_NGE:
315 case Mips::FCOND_NGT: return Mips::BC1T;
319 case Mips::FCOND_NEQ:
320 case Mips::FCOND_OGL:
321 case Mips::FCOND_UGE:
322 case Mips::FCOND_OGE:
323 case Mips::FCOND_UGT:
324 case Mips::FCOND_OGT:
326 case Mips::FCOND_GLE:
327 case Mips::FCOND_SNE:
329 case Mips::FCOND_NLT:
331 case Mips::FCOND_NLE:
332 case Mips::FCOND_GT: return Mips::BC1F;
336 /// GetOppositeBranchCondition - Return the inverse of the specified
337 /// condition, e.g. turning COND_E to COND_NE.
338 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
341 default: llvm_unreachable("Illegal condition code!");
342 case Mips::COND_E : return Mips::COND_NE;
343 case Mips::COND_NE : return Mips::COND_E;
344 case Mips::COND_GZ : return Mips::COND_LEZ;
345 case Mips::COND_GEZ : return Mips::COND_LZ;
346 case Mips::COND_LZ : return Mips::COND_GEZ;
347 case Mips::COND_LEZ : return Mips::COND_GZ;
348 case Mips::FCOND_F : return Mips::FCOND_T;
349 case Mips::FCOND_UN : return Mips::FCOND_OR;
350 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
351 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
352 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
353 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
354 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
355 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
356 case Mips::FCOND_SF: return Mips::FCOND_ST;
357 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
358 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
359 case Mips::FCOND_NGL: return Mips::FCOND_GL;
360 case Mips::FCOND_LT: return Mips::FCOND_NLT;
361 case Mips::FCOND_NGE: return Mips::FCOND_GE;
362 case Mips::FCOND_LE: return Mips::FCOND_NLE;
363 case Mips::FCOND_NGT: return Mips::FCOND_GT;
367 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
368 MachineBasicBlock *&TBB,
369 MachineBasicBlock *&FBB,
370 SmallVectorImpl<MachineOperand> &Cond,
371 bool AllowModify) const
373 // If the block has no terminators, it just falls into the block after it.
374 MachineBasicBlock::iterator I = MBB.end();
375 if (I == MBB.begin())
378 while (I->isDebugValue()) {
379 if (I == MBB.begin())
383 if (!isUnpredicatedTerminator(I))
386 // Get the last instruction in the block.
387 MachineInstr *LastInst = I;
389 // If there is only one terminator instruction, process it.
390 unsigned LastOpc = LastInst->getOpcode();
391 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
392 if (!LastInst->getDesc().isBranch())
395 // Unconditional branch
396 if (LastOpc == Mips::J) {
397 TBB = LastInst->getOperand(0).getMBB();
401 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
402 if (BranchCode == Mips::COND_INVALID)
403 return true; // Can't handle indirect branch.
405 // Conditional branch
406 // Block ends with fall-through condbranch.
407 if (LastOpc != Mips::COND_INVALID) {
408 int LastNumOp = LastInst->getNumOperands();
410 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
411 Cond.push_back(MachineOperand::CreateImm(BranchCode));
413 for (int i=0; i<LastNumOp-1; i++) {
414 Cond.push_back(LastInst->getOperand(i));
421 // Get the instruction before it if it is a terminator.
422 MachineInstr *SecondLastInst = I;
424 // If there are three terminators, we don't know what sort of block this is.
425 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
428 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
429 unsigned SecondLastOpc = SecondLastInst->getOpcode();
430 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
432 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
433 int SecondNumOp = SecondLastInst->getNumOperands();
435 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
436 Cond.push_back(MachineOperand::CreateImm(BranchCode));
438 for (int i=0; i<SecondNumOp-1; i++) {
439 Cond.push_back(SecondLastInst->getOperand(i));
442 FBB = LastInst->getOperand(0).getMBB();
446 // If the block ends with two unconditional branches, handle it. The last
447 // one is not executed, so remove it.
448 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
449 TBB = SecondLastInst->getOperand(0).getMBB();
452 I->eraseFromParent();
456 // Otherwise, can't handle this.
460 unsigned MipsInstrInfo::
461 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
462 MachineBasicBlock *FBB,
463 const SmallVectorImpl<MachineOperand> &Cond,
465 // Shouldn't be a fall through.
466 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
467 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
468 "Mips branch conditions can have two|three components!");
470 if (FBB == 0) { // One way branch.
472 // Unconditional branch?
473 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
475 // Conditional branch.
476 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
477 const TargetInstrDesc &TID = get(Opc);
479 if (TID.getNumOperands() == 3)
480 BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
481 .addReg(Cond[2].getReg())
484 BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
491 // Two-way Conditional branch.
492 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
493 const TargetInstrDesc &TID = get(Opc);
495 if (TID.getNumOperands() == 3)
496 BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
499 BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB);
501 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
505 unsigned MipsInstrInfo::
506 RemoveBranch(MachineBasicBlock &MBB) const
508 MachineBasicBlock::iterator I = MBB.end();
509 if (I == MBB.begin()) return 0;
511 while (I->isDebugValue()) {
512 if (I == MBB.begin())
516 if (I->getOpcode() != Mips::J &&
517 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
520 // Remove the branch.
521 I->eraseFromParent();
525 if (I == MBB.begin()) return 1;
527 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
530 // Remove the branch.
531 I->eraseFromParent();
535 /// ReverseBranchCondition - Return the inverse opcode of the
536 /// specified Branch instruction.
538 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
540 assert( (Cond.size() == 3 || Cond.size() == 2) &&
541 "Invalid Mips branch condition!");
542 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
546 /// getGlobalBaseReg - Return a virtual register initialized with the
547 /// the global base register value. Output instructions required to
548 /// initialize the register in the function entry block, if necessary.
550 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
551 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
552 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
553 if (GlobalBaseReg != 0)
554 return GlobalBaseReg;
556 // Insert the set of GlobalBaseReg into the first MBB of the function
557 MachineBasicBlock &FirstMBB = MF->front();
558 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
559 MachineRegisterInfo &RegInfo = MF->getRegInfo();
560 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
562 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
563 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
564 GlobalBaseReg).addReg(Mips::GP);
565 RegInfo.addLiveIn(Mips::GP);
567 MipsFI->setGlobalBaseReg(GlobalBaseReg);
568 return GlobalBaseReg;