1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
37 static unsigned RRegs[32] = {
38 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
39 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
40 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
41 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45 PPC::R28, PPC::R29, PPC::R30, PPC::R31
47 static unsigned RRegsNoR0[32] = {
49 PPC::R1, PPC::R2, PPC::R3,
50 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
51 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
52 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56 PPC::R28, PPC::R29, PPC::R30, PPC::R31
58 static unsigned XRegs[32] = {
59 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
60 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
61 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
62 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66 PPC::X28, PPC::X29, PPC::X30, PPC::X31
68 static unsigned XRegsNoX0[32] = {
70 PPC::X1, PPC::X2, PPC::X3,
71 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
72 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
73 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77 PPC::X28, PPC::X29, PPC::X30, PPC::X31
79 static unsigned FRegs[32] = {
80 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
81 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
82 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
83 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87 PPC::F28, PPC::F29, PPC::F30, PPC::F31
89 static unsigned VRegs[32] = {
90 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
91 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
92 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
93 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97 PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static unsigned VSRegs[64] = {
100 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
101 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
102 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
103 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
109 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
110 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
111 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
112 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
118 static unsigned VSFRegs[64] = {
119 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
120 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
122 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
128 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
129 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
130 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
131 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
137 static unsigned CRBITRegs[32] = {
138 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
147 static unsigned CRRegs[8] = {
148 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
152 // Evaluate an expression containing condition register
153 // or condition register field symbols. Returns positive
154 // value on success, or -1 on error.
156 EvaluateCRExpr(const MCExpr *E) {
157 switch (E->getKind()) {
161 case MCExpr::Constant: {
162 int64_t Res = cast<MCConstantExpr>(E)->getValue();
163 return Res < 0 ? -1 : Res;
166 case MCExpr::SymbolRef: {
167 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168 StringRef Name = SRE->getSymbol().getName();
170 if (Name == "lt") return 0;
171 if (Name == "gt") return 1;
172 if (Name == "eq") return 2;
173 if (Name == "so") return 3;
174 if (Name == "un") return 3;
176 if (Name == "cr0") return 0;
177 if (Name == "cr1") return 1;
178 if (Name == "cr2") return 2;
179 if (Name == "cr3") return 3;
180 if (Name == "cr4") return 4;
181 if (Name == "cr5") return 5;
182 if (Name == "cr6") return 6;
183 if (Name == "cr7") return 7;
191 case MCExpr::Binary: {
192 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
197 if (LHSVal < 0 || RHSVal < 0)
200 switch (BE->getOpcode()) {
202 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
206 return Res < 0 ? -1 : Res;
210 llvm_unreachable("Invalid expression kind!");
215 class PPCAsmParser : public MCTargetAsmParser {
216 MCSubtargetInfo &STI;
218 const MCInstrInfo &MII;
222 MCAsmParser &getParser() const { return Parser; }
223 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
225 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
226 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
228 bool isPPC64() const { return IsPPC64; }
229 bool isDarwin() const { return IsDarwin; }
231 bool MatchRegisterName(const AsmToken &Tok,
232 unsigned &RegNo, int64_t &IntVal);
234 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
236 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
237 PPCMCExpr::VariantKind &Variant);
238 const MCExpr *FixupVariantKind(const MCExpr *E);
239 bool ParseExpression(const MCExpr *&EVal);
240 bool ParseDarwinExpression(const MCExpr *&EVal);
242 bool ParseOperand(OperandVector &Operands);
244 bool ParseDirectiveWord(unsigned Size, SMLoc L);
245 bool ParseDirectiveTC(unsigned Size, SMLoc L);
246 bool ParseDirectiveMachine(SMLoc L);
247 bool ParseDarwinDirectiveMachine(SMLoc L);
248 bool ParseDirectiveAbiVersion(SMLoc L);
249 bool ParseDirectiveLocalEntry(SMLoc L);
251 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
252 OperandVector &Operands, MCStreamer &Out,
254 bool MatchingInlineAsm) override;
256 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
258 /// @name Auto-generated Match Functions
261 #define GET_ASSEMBLER_HEADER
262 #include "PPCGenAsmMatcher.inc"
268 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
269 const MCInstrInfo &_MII,
270 const MCTargetOptions &Options)
271 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
272 // Check for 64-bit vs. 32-bit pointer mode.
273 Triple TheTriple(STI.getTargetTriple());
274 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
275 TheTriple.getArch() == Triple::ppc64le);
276 IsDarwin = TheTriple.isMacOSX();
277 // Initialize the set of available features.
278 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
281 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
282 SMLoc NameLoc, OperandVector &Operands) override;
284 bool ParseDirective(AsmToken DirectiveID) override;
286 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
287 unsigned Kind) override;
289 const MCExpr *applyModifierToExpr(const MCExpr *E,
290 MCSymbolRefExpr::VariantKind,
291 MCContext &Ctx) override;
294 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
296 struct PPCOperand : public MCParsedAsmOperand {
304 SMLoc StartLoc, EndLoc;
318 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
322 const MCSymbolRefExpr *Sym;
329 struct TLSRegOp TLSReg;
332 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
334 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
336 StartLoc = o.StartLoc;
355 /// getStartLoc - Get the location of the first token of this operand.
356 SMLoc getStartLoc() const override { return StartLoc; }
358 /// getEndLoc - Get the location of the last token of this operand.
359 SMLoc getEndLoc() const override { return EndLoc; }
361 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
362 bool isPPC64() const { return IsPPC64; }
364 int64_t getImm() const {
365 assert(Kind == Immediate && "Invalid access!");
369 const MCExpr *getExpr() const {
370 assert(Kind == Expression && "Invalid access!");
374 int64_t getExprCRVal() const {
375 assert(Kind == Expression && "Invalid access!");
379 const MCExpr *getTLSReg() const {
380 assert(Kind == TLSRegister && "Invalid access!");
384 unsigned getReg() const override {
385 assert(isRegNumber() && "Invalid access!");
386 return (unsigned) Imm.Val;
389 unsigned getVSReg() const {
390 assert(isVSRegNumber() && "Invalid access!");
391 return (unsigned) Imm.Val;
394 unsigned getCCReg() const {
395 assert(isCCRegNumber() && "Invalid access!");
396 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
399 unsigned getCRBit() const {
400 assert(isCRBitNumber() && "Invalid access!");
401 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
404 unsigned getCRBitMask() const {
405 assert(isCRBitMask() && "Invalid access!");
406 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
409 bool isToken() const override { return Kind == Token; }
410 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
411 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
412 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
413 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
414 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
415 bool isU16Imm() const { return Kind == Expression ||
416 (Kind == Immediate && isUInt<16>(getImm())); }
417 bool isS16Imm() const { return Kind == Expression ||
418 (Kind == Immediate && isInt<16>(getImm())); }
419 bool isS16ImmX4() const { return Kind == Expression ||
420 (Kind == Immediate && isInt<16>(getImm()) &&
421 (getImm() & 3) == 0); }
422 bool isS17Imm() const { return Kind == Expression ||
423 (Kind == Immediate && isInt<17>(getImm())); }
424 bool isTLSReg() const { return Kind == TLSRegister; }
425 bool isDirectBr() const { return Kind == Expression ||
426 (Kind == Immediate && isInt<26>(getImm()) &&
427 (getImm() & 3) == 0); }
428 bool isCondBr() const { return Kind == Expression ||
429 (Kind == Immediate && isInt<16>(getImm()) &&
430 (getImm() & 3) == 0); }
431 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
432 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
433 bool isCCRegNumber() const { return (Kind == Expression
434 && isUInt<3>(getExprCRVal())) ||
436 && isUInt<3>(getImm())); }
437 bool isCRBitNumber() const { return (Kind == Expression
438 && isUInt<5>(getExprCRVal())) ||
440 && isUInt<5>(getImm())); }
441 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
442 isPowerOf2_32(getImm()); }
443 bool isMem() const override { return false; }
444 bool isReg() const override { return false; }
446 void addRegOperands(MCInst &Inst, unsigned N) const {
447 llvm_unreachable("addRegOperands");
450 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
451 assert(N == 1 && "Invalid number of operands!");
452 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
455 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
456 assert(N == 1 && "Invalid number of operands!");
457 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
460 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
461 assert(N == 1 && "Invalid number of operands!");
462 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
465 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
467 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
470 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
472 addRegG8RCOperands(Inst, N);
474 addRegGPRCOperands(Inst, N);
477 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
479 addRegG8RCNoX0Operands(Inst, N);
481 addRegGPRCNoR0Operands(Inst, N);
484 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
485 assert(N == 1 && "Invalid number of operands!");
486 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
489 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
490 assert(N == 1 && "Invalid number of operands!");
491 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
494 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
495 assert(N == 1 && "Invalid number of operands!");
496 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
499 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
500 assert(N == 1 && "Invalid number of operands!");
501 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
504 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
505 assert(N == 1 && "Invalid number of operands!");
506 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
509 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
510 assert(N == 1 && "Invalid number of operands!");
511 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
514 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
515 assert(N == 1 && "Invalid number of operands!");
516 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
519 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
520 assert(N == 1 && "Invalid number of operands!");
521 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
524 void addImmOperands(MCInst &Inst, unsigned N) const {
525 assert(N == 1 && "Invalid number of operands!");
526 if (Kind == Immediate)
527 Inst.addOperand(MCOperand::CreateImm(getImm()));
529 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
532 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
533 assert(N == 1 && "Invalid number of operands!");
534 if (Kind == Immediate)
535 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
537 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
540 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
541 assert(N == 1 && "Invalid number of operands!");
542 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
545 StringRef getToken() const {
546 assert(Kind == Token && "Invalid access!");
547 return StringRef(Tok.Data, Tok.Length);
550 void print(raw_ostream &OS) const override;
552 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
554 auto Op = make_unique<PPCOperand>(Token);
555 Op->Tok.Data = Str.data();
556 Op->Tok.Length = Str.size();
559 Op->IsPPC64 = IsPPC64;
563 static std::unique_ptr<PPCOperand>
564 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
565 // Allocate extra memory for the string and copy it.
566 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
567 // deleter which will destroy them by simply using "delete", not correctly
568 // calling operator delete on this extra memory after calling the dtor
570 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
571 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
572 Op->Tok.Data = (const char *)(Op.get() + 1);
573 Op->Tok.Length = Str.size();
574 std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
577 Op->IsPPC64 = IsPPC64;
581 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
583 auto Op = make_unique<PPCOperand>(Immediate);
587 Op->IsPPC64 = IsPPC64;
591 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
592 SMLoc E, bool IsPPC64) {
593 auto Op = make_unique<PPCOperand>(Expression);
595 Op->Expr.CRVal = EvaluateCRExpr(Val);
598 Op->IsPPC64 = IsPPC64;
602 static std::unique_ptr<PPCOperand>
603 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
604 auto Op = make_unique<PPCOperand>(TLSRegister);
605 Op->TLSReg.Sym = Sym;
608 Op->IsPPC64 = IsPPC64;
612 static std::unique_ptr<PPCOperand>
613 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
614 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
615 return CreateImm(CE->getValue(), S, E, IsPPC64);
617 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
618 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
619 return CreateTLSReg(SRE, S, E, IsPPC64);
621 return CreateExpr(Val, S, E, IsPPC64);
625 } // end anonymous namespace.
627 void PPCOperand::print(raw_ostream &OS) const {
630 OS << "'" << getToken() << "'";
636 getExpr()->print(OS);
639 getTLSReg()->print(OS);
644 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
645 const OperandVector &Operands) {
646 int Opcode = Inst.getOpcode();
650 TmpInst.setOpcode(PPC::LA);
651 TmpInst.addOperand(Inst.getOperand(0));
652 TmpInst.addOperand(Inst.getOperand(2));
653 TmpInst.addOperand(Inst.getOperand(1));
659 int64_t N = Inst.getOperand(2).getImm();
660 TmpInst.setOpcode(PPC::ADDI);
661 TmpInst.addOperand(Inst.getOperand(0));
662 TmpInst.addOperand(Inst.getOperand(1));
663 TmpInst.addOperand(MCOperand::CreateImm(-N));
669 int64_t N = Inst.getOperand(2).getImm();
670 TmpInst.setOpcode(PPC::ADDIS);
671 TmpInst.addOperand(Inst.getOperand(0));
672 TmpInst.addOperand(Inst.getOperand(1));
673 TmpInst.addOperand(MCOperand::CreateImm(-N));
679 int64_t N = Inst.getOperand(2).getImm();
680 TmpInst.setOpcode(PPC::ADDIC);
681 TmpInst.addOperand(Inst.getOperand(0));
682 TmpInst.addOperand(Inst.getOperand(1));
683 TmpInst.addOperand(MCOperand::CreateImm(-N));
689 int64_t N = Inst.getOperand(2).getImm();
690 TmpInst.setOpcode(PPC::ADDICo);
691 TmpInst.addOperand(Inst.getOperand(0));
692 TmpInst.addOperand(Inst.getOperand(1));
693 TmpInst.addOperand(MCOperand::CreateImm(-N));
700 int64_t N = Inst.getOperand(2).getImm();
701 int64_t B = Inst.getOperand(3).getImm();
702 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
703 TmpInst.addOperand(Inst.getOperand(0));
704 TmpInst.addOperand(Inst.getOperand(1));
705 TmpInst.addOperand(MCOperand::CreateImm(B));
706 TmpInst.addOperand(MCOperand::CreateImm(0));
707 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
714 int64_t N = Inst.getOperand(2).getImm();
715 int64_t B = Inst.getOperand(3).getImm();
716 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
717 TmpInst.addOperand(Inst.getOperand(0));
718 TmpInst.addOperand(Inst.getOperand(1));
719 TmpInst.addOperand(MCOperand::CreateImm(B + N));
720 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
721 TmpInst.addOperand(MCOperand::CreateImm(31));
728 int64_t N = Inst.getOperand(2).getImm();
729 int64_t B = Inst.getOperand(3).getImm();
730 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
731 TmpInst.addOperand(Inst.getOperand(0));
732 TmpInst.addOperand(Inst.getOperand(0));
733 TmpInst.addOperand(Inst.getOperand(1));
734 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
735 TmpInst.addOperand(MCOperand::CreateImm(B));
736 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
743 int64_t N = Inst.getOperand(2).getImm();
744 int64_t B = Inst.getOperand(3).getImm();
745 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
746 TmpInst.addOperand(Inst.getOperand(0));
747 TmpInst.addOperand(Inst.getOperand(0));
748 TmpInst.addOperand(Inst.getOperand(1));
749 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
750 TmpInst.addOperand(MCOperand::CreateImm(B));
751 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
758 int64_t N = Inst.getOperand(2).getImm();
759 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
760 TmpInst.addOperand(Inst.getOperand(0));
761 TmpInst.addOperand(Inst.getOperand(1));
762 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
763 TmpInst.addOperand(MCOperand::CreateImm(0));
764 TmpInst.addOperand(MCOperand::CreateImm(31));
771 int64_t N = Inst.getOperand(2).getImm();
772 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
773 TmpInst.addOperand(Inst.getOperand(0));
774 TmpInst.addOperand(Inst.getOperand(1));
775 TmpInst.addOperand(MCOperand::CreateImm(N));
776 TmpInst.addOperand(MCOperand::CreateImm(0));
777 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
784 int64_t N = Inst.getOperand(2).getImm();
785 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
786 TmpInst.addOperand(Inst.getOperand(0));
787 TmpInst.addOperand(Inst.getOperand(1));
788 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
789 TmpInst.addOperand(MCOperand::CreateImm(N));
790 TmpInst.addOperand(MCOperand::CreateImm(31));
797 int64_t N = Inst.getOperand(2).getImm();
798 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
799 TmpInst.addOperand(Inst.getOperand(0));
800 TmpInst.addOperand(Inst.getOperand(1));
801 TmpInst.addOperand(MCOperand::CreateImm(0));
802 TmpInst.addOperand(MCOperand::CreateImm(0));
803 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
808 case PPC::CLRLSLWIo: {
810 int64_t B = Inst.getOperand(2).getImm();
811 int64_t N = Inst.getOperand(3).getImm();
812 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
813 TmpInst.addOperand(Inst.getOperand(0));
814 TmpInst.addOperand(Inst.getOperand(1));
815 TmpInst.addOperand(MCOperand::CreateImm(N));
816 TmpInst.addOperand(MCOperand::CreateImm(B - N));
817 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
824 int64_t N = Inst.getOperand(2).getImm();
825 int64_t B = Inst.getOperand(3).getImm();
826 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
827 TmpInst.addOperand(Inst.getOperand(0));
828 TmpInst.addOperand(Inst.getOperand(1));
829 TmpInst.addOperand(MCOperand::CreateImm(B));
830 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
837 int64_t N = Inst.getOperand(2).getImm();
838 int64_t B = Inst.getOperand(3).getImm();
839 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
840 TmpInst.addOperand(Inst.getOperand(0));
841 TmpInst.addOperand(Inst.getOperand(1));
842 TmpInst.addOperand(MCOperand::CreateImm(B + N));
843 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
850 int64_t N = Inst.getOperand(2).getImm();
851 int64_t B = Inst.getOperand(3).getImm();
852 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
853 TmpInst.addOperand(Inst.getOperand(0));
854 TmpInst.addOperand(Inst.getOperand(0));
855 TmpInst.addOperand(Inst.getOperand(1));
856 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
857 TmpInst.addOperand(MCOperand::CreateImm(B));
864 int64_t N = Inst.getOperand(2).getImm();
865 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
866 TmpInst.addOperand(Inst.getOperand(0));
867 TmpInst.addOperand(Inst.getOperand(1));
868 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
869 TmpInst.addOperand(MCOperand::CreateImm(0));
876 int64_t N = Inst.getOperand(2).getImm();
877 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
878 TmpInst.addOperand(Inst.getOperand(0));
879 TmpInst.addOperand(Inst.getOperand(1));
880 TmpInst.addOperand(MCOperand::CreateImm(N));
881 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
888 int64_t N = Inst.getOperand(2).getImm();
889 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
890 TmpInst.addOperand(Inst.getOperand(0));
891 TmpInst.addOperand(Inst.getOperand(1));
892 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
893 TmpInst.addOperand(MCOperand::CreateImm(N));
900 int64_t N = Inst.getOperand(2).getImm();
901 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
902 TmpInst.addOperand(Inst.getOperand(0));
903 TmpInst.addOperand(Inst.getOperand(1));
904 TmpInst.addOperand(MCOperand::CreateImm(0));
905 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
910 case PPC::CLRLSLDIo: {
912 int64_t B = Inst.getOperand(2).getImm();
913 int64_t N = Inst.getOperand(3).getImm();
914 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
915 TmpInst.addOperand(Inst.getOperand(0));
916 TmpInst.addOperand(Inst.getOperand(1));
917 TmpInst.addOperand(MCOperand::CreateImm(N));
918 TmpInst.addOperand(MCOperand::CreateImm(B - N));
925 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
926 OperandVector &Operands,
927 MCStreamer &Out, unsigned &ErrorInfo,
928 bool MatchingInlineAsm) {
931 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
934 // Post-process instructions (typically extended mnemonics)
935 ProcessInstruction(Inst, Operands);
937 Out.EmitInstruction(Inst, STI);
939 case Match_MissingFeature:
940 return Error(IDLoc, "instruction use requires an option to be enabled");
941 case Match_MnemonicFail:
942 return Error(IDLoc, "unrecognized instruction mnemonic");
943 case Match_InvalidOperand: {
944 SMLoc ErrorLoc = IDLoc;
945 if (ErrorInfo != ~0U) {
946 if (ErrorInfo >= Operands.size())
947 return Error(IDLoc, "too few operands for instruction");
949 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
950 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
953 return Error(ErrorLoc, "invalid operand for instruction");
957 llvm_unreachable("Implement any new match types added!");
961 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
962 if (Tok.is(AsmToken::Identifier)) {
963 StringRef Name = Tok.getString();
965 if (Name.equals_lower("lr")) {
966 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
969 } else if (Name.equals_lower("ctr")) {
970 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
973 } else if (Name.equals_lower("vrsave")) {
977 } else if (Name.startswith_lower("r") &&
978 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
979 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
981 } else if (Name.startswith_lower("f") &&
982 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
983 RegNo = FRegs[IntVal];
985 } else if (Name.startswith_lower("v") &&
986 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
987 RegNo = VRegs[IntVal];
989 } else if (Name.startswith_lower("cr") &&
990 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
991 RegNo = CRRegs[IntVal];
1000 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1001 const AsmToken &Tok = Parser.getTok();
1002 StartLoc = Tok.getLoc();
1003 EndLoc = Tok.getEndLoc();
1007 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1008 Parser.Lex(); // Eat identifier token.
1012 return Error(StartLoc, "invalid register name");
1015 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1016 /// the expression and check for VK_PPC_LO/HI/HA
1017 /// symbol variants. If all symbols with modifier use the same
1018 /// variant, return the corresponding PPCMCExpr::VariantKind,
1019 /// and a modified expression using the default symbol variant.
1020 /// Otherwise, return NULL.
1021 const MCExpr *PPCAsmParser::
1022 ExtractModifierFromExpr(const MCExpr *E,
1023 PPCMCExpr::VariantKind &Variant) {
1024 MCContext &Context = getParser().getContext();
1025 Variant = PPCMCExpr::VK_PPC_None;
1027 switch (E->getKind()) {
1028 case MCExpr::Target:
1029 case MCExpr::Constant:
1032 case MCExpr::SymbolRef: {
1033 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1035 switch (SRE->getKind()) {
1036 case MCSymbolRefExpr::VK_PPC_LO:
1037 Variant = PPCMCExpr::VK_PPC_LO;
1039 case MCSymbolRefExpr::VK_PPC_HI:
1040 Variant = PPCMCExpr::VK_PPC_HI;
1042 case MCSymbolRefExpr::VK_PPC_HA:
1043 Variant = PPCMCExpr::VK_PPC_HA;
1045 case MCSymbolRefExpr::VK_PPC_HIGHER:
1046 Variant = PPCMCExpr::VK_PPC_HIGHER;
1048 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1049 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1051 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1052 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1054 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1055 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1061 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1064 case MCExpr::Unary: {
1065 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1066 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1069 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1072 case MCExpr::Binary: {
1073 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1074 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1075 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1076 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1081 if (!LHS) LHS = BE->getLHS();
1082 if (!RHS) RHS = BE->getRHS();
1084 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1085 Variant = RHSVariant;
1086 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1087 Variant = LHSVariant;
1088 else if (LHSVariant == RHSVariant)
1089 Variant = LHSVariant;
1093 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1097 llvm_unreachable("Invalid expression kind!");
1100 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1101 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1102 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1103 /// FIXME: This is a hack.
1104 const MCExpr *PPCAsmParser::
1105 FixupVariantKind(const MCExpr *E) {
1106 MCContext &Context = getParser().getContext();
1108 switch (E->getKind()) {
1109 case MCExpr::Target:
1110 case MCExpr::Constant:
1113 case MCExpr::SymbolRef: {
1114 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1115 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1117 switch (SRE->getKind()) {
1118 case MCSymbolRefExpr::VK_TLSGD:
1119 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1121 case MCSymbolRefExpr::VK_TLSLD:
1122 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1127 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1130 case MCExpr::Unary: {
1131 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1132 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1133 if (Sub == UE->getSubExpr())
1135 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1138 case MCExpr::Binary: {
1139 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1140 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1141 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1142 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1144 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1148 llvm_unreachable("Invalid expression kind!");
1151 /// ParseExpression. This differs from the default "parseExpression" in that
1152 /// it handles modifiers.
1154 ParseExpression(const MCExpr *&EVal) {
1157 return ParseDarwinExpression(EVal);
1160 // Handle \code @l/@ha \endcode
1161 if (getParser().parseExpression(EVal))
1164 EVal = FixupVariantKind(EVal);
1166 PPCMCExpr::VariantKind Variant;
1167 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1169 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1174 /// ParseDarwinExpression. (MachO Platforms)
1175 /// This differs from the default "parseExpression" in that it handles detection
1176 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1177 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1178 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1179 /// for this to be done at a higher level.
1181 ParseDarwinExpression(const MCExpr *&EVal) {
1182 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1183 switch (getLexer().getKind()) {
1186 case AsmToken::Identifier:
1187 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1188 // something starting with any other char should be part of the
1189 // asm syntax. If handwritten asm includes an identifier like lo16,
1190 // then all bets are off - but no-one would do that, right?
1191 StringRef poss = Parser.getTok().getString();
1192 if (poss.equals_lower("lo16")) {
1193 Variant = PPCMCExpr::VK_PPC_LO;
1194 } else if (poss.equals_lower("hi16")) {
1195 Variant = PPCMCExpr::VK_PPC_HI;
1196 } else if (poss.equals_lower("ha16")) {
1197 Variant = PPCMCExpr::VK_PPC_HA;
1199 if (Variant != PPCMCExpr::VK_PPC_None) {
1200 Parser.Lex(); // Eat the xx16
1201 if (getLexer().isNot(AsmToken::LParen))
1202 return Error(Parser.getTok().getLoc(), "expected '('");
1203 Parser.Lex(); // Eat the '('
1208 if (getParser().parseExpression(EVal))
1211 if (Variant != PPCMCExpr::VK_PPC_None) {
1212 if (getLexer().isNot(AsmToken::RParen))
1213 return Error(Parser.getTok().getLoc(), "expected ')'");
1214 Parser.Lex(); // Eat the ')'
1215 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1221 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1223 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1224 SMLoc S = Parser.getTok().getLoc();
1225 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1228 // Attempt to parse the next token as an immediate
1229 switch (getLexer().getKind()) {
1230 // Special handling for register names. These are interpreted
1231 // as immediates corresponding to the register number.
1232 case AsmToken::Percent:
1233 Parser.Lex(); // Eat the '%'.
1236 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1237 Parser.Lex(); // Eat the identifier token.
1238 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1241 return Error(S, "invalid register name");
1243 case AsmToken::Identifier:
1244 // Note that non-register-name identifiers from the compiler will begin
1245 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1246 // identifiers like r31foo - so we fall through in the event that parsing
1247 // a register name fails.
1251 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1252 Parser.Lex(); // Eat the identifier token.
1253 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1257 // Fall-through to process non-register-name identifiers as expression.
1258 // All other expressions
1259 case AsmToken::LParen:
1260 case AsmToken::Plus:
1261 case AsmToken::Minus:
1262 case AsmToken::Integer:
1264 case AsmToken::Dollar:
1265 case AsmToken::Exclaim:
1266 case AsmToken::Tilde:
1267 if (!ParseExpression(EVal))
1271 return Error(S, "unknown operand");
1274 // Push the parsed operand into the list of operands
1275 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1277 // Check whether this is a TLS call expression
1278 bool TLSCall = false;
1279 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1280 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1282 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1283 const MCExpr *TLSSym;
1285 Parser.Lex(); // Eat the '('.
1286 S = Parser.getTok().getLoc();
1287 if (ParseExpression(TLSSym))
1288 return Error(S, "invalid TLS call expression");
1289 if (getLexer().isNot(AsmToken::RParen))
1290 return Error(Parser.getTok().getLoc(), "missing ')'");
1291 E = Parser.getTok().getLoc();
1292 Parser.Lex(); // Eat the ')'.
1294 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1297 // Otherwise, check for D-form memory operands
1298 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1299 Parser.Lex(); // Eat the '('.
1300 S = Parser.getTok().getLoc();
1303 switch (getLexer().getKind()) {
1304 case AsmToken::Percent:
1305 Parser.Lex(); // Eat the '%'.
1307 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1308 return Error(S, "invalid register name");
1309 Parser.Lex(); // Eat the identifier token.
1312 case AsmToken::Integer:
1314 if (getParser().parseAbsoluteExpression(IntVal) ||
1315 IntVal < 0 || IntVal > 31)
1316 return Error(S, "invalid register number");
1318 return Error(S, "unexpected integer value");
1322 case AsmToken::Identifier:
1325 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1326 Parser.Lex(); // Eat the identifier token.
1333 return Error(S, "invalid memory operand");
1336 if (getLexer().isNot(AsmToken::RParen))
1337 return Error(Parser.getTok().getLoc(), "missing ')'");
1338 E = Parser.getTok().getLoc();
1339 Parser.Lex(); // Eat the ')'.
1341 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1347 /// Parse an instruction mnemonic followed by its operands.
1348 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1349 SMLoc NameLoc, OperandVector &Operands) {
1350 // The first operand is the token for the instruction name.
1351 // If the next character is a '+' or '-', we need to add it to the
1352 // instruction name, to match what TableGen is doing.
1353 std::string NewOpcode;
1354 if (getLexer().is(AsmToken::Plus)) {
1360 if (getLexer().is(AsmToken::Minus)) {
1366 // If the instruction ends in a '.', we need to create a separate
1367 // token for it, to match what TableGen is doing.
1368 size_t Dot = Name.find('.');
1369 StringRef Mnemonic = Name.slice(0, Dot);
1370 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1372 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1374 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1375 if (Dot != StringRef::npos) {
1376 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1377 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1378 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1380 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1382 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1385 // If there are no more operands then finish
1386 if (getLexer().is(AsmToken::EndOfStatement))
1389 // Parse the first operand
1390 if (ParseOperand(Operands))
1393 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1394 getLexer().is(AsmToken::Comma)) {
1395 // Consume the comma token
1398 // Parse the next operand
1399 if (ParseOperand(Operands))
1406 /// ParseDirective parses the PPC specific directives
1407 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1408 StringRef IDVal = DirectiveID.getIdentifier();
1410 if (IDVal == ".word")
1411 return ParseDirectiveWord(2, DirectiveID.getLoc());
1412 if (IDVal == ".llong")
1413 return ParseDirectiveWord(8, DirectiveID.getLoc());
1415 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1416 if (IDVal == ".machine")
1417 return ParseDirectiveMachine(DirectiveID.getLoc());
1418 if (IDVal == ".abiversion")
1419 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1420 if (IDVal == ".localentry")
1421 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1423 if (IDVal == ".machine")
1424 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1429 /// ParseDirectiveWord
1430 /// ::= .word [ expression (, expression)* ]
1431 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1432 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1434 const MCExpr *Value;
1435 if (getParser().parseExpression(Value))
1438 getParser().getStreamer().EmitValue(Value, Size);
1440 if (getLexer().is(AsmToken::EndOfStatement))
1443 if (getLexer().isNot(AsmToken::Comma))
1444 return Error(L, "unexpected token in directive");
1453 /// ParseDirectiveTC
1454 /// ::= .tc [ symbol (, expression)* ]
1455 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1456 // Skip TC symbol, which is only used with XCOFF.
1457 while (getLexer().isNot(AsmToken::EndOfStatement)
1458 && getLexer().isNot(AsmToken::Comma))
1460 if (getLexer().isNot(AsmToken::Comma)) {
1461 Error(L, "unexpected token in directive");
1466 // Align to word size.
1467 getParser().getStreamer().EmitValueToAlignment(Size);
1469 // Emit expressions.
1470 return ParseDirectiveWord(Size, L);
1473 /// ParseDirectiveMachine (ELF platforms)
1474 /// ::= .machine [ cpu | "push" | "pop" ]
1475 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1476 if (getLexer().isNot(AsmToken::Identifier) &&
1477 getLexer().isNot(AsmToken::String)) {
1478 Error(L, "unexpected token in directive");
1482 StringRef CPU = Parser.getTok().getIdentifier();
1485 // FIXME: Right now, the parser always allows any available
1486 // instruction, so the .machine directive is not useful.
1487 // Implement ".machine any" (by doing nothing) for the benefit
1488 // of existing assembler code. Likewise, we can then implement
1489 // ".machine push" and ".machine pop" as no-op.
1490 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1491 Error(L, "unrecognized machine type");
1495 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1496 Error(L, "unexpected token in directive");
1499 PPCTargetStreamer &TStreamer =
1500 *static_cast<PPCTargetStreamer *>(
1501 getParser().getStreamer().getTargetStreamer());
1502 TStreamer.emitMachine(CPU);
1507 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1508 /// ::= .machine cpu-identifier
1509 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1510 if (getLexer().isNot(AsmToken::Identifier) &&
1511 getLexer().isNot(AsmToken::String)) {
1512 Error(L, "unexpected token in directive");
1516 StringRef CPU = Parser.getTok().getIdentifier();
1519 // FIXME: this is only the 'default' set of cpu variants.
1520 // However we don't act on this information at present, this is simply
1521 // allowing parsing to proceed with minimal sanity checking.
1522 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1523 Error(L, "unrecognized cpu type");
1527 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1528 Error(L, "wrong cpu type specified for 64bit");
1531 if (!isPPC64() && CPU == "ppc64") {
1532 Error(L, "wrong cpu type specified for 32bit");
1536 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1537 Error(L, "unexpected token in directive");
1544 /// ParseDirectiveAbiVersion
1545 /// ::= .abiversion constant-expression
1546 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1548 if (getParser().parseAbsoluteExpression(AbiVersion)){
1549 Error(L, "expected constant expression");
1552 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1553 Error(L, "unexpected token in directive");
1557 PPCTargetStreamer &TStreamer =
1558 *static_cast<PPCTargetStreamer *>(
1559 getParser().getStreamer().getTargetStreamer());
1560 TStreamer.emitAbiVersion(AbiVersion);
1565 /// ParseDirectiveLocalEntry
1566 /// ::= .localentry symbol, expression
1567 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1569 if (getParser().parseIdentifier(Name)) {
1570 Error(L, "expected identifier in directive");
1573 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1575 if (getLexer().isNot(AsmToken::Comma)) {
1576 Error(L, "unexpected token in directive");
1582 if (getParser().parseExpression(Expr)) {
1583 Error(L, "expected expression");
1587 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1588 Error(L, "unexpected token in directive");
1592 PPCTargetStreamer &TStreamer =
1593 *static_cast<PPCTargetStreamer *>(
1594 getParser().getStreamer().getTargetStreamer());
1595 TStreamer.emitLocalEntry(Sym, Expr);
1602 /// Force static initialization.
1603 extern "C" void LLVMInitializePowerPCAsmParser() {
1604 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1605 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1606 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1609 #define GET_REGISTER_MATCHER
1610 #define GET_MATCHER_IMPLEMENTATION
1611 #include "PPCGenAsmMatcher.inc"
1613 // Define this matcher function after the auto-generated include so we
1614 // have the match class enum definitions.
1615 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1617 // If the kind is a token for a literal immediate, check if our asm
1618 // operand matches. This is for InstAliases which have a fixed-value
1619 // immediate in the syntax.
1622 case MCK_0: ImmVal = 0; break;
1623 case MCK_1: ImmVal = 1; break;
1624 case MCK_2: ImmVal = 2; break;
1625 case MCK_3: ImmVal = 3; break;
1626 default: return Match_InvalidOperand;
1629 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1630 if (Op.isImm() && Op.getImm() == ImmVal)
1631 return Match_Success;
1633 return Match_InvalidOperand;
1637 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1638 MCSymbolRefExpr::VariantKind Variant,
1641 case MCSymbolRefExpr::VK_PPC_LO:
1642 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1643 case MCSymbolRefExpr::VK_PPC_HI:
1644 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1645 case MCSymbolRefExpr::VK_PPC_HA:
1646 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1647 case MCSymbolRefExpr::VK_PPC_HIGHER:
1648 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1649 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1650 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1651 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1652 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1653 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1654 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);