1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
41 /// instructions for SelectionDAG operations.
43 class PPCDAGToDAGISel : public SelectionDAGISel {
45 PPCTargetLowering &PPCLowering;
46 const PPCSubtarget &PPCSubTarget;
47 unsigned GlobalBaseReg;
49 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(tm), TM(tm),
51 PPCLowering(*TM.getTargetLowering()),
52 PPCSubTarget(*TM.getSubtargetImpl()) {}
54 virtual bool runOnMachineFunction(MachineFunction &MF) {
55 // Make sure we re-emit a set of the global base reg if necessary
57 SelectionDAGISel::runOnMachineFunction(MF);
63 /// getI32Imm - Return a target constant with the specified value, of type
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 /// getI64Imm - Return a target constant with the specified value, of type
71 inline SDValue getI64Imm(uint64_t Imm) {
72 return CurDAG->getTargetConstant(Imm, MVT::i64);
75 /// getSmallIPtrImm - Return a target constant of pointer type.
76 inline SDValue getSmallIPtrImm(unsigned Imm) {
77 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
80 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
81 /// with any number of 0s on either side. The 1s are allowed to wrap from
82 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
83 /// 0x0F0F0000 is not, since all 1s are not contiguous.
84 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
87 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
88 /// rotate and mask opcode and mask operation.
89 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
90 unsigned &SH, unsigned &MB, unsigned &ME);
92 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
93 /// base register. Return the virtual register that holds this value.
94 SDNode *getGlobalBaseReg();
96 // Select - Convert the specified operand from a target-independent to a
97 // target-specific node if it hasn't already been changed.
98 SDNode *Select(SDValue Op);
100 SDNode *SelectBitfieldInsert(SDNode *N);
102 /// SelectCC - Select a comparison of the specified values with the
103 /// specified condition code, returning the CR# of the expression.
104 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
106 /// SelectAddrImm - Returns true if the address N can be represented by
107 /// a base register plus a signed 16-bit displacement [r+imm].
108 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
110 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
113 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
114 /// immediate field. Because preinc imms have already been validated, just
116 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
121 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
122 /// represented as an indexed [r+r] operation. Returns false if it can
123 /// be represented by [r+imm], which are preferred.
124 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
126 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
129 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
130 /// represented as an indexed [r+r] operation.
131 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
133 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
136 /// SelectAddrImmShift - Returns true if the address N can be represented by
137 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
138 /// for use by STD and friends.
139 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
141 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
144 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
145 /// inline asm expressions. It is always correct to compute the value into
146 /// a register. The case of adding a (possibly relocatable) constant to a
147 /// register can be improved, but it is wrong to substitute Reg+Reg for
148 /// Reg in an asm, because the load or store opcode would have to change.
149 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
151 std::vector<SDValue> &OutOps) {
152 OutOps.push_back(Op);
156 SDValue BuildSDIVSequence(SDNode *N);
157 SDValue BuildUDIVSequence(SDNode *N);
159 /// InstructionSelect - This callback is invoked by
160 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
161 virtual void InstructionSelect();
163 void InsertVRSaveCode(MachineFunction &MF);
165 virtual const char *getPassName() const {
166 return "PowerPC DAG->DAG Pattern Instruction Selection";
169 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
170 /// this target when scheduling the DAG.
171 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
172 // Should use subtarget info to pick the right hazard recognizer. For
173 // now, always return a PPC970 recognizer.
174 const TargetInstrInfo *II = TM.getInstrInfo();
175 assert(II && "No InstrInfo?");
176 return new PPCHazardRecognizer970(*II);
179 // Include the pieces autogenerated from the target description.
180 #include "PPCGenDAGISel.inc"
183 SDNode *SelectSETCC(SDValue Op);
187 /// InstructionSelect - This callback is invoked by
188 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
189 void PPCDAGToDAGISel::InstructionSelect() {
190 // Select target instructions for the DAG.
192 CurDAG->RemoveDeadNodes();
195 /// InsertVRSaveCode - Once the entire function has been instruction selected,
196 /// all virtual registers are created and all machine instructions are built,
197 /// check to see if we need to save/restore VRSAVE. If so, do it.
198 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
199 // Check to see if this function uses vector registers, which means we have to
200 // save and restore the VRSAVE register and update it with the regs we use.
202 // In this case, there will be virtual registers of vector type type created
203 // by the scheduler. Detect them now.
204 bool HasVectorVReg = false;
205 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
206 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
207 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
208 HasVectorVReg = true;
211 if (!HasVectorVReg) return; // nothing to do.
213 // If we have a vector register, we want to emit code into the entry and exit
214 // blocks to save and restore the VRSAVE register. We do this here (instead
215 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
217 // 1. This (trivially) reduces the load on the register allocator, by not
218 // having to represent the live range of the VRSAVE register.
219 // 2. This (more significantly) allows us to create a temporary virtual
220 // register to hold the saved VRSAVE value, allowing this temporary to be
221 // register allocated, instead of forcing it to be spilled to the stack.
223 // Create two vregs - one to hold the VRSAVE register that is live-in to the
224 // function and one for the value after having bits or'd into it.
225 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
226 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
228 const TargetInstrInfo &TII = *TM.getInstrInfo();
229 MachineBasicBlock &EntryBB = *Fn.begin();
230 DebugLoc dl = DebugLoc::getUnknownLoc();
231 // Emit the following code into the entry block:
232 // InVRSAVE = MFVRSAVE
233 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
234 // MTVRSAVE UpdatedVRSAVE
235 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
236 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
237 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
238 UpdatedVRSAVE).addReg(InVRSAVE);
239 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
241 // Find all return blocks, outputting a restore in each epilog.
242 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
243 if (!BB->empty() && BB->back().getDesc().isReturn()) {
244 IP = BB->end(); --IP;
246 // Skip over all terminator instructions, which are part of the return
248 MachineBasicBlock::iterator I2 = IP;
249 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
252 // Emit: MTVRSAVE InVRSave
253 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
259 /// getGlobalBaseReg - Output the instructions required to put the
260 /// base address to use for accessing globals into a register.
262 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
263 if (!GlobalBaseReg) {
264 const TargetInstrInfo &TII = *TM.getInstrInfo();
265 // Insert the set of GlobalBaseReg into the first MBB of the function
266 MachineBasicBlock &FirstMBB = MF->front();
267 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
268 DebugLoc dl = DebugLoc::getUnknownLoc();
270 if (PPCLowering.getPointerTy() == MVT::i32) {
271 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
272 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
273 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
275 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
276 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
277 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
280 return CurDAG->getRegister(GlobalBaseReg,
281 PPCLowering.getPointerTy()).getNode();
284 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
285 /// or 64-bit immediate, and if the value can be accurately represented as a
286 /// sign extension from a 16-bit value. If so, this returns true and the
288 static bool isIntS16Immediate(SDNode *N, short &Imm) {
289 if (N->getOpcode() != ISD::Constant)
292 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
293 if (N->getValueType(0) == MVT::i32)
294 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
296 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
299 static bool isIntS16Immediate(SDValue Op, short &Imm) {
300 return isIntS16Immediate(Op.getNode(), Imm);
304 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
305 /// operand. If so Imm will receive the 32-bit value.
306 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
307 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
308 Imm = cast<ConstantSDNode>(N)->getZExtValue();
314 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
315 /// operand. If so Imm will receive the 64-bit value.
316 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
317 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
318 Imm = cast<ConstantSDNode>(N)->getZExtValue();
324 // isInt32Immediate - This method tests to see if a constant operand.
325 // If so Imm will receive the 32 bit value.
326 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
327 return isInt32Immediate(N.getNode(), Imm);
331 // isOpcWithIntImmediate - This method tests to see if the node is a specific
332 // opcode and that it has a immediate integer right operand.
333 // If so Imm will receive the 32 bit value.
334 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
335 return N->getOpcode() == Opc
336 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
339 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
340 if (isShiftedMask_32(Val)) {
341 // look for the first non-zero bit
342 MB = CountLeadingZeros_32(Val);
343 // look for the first zero bit after the run of ones
344 ME = CountLeadingZeros_32((Val - 1) ^ Val);
347 Val = ~Val; // invert mask
348 if (isShiftedMask_32(Val)) {
349 // effectively look for the first zero bit
350 ME = CountLeadingZeros_32(Val) - 1;
351 // effectively look for the first one bit after the run of zeros
352 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
360 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
361 bool IsShiftMask, unsigned &SH,
362 unsigned &MB, unsigned &ME) {
363 // Don't even go down this path for i64, since different logic will be
364 // necessary for rldicl/rldicr/rldimi.
365 if (N->getValueType(0) != MVT::i32)
369 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
370 unsigned Opcode = N->getOpcode();
371 if (N->getNumOperands() != 2 ||
372 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
375 if (Opcode == ISD::SHL) {
376 // apply shift left to mask if it comes first
377 if (IsShiftMask) Mask = Mask << Shift;
378 // determine which bits are made indeterminant by shift
379 Indeterminant = ~(0xFFFFFFFFu << Shift);
380 } else if (Opcode == ISD::SRL) {
381 // apply shift right to mask if it comes first
382 if (IsShiftMask) Mask = Mask >> Shift;
383 // determine which bits are made indeterminant by shift
384 Indeterminant = ~(0xFFFFFFFFu >> Shift);
385 // adjust for the left rotate
387 } else if (Opcode == ISD::ROTL) {
393 // if the mask doesn't intersect any Indeterminant bits
394 if (Mask && !(Mask & Indeterminant)) {
396 // make sure the mask is still a mask (wrap arounds may not be)
397 return isRunOfOnes(Mask, MB, ME);
402 /// SelectBitfieldInsert - turn an or of two masked values into
403 /// the rotate left word immediate then mask insert (rlwimi) instruction.
404 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
405 SDValue Op0 = N->getOperand(0);
406 SDValue Op1 = N->getOperand(1);
407 DebugLoc dl = N->getDebugLoc();
409 APInt LKZ, LKO, RKZ, RKO;
410 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
411 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
413 unsigned TargetMask = LKZ.getZExtValue();
414 unsigned InsertMask = RKZ.getZExtValue();
416 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
417 unsigned Op0Opc = Op0.getOpcode();
418 unsigned Op1Opc = Op1.getOpcode();
419 unsigned Value, SH = 0;
420 TargetMask = ~TargetMask;
421 InsertMask = ~InsertMask;
423 // If the LHS has a foldable shift and the RHS does not, then swap it to the
424 // RHS so that we can fold the shift into the insert.
425 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
426 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
427 Op0.getOperand(0).getOpcode() == ISD::SRL) {
428 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
429 Op1.getOperand(0).getOpcode() != ISD::SRL) {
431 std::swap(Op0Opc, Op1Opc);
432 std::swap(TargetMask, InsertMask);
435 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
436 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
437 Op1.getOperand(0).getOpcode() != ISD::SRL) {
439 std::swap(Op0Opc, Op1Opc);
440 std::swap(TargetMask, InsertMask);
445 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
446 SDValue Tmp1, Tmp2, Tmp3;
447 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
449 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
450 isInt32Immediate(Op1.getOperand(1), Value)) {
451 Op1 = Op1.getOperand(0);
452 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
454 if (Op1Opc == ISD::AND) {
455 unsigned SHOpc = Op1.getOperand(0).getOpcode();
456 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
457 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
458 Op1 = Op1.getOperand(0).getOperand(0);
459 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
461 Op1 = Op1.getOperand(0);
465 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
467 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
469 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
475 /// SelectCC - Select a comparison of the specified values with the specified
476 /// condition code, returning the CR# of the expression.
477 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
478 ISD::CondCode CC, DebugLoc dl) {
479 // Always select the LHS.
482 if (LHS.getValueType() == MVT::i32) {
484 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
485 if (isInt32Immediate(RHS, Imm)) {
486 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
488 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
489 getI32Imm(Imm & 0xFFFF)), 0);
490 // If this is a 16-bit signed immediate, fold it.
491 if (isInt16((int)Imm))
492 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
493 getI32Imm(Imm & 0xFFFF)), 0);
495 // For non-equality comparisons, the default code would materialize the
496 // constant, then compare against it, like this:
500 // Since we are just comparing for equality, we can emit this instead:
501 // xoris r0,r3,0x1234
502 // cmplwi cr0,r0,0x5678
504 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
505 getI32Imm(Imm >> 16)), 0);
506 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
507 getI32Imm(Imm & 0xFFFF)), 0);
510 } else if (ISD::isUnsignedIntSetCC(CC)) {
511 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
512 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
513 getI32Imm(Imm & 0xFFFF)), 0);
517 if (isIntS16Immediate(RHS, SImm))
518 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
519 getI32Imm((int)SImm & 0xFFFF)),
523 } else if (LHS.getValueType() == MVT::i64) {
525 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
526 if (isInt64Immediate(RHS.getNode(), Imm)) {
527 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
529 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
530 getI32Imm(Imm & 0xFFFF)), 0);
531 // If this is a 16-bit signed immediate, fold it.
533 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
534 getI32Imm(Imm & 0xFFFF)), 0);
536 // For non-equality comparisons, the default code would materialize the
537 // constant, then compare against it, like this:
541 // Since we are just comparing for equality, we can emit this instead:
542 // xoris r0,r3,0x1234
543 // cmpldi cr0,r0,0x5678
546 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
547 getI64Imm(Imm >> 16)), 0);
548 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
549 getI64Imm(Imm & 0xFFFF)), 0);
553 } else if (ISD::isUnsignedIntSetCC(CC)) {
554 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
555 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
556 getI64Imm(Imm & 0xFFFF)), 0);
560 if (isIntS16Immediate(RHS, SImm))
561 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
562 getI64Imm(SImm & 0xFFFF)),
566 } else if (LHS.getValueType() == MVT::f32) {
569 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
572 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
575 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
581 llvm_unreachable("Should be lowered by legalize!");
582 default: llvm_unreachable("Unknown condition!");
584 case ISD::SETEQ: return PPC::PRED_EQ;
586 case ISD::SETNE: return PPC::PRED_NE;
588 case ISD::SETLT: return PPC::PRED_LT;
590 case ISD::SETLE: return PPC::PRED_LE;
592 case ISD::SETGT: return PPC::PRED_GT;
594 case ISD::SETGE: return PPC::PRED_GE;
595 case ISD::SETO: return PPC::PRED_NU;
596 case ISD::SETUO: return PPC::PRED_UN;
597 // These two are invalid for floating point. Assume we have int.
598 case ISD::SETULT: return PPC::PRED_LT;
599 case ISD::SETUGT: return PPC::PRED_GT;
603 /// getCRIdxForSetCC - Return the index of the condition register field
604 /// associated with the SetCC condition, and whether or not the field is
605 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
607 /// If this returns with Other != -1, then the returned comparison is an or of
608 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
609 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
613 default: llvm_unreachable("Unknown condition!");
615 case ISD::SETLT: return 0; // Bit #0 = SETOLT
617 case ISD::SETGT: return 1; // Bit #1 = SETOGT
619 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
620 case ISD::SETUO: return 3; // Bit #3 = SETUO
622 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
624 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
626 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
627 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
632 llvm_unreachable("Invalid branch code: should be expanded by legalize");
633 // These are invalid for floating point. Assume integer.
634 case ISD::SETULT: return 0;
635 case ISD::SETUGT: return 1;
640 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
641 SDNode *N = Op.getNode();
642 DebugLoc dl = N->getDebugLoc();
644 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
645 if (isInt32Immediate(N->getOperand(1), Imm)) {
646 // We can codegen setcc op, imm very efficiently compared to a brcond.
647 // Check for those cases here.
650 SDValue Op = N->getOperand(0);
654 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
655 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
656 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
660 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
661 Op, getI32Imm(~0U)), 0);
662 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
666 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
667 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
671 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
672 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
673 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
674 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
677 } else if (Imm == ~0U) { // setcc op, -1
678 SDValue Op = N->getOperand(0);
682 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
683 Op, getI32Imm(1)), 0);
684 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
685 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
690 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
691 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
693 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
697 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
699 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
701 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
702 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
705 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
706 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
708 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
717 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
718 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
721 // Force the ccreg into CR7.
722 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
724 SDValue InFlag(0, 0); // Null incoming flag value.
725 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
728 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
729 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
732 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
734 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
735 getI32Imm(31), getI32Imm(31) };
736 if (OtherCondIdx == -1 && !Inv)
737 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
739 // Get the specified bit.
741 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
743 assert(OtherCondIdx == -1 && "Can't have split plus negation");
744 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
747 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
748 // We already got the bit for the first part of the comparison (e.g. SETULE).
750 // Get the other bit of the comparison.
751 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
753 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
755 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
759 // Select - Convert the specified operand from a target-independent to a
760 // target-specific node if it hasn't already been changed.
761 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
762 SDNode *N = Op.getNode();
763 DebugLoc dl = Op.getDebugLoc();
764 if (N->isMachineOpcode())
765 return NULL; // Already selected.
767 switch (N->getOpcode()) {
770 case ISD::Constant: {
771 if (N->getValueType(0) == MVT::i64) {
773 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
774 // Assume no remaining bits.
775 unsigned Remainder = 0;
776 // Assume no shift required.
779 // If it can't be represented as a 32 bit value.
781 Shift = CountTrailingZeros_64(Imm);
782 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
784 // If the shifted value fits 32 bits.
785 if (isInt32(ImmSh)) {
786 // Go with the shifted value.
789 // Still stuck with a 64 bit value.
796 // Intermediate operand.
799 // Handle first 32 bits.
800 unsigned Lo = Imm & 0xFFFF;
801 unsigned Hi = (Imm >> 16) & 0xFFFF;
806 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
808 // Handle the Hi bits.
809 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
810 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
812 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
813 SDValue(Result, 0), getI32Imm(Lo));
816 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
819 // If no shift, we're done.
820 if (!Shift) return Result;
822 // Shift for next step if the upper 32-bits were not zero.
824 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
827 getI32Imm(63 - Shift));
830 // Add in the last bits as required.
831 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
832 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
833 SDValue(Result, 0), getI32Imm(Hi));
835 if ((Lo = Remainder & 0xFFFF)) {
836 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
837 SDValue(Result, 0), getI32Imm(Lo));
846 return SelectSETCC(Op);
847 case PPCISD::GlobalBaseReg:
848 return getGlobalBaseReg();
850 case ISD::FrameIndex: {
851 int FI = cast<FrameIndexSDNode>(N)->getIndex();
852 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
853 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
855 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
857 return CurDAG->getMachineNode(Opc, dl, Op.getValueType(), TFI,
862 SDValue InFlag = N->getOperand(1);
863 // Use MFOCRF if supported.
864 if (PPCSubTarget.isGigaProcessor())
865 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
866 N->getOperand(0), InFlag);
868 return CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, InFlag);
872 // FIXME: since this depends on the setting of the carry flag from the srawi
873 // we should really be making notes about that for the scheduler.
874 // FIXME: It sure would be nice if we could cheaply recognize the
875 // srl/add/sra pattern the dag combiner will generate for this as
876 // sra/addze rather than having to handle sdiv ourselves. oh well.
878 if (isInt32Immediate(N->getOperand(1), Imm)) {
879 SDValue N0 = N->getOperand(0);
880 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
882 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
883 N0, getI32Imm(Log2_32(Imm)));
884 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
885 SDValue(Op, 0), SDValue(Op, 1));
886 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
888 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
889 N0, getI32Imm(Log2_32(-Imm)));
891 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
892 SDValue(Op, 0), SDValue(Op, 1)),
894 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
898 // Other cases are autogenerated.
903 // Handle preincrement loads.
904 LoadSDNode *LD = cast<LoadSDNode>(Op);
905 EVT LoadedVT = LD->getMemoryVT();
907 // Normal loads are handled by code generated from the .td file.
908 if (LD->getAddressingMode() != ISD::PRE_INC)
911 SDValue Offset = LD->getOffset();
912 if (isa<ConstantSDNode>(Offset) ||
913 Offset.getOpcode() == ISD::TargetGlobalAddress) {
916 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
917 if (LD->getValueType(0) != MVT::i64) {
918 // Handle PPC32 integer and normal FP loads.
919 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
920 switch (LoadedVT.getSimpleVT().SimpleTy) {
921 default: llvm_unreachable("Invalid PPC load type!");
922 case MVT::f64: Opcode = PPC::LFDU; break;
923 case MVT::f32: Opcode = PPC::LFSU; break;
924 case MVT::i32: Opcode = PPC::LWZU; break;
925 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
927 case MVT::i8: Opcode = PPC::LBZU; break;
930 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
931 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
932 switch (LoadedVT.getSimpleVT().SimpleTy) {
933 default: llvm_unreachable("Invalid PPC load type!");
934 case MVT::i64: Opcode = PPC::LDU; break;
935 case MVT::i32: Opcode = PPC::LWZU8; break;
936 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
938 case MVT::i8: Opcode = PPC::LBZU8; break;
942 SDValue Chain = LD->getChain();
943 SDValue Base = LD->getBasePtr();
944 SDValue Ops[] = { Offset, Base, Chain };
946 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
947 PPCLowering.getPointerTy(),
950 llvm_unreachable("R+R preindex loads not supported yet!");
955 unsigned Imm, Imm2, SH, MB, ME;
957 // If this is an and of a value rotated between 0 and 31 bits and then and'd
958 // with a mask, emit rlwinm
959 if (isInt32Immediate(N->getOperand(1), Imm) &&
960 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
961 SDValue Val = N->getOperand(0).getOperand(0);
962 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
963 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
965 // If this is just a masked value where the input is not handled above, and
966 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
967 if (isInt32Immediate(N->getOperand(1), Imm) &&
968 isRunOfOnes(Imm, MB, ME) &&
969 N->getOperand(0).getOpcode() != ISD::ROTL) {
970 SDValue Val = N->getOperand(0);
971 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
972 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
974 // AND X, 0 -> 0, not "rlwinm 32".
975 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
976 ReplaceUses(SDValue(N, 0), N->getOperand(1));
979 // ISD::OR doesn't get all the bitfield insertion fun.
980 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
981 if (isInt32Immediate(N->getOperand(1), Imm) &&
982 N->getOperand(0).getOpcode() == ISD::OR &&
983 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
986 if (isRunOfOnes(Imm, MB, ME)) {
987 SDValue Ops[] = { N->getOperand(0).getOperand(0),
988 N->getOperand(0).getOperand(1),
989 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
990 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
994 // Other cases are autogenerated.
998 if (N->getValueType(0) == MVT::i32)
999 if (SDNode *I = SelectBitfieldInsert(N))
1002 // Other cases are autogenerated.
1005 unsigned Imm, SH, MB, ME;
1006 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1007 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1008 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1009 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1010 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1013 // Other cases are autogenerated.
1017 unsigned Imm, SH, MB, ME;
1018 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1019 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1020 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1021 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1022 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1025 // Other cases are autogenerated.
1028 case ISD::SELECT_CC: {
1029 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1031 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1032 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1033 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1034 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1035 if (N1C->isNullValue() && N3C->isNullValue() &&
1036 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1037 // FIXME: Implement this optzn for PPC64.
1038 N->getValueType(0) == MVT::i32) {
1040 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
1041 N->getOperand(0), getI32Imm(~0U));
1042 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1043 SDValue(Tmp, 0), N->getOperand(0),
1047 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1048 unsigned BROpc = getPredicateForSetCC(CC);
1050 unsigned SelectCCOp;
1051 if (N->getValueType(0) == MVT::i32)
1052 SelectCCOp = PPC::SELECT_CC_I4;
1053 else if (N->getValueType(0) == MVT::i64)
1054 SelectCCOp = PPC::SELECT_CC_I8;
1055 else if (N->getValueType(0) == MVT::f32)
1056 SelectCCOp = PPC::SELECT_CC_F4;
1057 else if (N->getValueType(0) == MVT::f64)
1058 SelectCCOp = PPC::SELECT_CC_F8;
1060 SelectCCOp = PPC::SELECT_CC_VRRC;
1062 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1064 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1066 case PPCISD::COND_BRANCH: {
1067 // Op #0 is the Chain.
1068 // Op #1 is the PPC::PRED_* number.
1070 // Op #3 is the Dest MBB
1071 // Op #4 is the Flag.
1072 // Prevent PPC::PRED_* from being selected into LI.
1074 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1075 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1076 N->getOperand(0), N->getOperand(4) };
1077 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1080 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1081 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1082 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1083 N->getOperand(4), N->getOperand(0) };
1084 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1087 // FIXME: Should custom lower this.
1088 SDValue Chain = N->getOperand(0);
1089 SDValue Target = N->getOperand(1);
1090 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1091 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1093 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1097 return SelectCode(Op);
1102 /// createPPCISelDag - This pass converts a legalized DAG into a
1103 /// PowerPC-specific DAG, ready for instruction scheduling.
1105 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1106 return new PPCDAGToDAGISel(TM);