1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 /// Indicate that the VSX instruction is to use VSX numbering/encoding.
42 /// Since ISA 3.0, there are scalar instructions that use the upper
43 /// half of the VSX register set only. Rather than adding further complexity
44 /// to the register class set, the VSX registers just include the Altivec
45 /// registers and this flag decides the numbering to be used for them.
46 bits<1> UseVSXReg = 0;
47 let TSFlags{6} = UseVSXReg;
49 // Fields used for relation models.
52 // For cases where multiple instruction definitions really represent the
53 // same underlying instruction but with one definition for 64-bit arguments
54 // and one for 32-bit arguments, this bit breaks the degeneracy between
55 // the two forms and allows TableGen to generate mapping tables.
56 bit Interpretation64Bit = 0;
59 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
60 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
61 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
62 class PPC970_MicroCode;
64 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
65 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
66 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
67 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
68 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
69 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
70 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
71 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
73 class UseVSXReg { bits<1> UseVSXReg = 1; }
75 // Two joined instructions; used to emit two adjacent instructions as one.
76 // The itinerary from the first instruction is used for scheduling and
78 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
82 field bits<64> SoftFail = 0;
85 bit PPC64 = 0; // Default value, override with isPPC64
87 let Namespace = "PPC";
88 let Inst{0-5} = opcode1;
89 let Inst{32-37} = opcode2;
90 let OutOperandList = OOL;
91 let InOperandList = IOL;
92 let AsmString = asmstr;
95 bits<1> PPC970_First = 0;
96 bits<1> PPC970_Single = 0;
97 bits<1> PPC970_Cracked = 0;
98 bits<3> PPC970_Unit = 0;
100 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
101 /// these must be reflected there! See comments there for what these are.
102 let TSFlags{0} = PPC970_First;
103 let TSFlags{1} = PPC970_Single;
104 let TSFlags{2} = PPC970_Cracked;
105 let TSFlags{5-3} = PPC970_Unit;
107 // Fields used for relation models.
108 string BaseName = "";
109 bit Interpretation64Bit = 0;
113 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
114 InstrItinClass itin, list<dag> pattern>
115 : I<opcode, OOL, IOL, asmstr, itin> {
116 let Pattern = pattern;
125 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
132 let BI{0-1} = BIBO{5-6};
133 let BI{2-4} = CR{0-2};
135 let Inst{6-10} = BIBO{4-0};
136 let Inst{11-15} = BI;
137 let Inst{16-29} = BD;
142 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
150 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
151 dag OOL, dag IOL, string asmstr>
152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
156 let Inst{11-15} = bi;
157 let Inst{16-29} = BD;
162 class BForm_3<bits<6> opcode, bit aa, bit lk,
163 dag OOL, dag IOL, string asmstr>
164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
170 let Inst{11-15} = BI;
171 let Inst{16-29} = BD;
176 class BForm_3_at<bits<6> opcode, bit aa, bit lk,
177 dag OOL, dag IOL, string asmstr>
178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
184 let Inst{6-8} = BO{4-2};
186 let Inst{11-15} = BI;
187 let Inst{16-29} = BD;
192 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
193 dag OOL, dag IOL, string asmstr>
194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
199 let Inst{11-15} = BI;
200 let Inst{16-29} = BD;
206 class SCForm<bits<6> opcode, bits<1> xo,
207 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
209 : I<opcode, OOL, IOL, asmstr, itin> {
212 let Pattern = pattern;
214 let Inst{20-26} = LEV;
219 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
220 InstrItinClass itin, list<dag> pattern>
221 : I<opcode, OOL, IOL, asmstr, itin> {
226 let Pattern = pattern;
233 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
234 InstrItinClass itin, list<dag> pattern>
235 : I<opcode, OOL, IOL, asmstr, itin> {
239 let Pattern = pattern;
242 let Inst{11-15} = Addr{20-16}; // Base Reg
243 let Inst{16-31} = Addr{15-0}; // Displacement
246 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
247 InstrItinClass itin, list<dag> pattern>
248 : I<opcode, OOL, IOL, asmstr, itin> {
253 let Pattern = pattern;
261 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
262 InstrItinClass itin, list<dag> pattern>
263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
265 // Even though ADDICo does not really have an RC bit, provide
266 // the declaration of one here so that isDOT has something to set.
270 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
271 InstrItinClass itin, list<dag> pattern>
272 : I<opcode, OOL, IOL, asmstr, itin> {
276 let Pattern = pattern;
283 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
284 InstrItinClass itin, list<dag> pattern>
285 : I<opcode, OOL, IOL, asmstr, itin> {
290 let Pattern = pattern;
297 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
298 InstrItinClass itin, list<dag> pattern>
299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
304 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
305 string asmstr, InstrItinClass itin,
307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
313 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
314 dag OOL, dag IOL, string asmstr,
315 InstrItinClass itin, list<dag> pattern>
316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
320 let Pattern = pattern;
328 let Inst{43-47} = Addr{20-16}; // Base Reg
329 let Inst{48-63} = Addr{15-0}; // Displacement
332 // This is used to emit BL8+NOP.
333 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
334 dag OOL, dag IOL, string asmstr,
335 InstrItinClass itin, list<dag> pattern>
336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
337 OOL, IOL, asmstr, itin, pattern> {
342 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
344 : I<opcode, OOL, IOL, asmstr, itin> {
353 let Inst{11-15} = RA;
357 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
359 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
363 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
365 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
367 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
369 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
375 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
376 InstrItinClass itin, list<dag> pattern>
377 : I<opcode, OOL, IOL, asmstr, itin> {
381 let Pattern = pattern;
383 let Inst{6-10} = RST;
384 let Inst{11-15} = DS_RA{18-14}; // Register #
385 let Inst{16-29} = DS_RA{13-0}; // Displacement.
386 let Inst{30-31} = xo;
389 // ISA V3.0B 1.6.6 DX-Form
390 class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
391 InstrItinClass itin, list<dag> pattern>
392 : I<opcode, OOL, IOL, asmstr, itin> {
396 let Pattern = pattern;
399 let Inst{11-15} = D{5-1}; // d1
400 let Inst{16-25} = D{15-6}; // d0
401 let Inst{26-30} = xo;
402 let Inst{31} = D{0}; // d2
405 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
406 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
407 string asmstr, InstrItinClass itin, list<dag> pattern>
408 : I<opcode, OOL, IOL, asmstr, itin> {
412 let Pattern = pattern;
414 let Inst{6-10} = XT{4-0};
415 let Inst{11-15} = DS_RA{16-12}; // Register #
416 let Inst{16-27} = DS_RA{11-0}; // Displacement.
417 let Inst{28} = XT{5};
418 let Inst{29-31} = xo;
422 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
423 InstrItinClass itin, list<dag> pattern>
424 : I<opcode, OOL, IOL, asmstr, itin> {
429 let Pattern = pattern;
431 bit RC = 0; // set by isDOT
433 let Inst{6-10} = RST;
436 let Inst{21-30} = xo;
440 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
441 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
445 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
447 : I<opcode, OOL, IOL, asmstr, itin> {
448 let Inst{21-30} = xo;
451 // This is the same as XForm_base_r3xo, but the first two operands are swapped
452 // when code is emitted.
453 class XForm_base_r3xo_swapped
454 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
456 : I<opcode, OOL, IOL, asmstr, itin> {
461 bit RC = 0; // set by isDOT
463 let Inst{6-10} = RST;
466 let Inst{21-30} = xo;
471 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
472 InstrItinClass itin, list<dag> pattern>
473 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
475 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
476 InstrItinClass itin, list<dag> pattern>
477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
481 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
482 InstrItinClass itin, list<dag> pattern>
483 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
488 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 InstrItinClass itin, list<dag> pattern>
490 : I<opcode, OOL, IOL, asmstr, itin> {
495 let Pattern = pattern;
497 let Inst{6-10} = RST;
500 let Inst{21-30} = xo;
504 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
505 InstrItinClass itin, list<dag> pattern>
506 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
507 let Pattern = pattern;
510 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
511 InstrItinClass itin, list<dag> pattern>
512 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
514 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 InstrItinClass itin, list<dag> pattern>
516 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
517 let Pattern = pattern;
520 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
521 InstrItinClass itin, list<dag> pattern>
522 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
524 let Pattern = pattern;
527 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
529 : I<opcode, OOL, IOL, asmstr, itin> {
538 let Inst{11-15} = RA;
539 let Inst{16-20} = RB;
540 let Inst{21-30} = xo;
544 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : I<opcode, OOL, IOL, asmstr, itin> {
553 let Inst{11-15} = RA;
554 let Inst{16-20} = RB;
555 let Inst{21-30} = xo;
559 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
561 : I<opcode, OOL, IOL, asmstr, itin> {
566 let Inst{12-15} = SR;
567 let Inst{21-30} = xo;
570 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
572 : I<opcode, OOL, IOL, asmstr, itin> {
576 let Inst{21-30} = xo;
579 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
581 : I<opcode, OOL, IOL, asmstr, itin> {
586 let Inst{16-20} = RB;
587 let Inst{21-30} = xo;
590 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
592 : I<opcode, OOL, IOL, asmstr, itin> {
598 let Inst{21-30} = xo;
601 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
603 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
607 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
609 : I<opcode, OOL, IOL, asmstr, itin> {
616 let Inst{11-15} = FRA;
617 let Inst{16-20} = FRB;
618 let Inst{21-30} = xo;
622 class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
624 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
629 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
630 InstrItinClass itin, list<dag> pattern>
631 : I<opcode, OOL, IOL, asmstr, itin> {
636 let Pattern = pattern;
638 let Inst{6-10} = FRT;
639 let Inst{11-15} = FRA;
640 let Inst{16-20} = FRB;
641 let Inst{21-30} = xo;
645 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
646 InstrItinClass itin, list<dag> pattern>
647 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
651 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
652 InstrItinClass itin, list<dag> pattern>
653 : I<opcode, OOL, IOL, asmstr, itin> {
659 let Pattern = pattern;
661 let Inst{6-10} = FRT;
662 let Inst{11-15} = FRA;
663 let Inst{16-20} = FRB;
664 let Inst{21-24} = tttt;
665 let Inst{25-30} = xo;
669 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
670 InstrItinClass itin, list<dag> pattern>
671 : I<opcode, OOL, IOL, asmstr, itin> {
672 let Pattern = pattern;
676 let Inst{21-30} = xo;
680 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
681 string asmstr, InstrItinClass itin, list<dag> pattern>
682 : I<opcode, OOL, IOL, asmstr, itin> {
685 let Pattern = pattern;
690 let Inst{21-30} = xo;
694 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
695 string asmstr, InstrItinClass itin, list<dag> pattern>
696 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
700 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
701 InstrItinClass itin, list<dag> pattern>
702 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
705 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
706 InstrItinClass itin, list<dag> pattern>
707 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
711 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
712 InstrItinClass itin, list<dag> pattern>
713 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
716 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
717 // numbers presumably relates to some document, but I haven't found it.
718 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
719 InstrItinClass itin, list<dag> pattern>
720 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
721 let Pattern = pattern;
723 bit RC = 0; // set by isDOT
725 let Inst{6-10} = RST;
727 let Inst{21-30} = xo;
730 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
731 InstrItinClass itin, list<dag> pattern>
732 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
733 let Pattern = pattern;
736 bit RC = 0; // set by isDOT
740 let Inst{21-30} = xo;
744 class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
746 : I<opcode, OOL, IOL, asmstr, itin> {
751 let Inst{11-13} = BFA;
754 let Inst{21-30} = xo;
758 class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
760 : I<opcode, OOL, IOL, asmstr, itin> {
768 let Inst{21-30} = xo;
772 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
773 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
775 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
776 let Pattern = pattern;
778 let Inst{6-10} = RST;
779 let Inst{11-12} = xo1;
780 let Inst{13-15} = xo2;
782 let Inst{21-30} = xo;
786 class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
787 bits<10> xo, dag OOL, dag IOL, string asmstr,
788 InstrItinClass itin, list<dag> pattern>
789 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
790 let Pattern = pattern;
793 let Inst{6-10} = RST;
794 let Inst{11-12} = xo1;
795 let Inst{13-15} = xo2;
796 let Inst{16-20} = FRB;
797 let Inst{21-30} = xo;
801 class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
802 bits<10> xo, dag OOL, dag IOL, string asmstr,
803 InstrItinClass itin, list<dag> pattern>
804 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
805 let Pattern = pattern;
808 let Inst{6-10} = RST;
809 let Inst{11-12} = xo1;
810 let Inst{13-15} = xo2;
812 let Inst{18-20} = DRM;
813 let Inst{21-30} = xo;
817 class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
818 bits<10> xo, dag OOL, dag IOL, string asmstr,
819 InstrItinClass itin, list<dag> pattern>
820 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
821 let Pattern = pattern;
824 let Inst{6-10} = RST;
825 let Inst{11-12} = xo1;
826 let Inst{13-15} = xo2;
828 let Inst{19-20} = RM;
829 let Inst{21-30} = xo;
834 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
835 InstrItinClass itin, list<dag> pattern>
836 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
842 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
843 InstrItinClass itin, list<dag> pattern>
844 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
849 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
850 string asmstr, InstrItinClass itin, list<dag> pattern>
851 : I<opcode, OOL, IOL, asmstr, itin> {
859 let Inst{21-30} = xo;
863 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
864 string asmstr, InstrItinClass itin, list<dag> pattern>
865 : I<opcode, OOL, IOL, asmstr, itin> {
872 let Inst{21-30} = xo;
876 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
877 InstrItinClass itin, list<dag> pattern>
878 : I<opcode, OOL, IOL, asmstr, itin> {
881 bit RC = 0; // set by isDOT
886 let Inst{21-30} = xo;
890 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
891 InstrItinClass itin, list<dag> pattern>
892 : I<opcode, OOL, IOL, asmstr, itin> {
899 let Inst{21-30} = xo;
903 // [PO RT RA RB XO /]
904 class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
905 string asmstr, InstrItinClass itin, list<dag> pattern>
906 : I<opcode, OOL, IOL, asmstr, itin> {
912 let Pattern = pattern;
917 let Inst{11-15} = RA;
918 let Inst{16-20} = RB;
919 let Inst{21-30} = xo;
923 // Same as XForm_17 but with GPR's and new naming convention
924 class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
925 string asmstr, InstrItinClass itin, list<dag> pattern>
926 : I<opcode, OOL, IOL, asmstr, itin> {
931 let Pattern = pattern;
935 let Inst{11-15} = RA;
936 let Inst{16-20} = RB;
937 let Inst{21-30} = xo;
941 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
942 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
943 string asmstr, InstrItinClass itin, list<dag> pattern>
944 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
948 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
949 string asmstr, InstrItinClass itin, list<dag> pattern>
950 : I<opcode, OOL, IOL, asmstr, itin> {
955 let Pattern = pattern;
958 let Inst{9-15} = DCMX;
959 let Inst{16-20} = VB;
960 let Inst{21-30} = xo;
964 class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
965 string asmstr, InstrItinClass itin, list<dag> pattern>
966 : I<opcode, OOL, IOL, asmstr, itin> {
970 let Pattern = pattern;
972 let Inst{6-10} = XT{4-0};
974 let Inst{13-20} = IMM8;
975 let Inst{21-30} = xo;
976 let Inst{31} = XT{5};
979 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
980 // to specify an SDAG pattern for matching.
981 class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
982 string asmstr, InstrItinClass itin>
983 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
986 class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
988 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
993 // [PO /// L RA RB XO /]
994 class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
995 string asmstr, InstrItinClass itin, list<dag> pattern>
996 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
998 let Pattern = pattern;
1005 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1006 InstrItinClass itin, list<dag> pattern>
1007 : I<opcode, OOL, IOL, asmstr, itin> {
1012 let Pattern = pattern;
1014 let Inst{6-10} = XT{4-0};
1015 let Inst{11-15} = A;
1016 let Inst{16-20} = B;
1017 let Inst{21-30} = xo;
1018 let Inst{31} = XT{5};
1021 class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1022 string asmstr, InstrItinClass itin, list<dag> pattern>
1023 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1027 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1028 InstrItinClass itin, list<dag> pattern>
1029 : I<opcode, OOL, IOL, asmstr, itin> {
1033 let Pattern = pattern;
1035 let Inst{6-10} = XT{4-0};
1036 let Inst{11-15} = 0;
1037 let Inst{16-20} = XB{4-0};
1038 let Inst{21-29} = xo;
1039 let Inst{30} = XB{5};
1040 let Inst{31} = XT{5};
1043 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1044 InstrItinClass itin, list<dag> pattern>
1045 : I<opcode, OOL, IOL, asmstr, itin> {
1049 let Pattern = pattern;
1053 let Inst{16-20} = XB{4-0};
1054 let Inst{21-29} = xo;
1055 let Inst{30} = XB{5};
1059 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1060 InstrItinClass itin, list<dag> pattern>
1061 : I<opcode, OOL, IOL, asmstr, itin> {
1066 let Pattern = pattern;
1068 let Inst{6-10} = XT{4-0};
1069 let Inst{11-13} = 0;
1070 let Inst{14-15} = D;
1071 let Inst{16-20} = XB{4-0};
1072 let Inst{21-29} = xo;
1073 let Inst{30} = XB{5};
1074 let Inst{31} = XT{5};
1077 class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1078 string asmstr, InstrItinClass itin, list<dag> pattern>
1079 : I<opcode, OOL, IOL, asmstr, itin> {
1084 let Pattern = pattern;
1086 let Inst{6-10} = XT{4-0};
1087 let Inst{11-15} = UIM5;
1088 let Inst{16-20} = XB{4-0};
1089 let Inst{21-29} = xo;
1090 let Inst{30} = XB{5};
1091 let Inst{31} = XT{5};
1094 // [PO T XO B XO BX /]
1095 class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1096 string asmstr, InstrItinClass itin, list<dag> pattern>
1097 : I<opcode, OOL, IOL, asmstr, itin> {
1101 let Pattern = pattern;
1103 let Inst{6-10} = RT;
1104 let Inst{11-15} = xo2;
1105 let Inst{16-20} = XB{4-0};
1106 let Inst{21-29} = xo;
1107 let Inst{30} = XB{5};
1111 // [PO T XO B XO BX TX]
1112 class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1113 string asmstr, InstrItinClass itin, list<dag> pattern>
1114 : I<opcode, OOL, IOL, asmstr, itin> {
1118 let Pattern = pattern;
1120 let Inst{6-10} = XT{4-0};
1121 let Inst{11-15} = xo2;
1122 let Inst{16-20} = XB{4-0};
1123 let Inst{21-29} = xo;
1124 let Inst{30} = XB{5};
1125 let Inst{31} = XT{5};
1128 class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1129 string asmstr, InstrItinClass itin, list<dag> pattern>
1130 : I<opcode, OOL, IOL, asmstr, itin> {
1135 let Pattern = pattern;
1138 let Inst{9-15} = DCMX;
1139 let Inst{16-20} = XB{4-0};
1140 let Inst{21-29} = xo;
1141 let Inst{30} = XB{5};
1145 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1146 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
1148 : I<opcode, OOL, IOL, asmstr, itin> {
1153 let Pattern = pattern;
1155 let Inst{6-10} = XT{4-0};
1156 let Inst{11-15} = DCMX{4-0};
1157 let Inst{16-20} = XB{4-0};
1158 let Inst{21-24} = xo1;
1159 let Inst{25} = DCMX{5};
1160 let Inst{26-28} = xo2;
1161 let Inst{29} = DCMX{6};
1162 let Inst{30} = XB{5};
1163 let Inst{31} = XT{5};
1166 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1167 InstrItinClass itin, list<dag> pattern>
1168 : I<opcode, OOL, IOL, asmstr, itin> {
1173 let Pattern = pattern;
1175 let Inst{6-10} = XT{4-0};
1176 let Inst{11-15} = XA{4-0};
1177 let Inst{16-20} = XB{4-0};
1178 let Inst{21-28} = xo;
1179 let Inst{29} = XA{5};
1180 let Inst{30} = XB{5};
1181 let Inst{31} = XT{5};
1184 class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1185 InstrItinClass itin, list<dag> pattern>
1186 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1191 class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1192 InstrItinClass itin, list<dag> pattern>
1193 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1198 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1199 InstrItinClass itin, list<dag> pattern>
1200 : I<opcode, OOL, IOL, asmstr, itin> {
1205 let Pattern = pattern;
1209 let Inst{11-15} = XA{4-0};
1210 let Inst{16-20} = XB{4-0};
1211 let Inst{21-28} = xo;
1212 let Inst{29} = XA{5};
1213 let Inst{30} = XB{5};
1217 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1218 InstrItinClass itin, list<dag> pattern>
1219 : I<opcode, OOL, IOL, asmstr, itin> {
1225 let Pattern = pattern;
1227 let Inst{6-10} = XT{4-0};
1228 let Inst{11-15} = XA{4-0};
1229 let Inst{16-20} = XB{4-0};
1231 let Inst{22-23} = D;
1232 let Inst{24-28} = xo;
1233 let Inst{29} = XA{5};
1234 let Inst{30} = XB{5};
1235 let Inst{31} = XT{5};
1238 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
1239 InstrItinClass itin, list<dag> pattern>
1240 : I<opcode, OOL, IOL, asmstr, itin> {
1245 let Pattern = pattern;
1247 bit RC = 0; // set by isDOT
1249 let Inst{6-10} = XT{4-0};
1250 let Inst{11-15} = XA{4-0};
1251 let Inst{16-20} = XB{4-0};
1253 let Inst{22-28} = xo;
1254 let Inst{29} = XA{5};
1255 let Inst{30} = XB{5};
1256 let Inst{31} = XT{5};
1259 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
1260 InstrItinClass itin, list<dag> pattern>
1261 : I<opcode, OOL, IOL, asmstr, itin> {
1267 let Pattern = pattern;
1269 let Inst{6-10} = XT{4-0};
1270 let Inst{11-15} = XA{4-0};
1271 let Inst{16-20} = XB{4-0};
1272 let Inst{21-25} = XC{4-0};
1273 let Inst{26-27} = xo;
1274 let Inst{28} = XC{5};
1275 let Inst{29} = XA{5};
1276 let Inst{30} = XB{5};
1277 let Inst{31} = XT{5};
1280 // DCB_Form - Form X instruction, used for dcb* instructions.
1281 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
1282 InstrItinClass itin, list<dag> pattern>
1283 : I<31, OOL, IOL, asmstr, itin> {
1287 let Pattern = pattern;
1289 let Inst{6-10} = immfield;
1290 let Inst{11-15} = A;
1291 let Inst{16-20} = B;
1292 let Inst{21-30} = xo;
1296 class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
1297 InstrItinClass itin, list<dag> pattern>
1298 : I<31, OOL, IOL, asmstr, itin> {
1303 let Pattern = pattern;
1305 let Inst{6-10} = TH;
1306 let Inst{11-15} = A;
1307 let Inst{16-20} = B;
1308 let Inst{21-30} = xo;
1312 // DSS_Form - Form X instruction, used for altivec dss* instructions.
1313 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
1314 InstrItinClass itin, list<dag> pattern>
1315 : I<31, OOL, IOL, asmstr, itin> {
1320 let Pattern = pattern;
1324 let Inst{9-10} = STRM;
1325 let Inst{11-15} = A;
1326 let Inst{16-20} = B;
1327 let Inst{21-30} = xo;
1332 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1333 InstrItinClass itin, list<dag> pattern>
1334 : I<opcode, OOL, IOL, asmstr, itin> {
1339 let Pattern = pattern;
1341 let Inst{6-10} = CRD;
1342 let Inst{11-15} = CRA;
1343 let Inst{16-20} = CRB;
1344 let Inst{21-30} = xo;
1348 class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1349 InstrItinClass itin, list<dag> pattern>
1350 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1356 class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1357 InstrItinClass itin, list<dag> pattern>
1358 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1367 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1368 InstrItinClass itin, list<dag> pattern>
1369 : I<opcode, OOL, IOL, asmstr, itin> {
1372 let Pattern = pattern;
1374 let Inst{6-10} = CRD;
1375 let Inst{11-15} = CRD;
1376 let Inst{16-20} = CRD;
1377 let Inst{21-30} = xo;
1381 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
1382 InstrItinClass itin, list<dag> pattern>
1383 : I<opcode, OOL, IOL, asmstr, itin> {
1388 let Pattern = pattern;
1390 let Inst{6-10} = BO;
1391 let Inst{11-15} = BI;
1392 let Inst{16-18} = 0;
1393 let Inst{19-20} = BH;
1394 let Inst{21-30} = xo;
1398 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1399 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1400 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1401 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1405 let BI{0-1} = BIBO{5-6};
1406 let BI{2-4} = CR{0-2};
1410 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1411 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1412 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1417 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1418 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1419 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1425 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1426 InstrItinClass itin>
1427 : I<opcode, OOL, IOL, asmstr, itin> {
1433 let Inst{11-13} = BFA;
1434 let Inst{14-15} = 0;
1435 let Inst{16-20} = 0;
1436 let Inst{21-30} = xo;
1440 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1441 InstrItinClass itin>
1442 : I<opcode, OOL, IOL, asmstr, itin> {
1451 let Inst{11-14} = 0;
1453 let Inst{16-19} = U;
1455 let Inst{21-30} = xo;
1459 class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1460 InstrItinClass itin, list<dag> pattern>
1461 : I<opcode, OOL, IOL, asmstr, itin> {
1464 let Pattern = pattern;
1468 let Inst{21-30} = xo;
1472 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1473 bits<6> opcode2, bits<2> xo2,
1474 dag OOL, dag IOL, string asmstr,
1475 InstrItinClass itin, list<dag> pattern>
1476 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1484 let Pattern = pattern;
1486 let Inst{6-10} = BO;
1487 let Inst{11-15} = BI;
1488 let Inst{16-18} = 0;
1489 let Inst{19-20} = BH;
1490 let Inst{21-30} = xo1;
1493 let Inst{38-42} = RST;
1494 let Inst{43-47} = DS_RA{18-14}; // Register #
1495 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1496 let Inst{62-63} = xo2;
1499 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1500 bits<5> bo, bits<5> bi, bit lk,
1501 bits<6> opcode2, bits<2> xo2,
1502 dag OOL, dag IOL, string asmstr,
1503 InstrItinClass itin, list<dag> pattern>
1504 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1505 OOL, IOL, asmstr, itin, pattern> {
1512 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1513 InstrItinClass itin>
1514 : I<opcode, OOL, IOL, asmstr, itin> {
1518 let Inst{6-10} = RT;
1519 let Inst{11} = SPR{4};
1520 let Inst{12} = SPR{3};
1521 let Inst{13} = SPR{2};
1522 let Inst{14} = SPR{1};
1523 let Inst{15} = SPR{0};
1524 let Inst{16} = SPR{9};
1525 let Inst{17} = SPR{8};
1526 let Inst{18} = SPR{7};
1527 let Inst{19} = SPR{6};
1528 let Inst{20} = SPR{5};
1529 let Inst{21-30} = xo;
1533 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1534 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1535 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1539 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1540 InstrItinClass itin>
1541 : I<opcode, OOL, IOL, asmstr, itin> {
1544 let Inst{6-10} = RT;
1545 let Inst{11-20} = 0;
1546 let Inst{21-30} = xo;
1550 class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1551 InstrItinClass itin, list<dag> pattern>
1552 : I<opcode, OOL, IOL, asmstr, itin> {
1555 let Pattern = pattern;
1557 let Inst{6-10} = RT;
1558 let Inst{11-20} = Entry;
1559 let Inst{21-30} = xo;
1563 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1564 InstrItinClass itin>
1565 : I<opcode, OOL, IOL, asmstr, itin> {
1569 let Inst{6-10} = rS;
1571 let Inst{12-19} = FXM;
1573 let Inst{21-30} = xo;
1577 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1578 InstrItinClass itin>
1579 : I<opcode, OOL, IOL, asmstr, itin> {
1583 let Inst{6-10} = ST;
1585 let Inst{12-19} = FXM;
1587 let Inst{21-30} = xo;
1591 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1592 InstrItinClass itin>
1593 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1595 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1596 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1597 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1602 // This is probably 1.7.9, but I don't have the reference that uses this
1603 // numbering scheme...
1604 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1605 InstrItinClass itin, list<dag>pattern>
1606 : I<opcode, OOL, IOL, asmstr, itin> {
1610 bit RC = 0; // set by isDOT
1611 let Pattern = pattern;
1614 let Inst{7-14} = FM;
1616 let Inst{16-20} = rT;
1617 let Inst{21-30} = xo;
1621 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1622 InstrItinClass itin, list<dag>pattern>
1623 : I<opcode, OOL, IOL, asmstr, itin> {
1629 bit RC = 0; // set by isDOT
1630 let Pattern = pattern;
1633 let Inst{7-14} = FLM;
1635 let Inst{16-20} = FRB;
1636 let Inst{21-30} = xo;
1640 // 1.7.10 XS-Form - SRADI.
1641 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1642 InstrItinClass itin, list<dag> pattern>
1643 : I<opcode, OOL, IOL, asmstr, itin> {
1648 bit RC = 0; // set by isDOT
1649 let Pattern = pattern;
1651 let Inst{6-10} = RS;
1652 let Inst{11-15} = A;
1653 let Inst{16-20} = SH{4,3,2,1,0};
1654 let Inst{21-29} = xo;
1655 let Inst{30} = SH{5};
1660 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1661 InstrItinClass itin, list<dag> pattern>
1662 : I<opcode, OOL, IOL, asmstr, itin> {
1667 let Pattern = pattern;
1669 bit RC = 0; // set by isDOT
1671 let Inst{6-10} = RT;
1672 let Inst{11-15} = RA;
1673 let Inst{16-20} = RB;
1675 let Inst{22-30} = xo;
1679 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1680 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1681 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1686 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1687 InstrItinClass itin, list<dag> pattern>
1688 : I<opcode, OOL, IOL, asmstr, itin> {
1694 let Pattern = pattern;
1696 bit RC = 0; // set by isDOT
1698 let Inst{6-10} = FRT;
1699 let Inst{11-15} = FRA;
1700 let Inst{16-20} = FRB;
1701 let Inst{21-25} = FRC;
1702 let Inst{26-30} = xo;
1706 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1707 InstrItinClass itin, list<dag> pattern>
1708 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1712 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1713 InstrItinClass itin, list<dag> pattern>
1714 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1718 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1719 InstrItinClass itin, list<dag> pattern>
1720 : I<opcode, OOL, IOL, asmstr, itin> {
1726 let Pattern = pattern;
1728 let Inst{6-10} = RT;
1729 let Inst{11-15} = RA;
1730 let Inst{16-20} = RB;
1731 let Inst{21-25} = COND;
1732 let Inst{26-30} = xo;
1737 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1738 InstrItinClass itin, list<dag> pattern>
1739 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1745 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1746 InstrItinClass itin, list<dag> pattern>
1747 : I<opcode, OOL, IOL, asmstr, itin> {
1754 let Pattern = pattern;
1756 bit RC = 0; // set by isDOT
1758 let Inst{6-10} = RS;
1759 let Inst{11-15} = RA;
1760 let Inst{16-20} = RB;
1761 let Inst{21-25} = MB;
1762 let Inst{26-30} = ME;
1766 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1767 InstrItinClass itin, list<dag> pattern>
1768 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1772 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1773 InstrItinClass itin, list<dag> pattern>
1774 : I<opcode, OOL, IOL, asmstr, itin> {
1780 let Pattern = pattern;
1782 bit RC = 0; // set by isDOT
1784 let Inst{6-10} = RS;
1785 let Inst{11-15} = RA;
1786 let Inst{16-20} = SH{4,3,2,1,0};
1787 let Inst{21-26} = MBE{4,3,2,1,0,5};
1788 let Inst{27-29} = xo;
1789 let Inst{30} = SH{5};
1793 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1794 InstrItinClass itin, list<dag> pattern>
1795 : I<opcode, OOL, IOL, asmstr, itin> {
1801 let Pattern = pattern;
1803 bit RC = 0; // set by isDOT
1805 let Inst{6-10} = RS;
1806 let Inst{11-15} = RA;
1807 let Inst{16-20} = RB;
1808 let Inst{21-26} = MBE{4,3,2,1,0,5};
1809 let Inst{27-30} = xo;
1816 // VAForm_1 - DACB ordering.
1817 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1818 InstrItinClass itin, list<dag> pattern>
1819 : I<4, OOL, IOL, asmstr, itin> {
1825 let Pattern = pattern;
1827 let Inst{6-10} = VD;
1828 let Inst{11-15} = VA;
1829 let Inst{16-20} = VB;
1830 let Inst{21-25} = VC;
1831 let Inst{26-31} = xo;
1834 // VAForm_1a - DABC ordering.
1835 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1836 InstrItinClass itin, list<dag> pattern>
1837 : I<4, OOL, IOL, asmstr, itin> {
1843 let Pattern = pattern;
1845 let Inst{6-10} = VD;
1846 let Inst{11-15} = VA;
1847 let Inst{16-20} = VB;
1848 let Inst{21-25} = VC;
1849 let Inst{26-31} = xo;
1852 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1853 InstrItinClass itin, list<dag> pattern>
1854 : I<4, OOL, IOL, asmstr, itin> {
1860 let Pattern = pattern;
1862 let Inst{6-10} = VD;
1863 let Inst{11-15} = VA;
1864 let Inst{16-20} = VB;
1866 let Inst{22-25} = SH;
1867 let Inst{26-31} = xo;
1871 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1872 InstrItinClass itin, list<dag> pattern>
1873 : I<4, OOL, IOL, asmstr, itin> {
1878 let Pattern = pattern;
1880 let Inst{6-10} = VD;
1881 let Inst{11-15} = VA;
1882 let Inst{16-20} = VB;
1883 let Inst{21-31} = xo;
1886 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1887 InstrItinClass itin, list<dag> pattern>
1888 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1894 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1895 InstrItinClass itin, list<dag> pattern>
1896 : I<4, OOL, IOL, asmstr, itin> {
1900 let Pattern = pattern;
1902 let Inst{6-10} = VD;
1903 let Inst{11-15} = 0;
1904 let Inst{16-20} = VB;
1905 let Inst{21-31} = xo;
1908 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1909 InstrItinClass itin, list<dag> pattern>
1910 : I<4, OOL, IOL, asmstr, itin> {
1914 let Pattern = pattern;
1916 let Inst{6-10} = VD;
1917 let Inst{11-15} = IMM;
1918 let Inst{16-20} = 0;
1919 let Inst{21-31} = xo;
1922 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1923 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1924 InstrItinClass itin, list<dag> pattern>
1925 : I<4, OOL, IOL, asmstr, itin> {
1928 let Pattern = pattern;
1930 let Inst{6-10} = VD;
1931 let Inst{11-15} = 0;
1932 let Inst{16-20} = 0;
1933 let Inst{21-31} = xo;
1936 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1937 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1938 InstrItinClass itin, list<dag> pattern>
1939 : I<4, OOL, IOL, asmstr, itin> {
1942 let Pattern = pattern;
1945 let Inst{11-15} = 0;
1946 let Inst{16-20} = VB;
1947 let Inst{21-31} = xo;
1950 // e.g. [PO VRT EO VRB XO]
1951 class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
1952 string asmstr, InstrItinClass itin, list<dag> pattern>
1953 : I<4, OOL, IOL, asmstr, itin> {
1957 let Pattern = pattern;
1959 let Inst{6-10} = RD;
1960 let Inst{11-15} = eo;
1961 let Inst{16-20} = VB;
1962 let Inst{21-31} = xo;
1965 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
1966 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
1967 InstrItinClass itin, list<dag> pattern>
1968 : I<4, OOL, IOL, asmstr, itin> {
1974 let Pattern = pattern;
1976 let Inst{6-10} = VD;
1977 let Inst{11-15} = VA;
1979 let Inst{17-20} = SIX;
1980 let Inst{21-31} = xo;
1983 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
1984 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
1985 InstrItinClass itin, list<dag> pattern>
1986 : I<4, OOL, IOL, asmstr, itin> {
1990 let Pattern = pattern;
1992 let Inst{6-10} = VD;
1993 let Inst{11-15} = VA;
1994 let Inst{16-20} = 0;
1995 let Inst{21-31} = xo;
1999 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
2000 InstrItinClass itin, list<dag> pattern>
2001 : I<4, OOL, IOL, asmstr, itin> {
2007 let Pattern = pattern;
2009 let Inst{6-10} = VD;
2010 let Inst{11-15} = VA;
2011 let Inst{16-20} = VB;
2013 let Inst{22-31} = xo;
2016 // VX-Form: [PO VRT EO VRB 1 PS XO]
2017 class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
2018 dag OOL, dag IOL, string asmstr,
2019 InstrItinClass itin, list<dag> pattern>
2020 : I<4, OOL, IOL, asmstr, itin> {
2025 let Pattern = pattern;
2027 let Inst{6-10} = VD;
2028 let Inst{11-15} = eo;
2029 let Inst{16-20} = VB;
2032 let Inst{23-31} = xo;
2035 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
2036 class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
2037 InstrItinClass itin, list<dag> pattern>
2038 : I<4, OOL, IOL, asmstr, itin> {
2044 let Pattern = pattern;
2046 let Inst{6-10} = VD;
2047 let Inst{11-15} = VA;
2048 let Inst{16-20} = VB;
2051 let Inst{23-31} = xo;
2054 // Z23-Form (used by QPX)
2055 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2056 InstrItinClass itin, list<dag> pattern>
2057 : I<opcode, OOL, IOL, asmstr, itin> {
2063 let Pattern = pattern;
2065 bit RC = 0; // set by isDOT
2067 let Inst{6-10} = FRT;
2068 let Inst{11-15} = FRA;
2069 let Inst{16-20} = FRB;
2070 let Inst{21-22} = idx;
2071 let Inst{23-30} = xo;
2075 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2076 InstrItinClass itin, list<dag> pattern>
2077 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
2081 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
2082 InstrItinClass itin, list<dag> pattern>
2083 : I<opcode, OOL, IOL, asmstr, itin> {
2087 let Pattern = pattern;
2089 bit RC = 0; // set by isDOT
2091 let Inst{6-10} = FRT;
2092 let Inst{11-22} = idx;
2093 let Inst{23-30} = xo;
2097 //===----------------------------------------------------------------------===//
2098 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
2099 : I<0, OOL, IOL, asmstr, NoItinerary> {
2100 let isCodeGenOnly = 1;
2102 let Pattern = pattern;
2104 let hasNoSchedulingInfo = 1;